Here is a list of all struct and union fields with links to the structures/unions they belong to:

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• Oai3Gate() : RTLIL::Module
• Oai4Gate() : RTLIL::Module
• ObjIterator() : RTLIL::ObjIterator< T >
• ObjRange() : RTLIL::ObjRange< T >
• OccLists() : Minisat::OccLists< K, Vec, Deleted, MkIndex >
• occs : Minisat::OccLists< K, Vec, Deleted, MkIndex >
• occurs : Minisat::SimpSolver
• offset : AST::AstNode::varinfo_t , ModIndex::PortInfo , ModWalker::PortBit , RTLIL::SigBit , RTLIL::SigChunk , SatHelper::ModelBlockInfo
• ok : Minisat::Solver , RTLIL::IdString::destruct_guard_t
• okay() : Minisat::Solver
• onehot() : ezSAT
• OpAnd : ezSAT
• operator BigUnsigned() : BigUnsignedInABase
• operator bool() : Minisat::BoolOption
• operator bool &() : Minisat::BoolOption
• operator const char *() : Minisat::StringOption
• operator const char *&() : Minisat::StringOption
• operator const Lit *() : Minisat::Clause
• operator double() : Minisat::DoubleOption
• operator double &() : Minisat::DoubleOption
• operator ezSAT::_V() : ezSATbit
• operator int() : ezSATbit
• operator int32_t() : Minisat::IntOption
• operator int32_t &() : Minisat::IntOption
• operator int64_t() : Minisat::Int64Option
• operator int64_t &() : Minisat::Int64Option
• operator std::set< T >() : RTLIL::ObjRange< T >
• operator std::string() : BigUnsignedInABase
• operator std::vector< int >() : ezSATbit , ezSATvec
• operator std::vector< RTLIL::SigBit >() : RTLIL::SigSpec
• operator std::vector< RTLIL::SigChunk >() : RTLIL::SigSpec
• operator std::vector< T >() : RTLIL::ObjRange< T >
• operator T *() : Minisat::vec< T, _Size >
• operator!=() : AST::AstNode , BigInteger , BigUnsigned , BigUnsignedInABase , ezSATbit , ezSATvec , Minisat::ClauseIterator , Minisat::lbool , Minisat::Lit , Minisat::Solver::Watcher , Minisat::TrailIterator , NumberlikeArray< Blk > , RTLIL::Const , RTLIL::IdString , RTLIL::ObjIterator< T > , RTLIL::SigBit , RTLIL::SigChunk , RTLIL::SigSpec , RTLIL::SigSpecConstIterator , RTLIL::SigSpecIterator
• operator%() : BigInteger , BigUnsigned
• operator%=() : BigInteger , BigUnsigned
• operator&() : BigUnsigned , ezSATbit , ezSATvec
• operator&&() : Minisat::lbool
• operator&=() : BigUnsigned
• operator()() : CountBitUsage , Minisat::CMap< T >::CRefHash , Minisat::DeepEqual< K > , Minisat::DeepHash< K > , Minisat::Equal< K > , Minisat::Hash< K > , Minisat::LessThan_default< T > , Minisat::MkIndexDefault< T > , Minisat::MkIndexLit , Minisat::Option::OptionLt , Minisat::SimpSolver::ClauseDeleted , Minisat::SimpSolver::ElimLt , Minisat::Solver::VarOrderLt , Minisat::Solver::WatcherDeleted , OptShareWorker::CompareCells , reduceDB_lt , RTLIL::IdString::char_ptr_cmp , RTLIL::IdString::compare_ptr_by_name< T > , RTLIL::sort_by_id_str , RTLIL::sort_by_name_id< T > , RTLIL::sort_by_name_str< T > , SetundefWorker , SigMap , SplitnetsWorker , WireInfoOrder , xorshift128
• operator*() : BigInteger , BigUnsigned , Minisat::ClauseIterator , Minisat::StreamBuffer , Minisat::TrailIterator , RTLIL::ObjIterator< T > , RTLIL::SigSpecConstIterator , RTLIL::SigSpecIterator , statdata_t
• operator*=() : BigInteger , BigUnsigned
• operator+() : BigInteger , BigUnsigned , ezSATvec , statdata_t
• operator++() : BigInteger , BigUnsigned , Minisat::ClauseIterator , Minisat::StreamBuffer , Minisat::TrailIterator , RTLIL::ObjIterator< T > , RTLIL::SigSpecConstIterator , RTLIL::SigSpecIterator
• operator+=() : BigInteger , BigUnsigned
• operator-() : BigInteger , BigUnsigned , ezSATvec
• operator--() : BigInteger , BigUnsigned
• operator-=() : BigInteger , BigUnsigned
• operator/() : BigInteger , BigUnsigned
• operator/=() : BigInteger , BigUnsigned
• operator<() : BigInteger , BigUnsigned , blockgeom_t , equiv_bit_t , ezSATvec , Minisat::Lit , ModIndex::PortInfo , ModWalker::PortBit , RTLIL::Const , RTLIL::IdString , RTLIL::SigBit , RTLIL::SigChunk , RTLIL::SigSpec , SatHelper::ModelBlockInfo , SubCircuit::Graph::BitRef , SubCircuit::SolverWorker::DiBit , SubCircuit::SolverWorker::DiEdge , SubCircuit::SolverWorker::DiNode , SubCircuit::SolverWorker::NodeSet
• operator<<() : BigUnsigned , ezSATvec
• operator<<=() : BigUnsigned
• operator<=() : BigInteger , BigUnsigned , ezSATvec
• operator=() : BigInteger , BigUnsigned , BigUnsignedInABase , Minisat::BoolOption , Minisat::DoubleOption , Minisat::Int64Option , Minisat::IntOption , Minisat::Map< K, D, H, E > , Minisat::StringOption , Minisat::vec< T, _Size > , NumberlikeArray< Blk > , RTLIL::Cell , RTLIL::IdString , RTLIL::ObjIterator< T > , RTLIL::SigSpec , RTLIL::Wire , SigMap , stackmap< Key, T, Compare >
• operator==() : AST::AstNode , BigInteger , BigUnsigned , BigUnsignedInABase , ezSATbit , ezSATvec , Minisat::ClauseIterator , Minisat::lbool , Minisat::Lit , Minisat::Solver::Watcher , Minisat::TrailIterator , NumberlikeArray< Blk > , RTLIL::Const , RTLIL::IdString , RTLIL::SigBit , RTLIL::SigChunk , RTLIL::SigSpec , RTLIL::SigSpecConstIterator , RTLIL::SigSpecIterator
• operator>() : BigInteger , BigUnsigned , ezSATvec
• operator>=() : BigInteger , BigUnsigned , ezSATvec
• operator>>() : BigUnsigned , ezSATvec
• operator>>=() : BigUnsigned
• operator[]() : Minisat::Clause , Minisat::ClauseAllocator , Minisat::CMap< T > , Minisat::Heap< K, Comp, MkIndex > , Minisat::IntMap< K, V, MkIndex > , Minisat::IntSet< K, MkIndex > , Minisat::Map< K, D, H, E > , Minisat::OccLists< K, Vec, Deleted, MkIndex > , Minisat::Queue< T > , Minisat::RegionAllocator< T > , Minisat::vec< T, _Size > , RTLIL::IdString , RTLIL::SigSpec
• operator^() : BigUnsigned , ezSATbit , ezSATvec , Minisat::lbool
• operator^=() : BigUnsigned
• operator|() : BigUnsigned , ezSATbit , ezSATvec
• operator|=() : BigUnsigned
• operator||() : Minisat::lbool
• operator~() : ezSATbit , ezSATvec
• OpId : ezSAT
• OpIFF : ezSAT
• OpITE : ezSAT
• OpNot : ezSAT
• OpOr : ezSAT
• opt_aggressive : ShareWorkerConfig
• opt_alias_inputs() : FsmOpt
• opt_const_and_unused_inputs() : FsmOpt
• opt_fast : ShareWorkerConfig
• opt_feedback_inputs() : FsmOpt
• opt_find_dont_care() : FsmOpt
• opt_find_dont_care_worker() : FsmOpt
• opt_force : ShareWorkerConfig
• opt_mux() : OptReduceWorker
• opt_mux_bits() : OptReduceWorker
• opt_name : SubmodWorker
• opt_reduce() : OptReduceWorker
• opt_unreachable_states() : FsmOpt
• opt_unused_outputs() : FsmOpt
• OptCleanPass() : OptCleanPass
• OptConstPass() : OptConstPass
• optimize() : Macc , RTLIL::CaseRule , RTLIL::Design , RTLIL::Module , RTLIL::Selection
• optimize_activation_patterns() : ShareWorker
• optimize_fsm() : FsmData
• optimze_as_needed() : FsmExpand
• Option() : Minisat::Option
• OptMuxtreePass() : OptMuxtreePass
• OptMuxtreeWorker() : OptMuxtreeWorker
• OptPass() : OptPass
• OptReducePass() : OptReducePass
• OptReduceWorker() : OptReduceWorker
• OptRmdffPass() : OptRmdffPass
• OptSharePass() : OptSharePass
• OptShareWorker() : OptShareWorker
• OpXor : ezSAT
• OR() : ezSAT
• Or() : RTLIL::Module
• order_heap : Minisat::Solver
• ordered() : ezSAT
• OrGate() : RTLIL::Module
• out : ShowWorker::net_conn
• out_bits : PerformReduction
• out_depth : PerformReduction
• out_inverted : PerformReduction
• output : generate_port_decl_t
• outputs : CellType
• outputSignals : AST_INTERNAL::ProcessGenerator