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Data Structures | Public Member Functions | Data Fields
SubmodWorker Struct Reference
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Data Structures

struct  SubModule
 
struct  wire_flags_t
 

Public Member Functions

void flag_wire (RTLIL::Wire *wire, bool create, bool set_int_driven, bool set_int_used, bool set_ext_driven, bool set_ext_used)
 
void flag_signal (const RTLIL::SigSpec &sig, bool create, bool set_int_driven, bool set_int_used, bool set_ext_driven, bool set_ext_used)
 
void handle_submodule (SubModule &submod)
 
 SubmodWorker (RTLIL::Design *design, RTLIL::Module *module, std::string opt_name=std::string())
 

Data Fields

CellTypes ct
 
RTLIL::Design * design
 
RTLIL::Module * module
 
std::string opt_name
 
std::map< std::string, SubModule > submodules
 
std::map< RTLIL::Wire
*, wire_flags_t > 		wire_flags
 
bool flag_found_something
 

Detailed Description

Definition at line 30 of file submod.cc.

Constructor & Destructor Documentation

SubmodWorker::SubmodWorker ( RTLIL::Design *  design,
RTLIL::Module *  module,
std::string  opt_name = std::string() 
)
inline

Definition at line 194 of file submod.cc.

194  : design(design), module(module), opt_name(opt_name)
195  {
196  if (!design->selected_whole_module(module->name) && opt_name.empty())
197  return;
198 
199  if (module->processes.size() > 0) {
200  log("Skipping module %s as it contains processes (run 'proc' pass first).\n", module->name.c_str());
201  return;
202  }
203 
204  if (module->memories.size() > 0) {
205  log("Skipping module %s as it contains memories (run 'memory' pass first).\n", module->name.c_str());
206  return;
207  }
208 
209  ct.setup_internals();
210  ct.setup_internals_mem();
211  ct.setup_stdcells();
212  ct.setup_stdcells_mem();
213  ct.setup_design(design);
214 
215  if (opt_name.empty())
216  {
217  for (auto &it : module->wires_)
218  it.second->attributes.erase("\\submod");
219 
220  for (auto &it : module->cells_)
221  {
222  RTLIL::Cell *cell = it.second;
223  if (cell->attributes.count("\\submod") == 0 || cell->attributes["\\submod"].bits.size() == 0) {
224  cell->attributes.erase("\\submod");
225  continue;
226  }
227 
228  std::string submod_str = cell->attributes["\\submod"].decode_string();
229  cell->attributes.erase("\\submod");
230 
231  if (submodules.count(submod_str) == 0) {
232  submodules[submod_str].name = submod_str;
233  submodules[submod_str].full_name = module->name.str() + "_" + submod_str;
234  while (design->modules_.count(submodules[submod_str].full_name) != 0 ||
235  module->count_id(submodules[submod_str].full_name) != 0)
236  submodules[submod_str].full_name += "_";
237  }
238 
239  submodules[submod_str].cells.insert(cell);
240  }
241  }
242  else
243  {
244  for (auto &it : module->cells_)
245  {
246  RTLIL::Cell *cell = it.second;
247  if (!design->selected(module, cell))
248  continue;
249  submodules[opt_name].name = opt_name;
250  submodules[opt_name].full_name = RTLIL::escape_id(opt_name);
251  submodules[opt_name].cells.insert(cell);
252  }
253 
254  if (submodules.size() == 0)
255  log("Nothing selected -> do nothing.\n");
256  }
257 
258  for (auto &it : submodules)
259  handle_submodule(it.second);
260  }
RTLIL::IdString::c_str
const char * c_str() const
Definition: rtlil.h:178
RTLIL::Design::selected
bool selected(T1 *module) const
Definition: rtlil.h:551
RTLIL::IdString::str
std::string str() const
Definition: rtlil.h:182
CellTypes::setup_stdcells
void setup_stdcells()
Definition: celltypes.h:132
SubmodWorker::module
RTLIL::Module * module
Definition: submod.cc:34
CellTypes::setup_internals_mem
void setup_internals_mem()
Definition: celltypes.h:115
RTLIL::Module::wires_
std::map< RTLIL::IdString, RTLIL::Wire * > wires_
Definition: rtlil.h:595
RTLIL::Module::memories
std::map< RTLIL::IdString, RTLIL::Memory * > memories
Definition: rtlil.h:601
SubmodWorker::handle_submodule
void handle_submodule(SubModule &submod)
Definition: submod.cc:78
RTLIL::escape_id
static std::string escape_id(std::string str)
Definition: rtlil.h:251
RTLIL::Module::name
RTLIL::IdString name
Definition: rtlil.h:599
RTLIL::Design::selected_whole_module
bool selected_whole_module(RTLIL::IdString mod_name) const
Definition: rtlil.cc:388
RTLIL::Module::processes
std::map< RTLIL::IdString, RTLIL::Process * > processes
Definition: rtlil.h:602
RTLIL::Module::count_id
virtual size_t count_id(RTLIL::IdString id)
Definition: rtlil.cc:472
RTLIL::Design::modules_
std::map< RTLIL::IdString, RTLIL::Module * > modules_
Definition: rtlil.h:507
SubmodWorker::submodules
std::map< std::string, SubModule > submodules
Definition: submod.cc:43
RTLIL::Module::cells_
std::map< RTLIL::IdString, RTLIL::Cell * > cells_
Definition: rtlil.h:596
log
void log(const char *format,...)
Definition: log.cc:180
CellTypes::setup_internals
void setup_internals()
Definition: celltypes.h:83
SubmodWorker::opt_name
std::string opt_name
Definition: submod.cc:35
CellTypes::setup_design
void setup_design(RTLIL::Design *design)
Definition: celltypes.h:77
CellTypes::setup_stdcells_mem
void setup_stdcells_mem()
Definition: celltypes.h:149
SubmodWorker::design
RTLIL::Design * design
Definition: submod.cc:33
SubmodWorker::ct
CellTypes ct
Definition: submod.cc:32

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Member Function Documentation

void SubmodWorker::flag_signal ( const RTLIL::SigSpec &  sig,
bool  create,
bool  set_int_driven,
bool  set_int_used,
bool  set_ext_driven,
bool  set_ext_used 
)
inline

Definition at line 71 of file submod.cc.

72  {
73  for (auto &c : sig.chunks())
74  if (c.wire != NULL)
75  flag_wire(c.wire, create, set_int_driven, set_int_used, set_ext_driven, set_ext_used);
76  }
SubmodWorker::flag_wire
void flag_wire(RTLIL::Wire *wire, bool create, bool set_int_driven, bool set_int_used, bool set_ext_driven, bool set_ext_used)
Definition: submod.cc:53
NULL
#define NULL
Definition: NumberlikeArray.hh:6
RTLIL::SigSpec::chunks
const std::vector< RTLIL::SigChunk > & chunks() const
Definition: rtlil.h:1016

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void SubmodWorker::flag_wire ( RTLIL::Wire *  wire,
bool  create,
bool  set_int_driven,
bool  set_int_used,
bool  set_ext_driven,
bool  set_ext_used 
)
inline

Definition at line 53 of file submod.cc.

54  {
55  if (wire_flags.count(wire) == 0) {
56  if (!create)
57  return;
58  wire_flags[wire] = wire_flags_t();
59  }
60  if (set_int_driven)
61  wire_flags[wire].is_int_driven = true;
62  if (set_int_used)
63  wire_flags[wire].is_int_used = true;
64  if (set_ext_driven)
65  wire_flags[wire].is_ext_driven = true;
66  if (set_ext_used)
67  wire_flags[wire].is_ext_used = true;
68  flag_found_something = true;
69  }
SubmodWorker::wire_flags
std::map< RTLIL::Wire *, wire_flags_t > wire_flags
Definition: submod.cc:50
SubmodWorker::flag_found_something
bool flag_found_something
Definition: submod.cc:51

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void SubmodWorker::handle_submodule ( SubModule &  submod)
inline

Definition at line 78 of file submod.cc.

79  {
80  log("Creating submodule %s (%s) of module %s.\n", submod.name.c_str(), submod.full_name.c_str(), module->name.c_str());
81 
82  wire_flags.clear();
83  for (RTLIL::Cell *cell : submod.cells) {
84  if (ct.cell_known(cell->type)) {
85  for (auto &conn : cell->connections())
86  flag_signal(conn.second, true, ct.cell_output(cell->type, conn.first), ct.cell_input(cell->type, conn.first), false, false);
87  } else {
88  log_warning("Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name.c_str(), cell->type.c_str());
89  for (auto &conn : cell->connections())
90  flag_signal(conn.second, true, true, true, false, false);
91  }
92  }
93  for (auto &it : module->cells_) {
94  RTLIL::Cell *cell = it.second;
95  if (submod.cells.count(cell) > 0)
96  continue;
97  if (ct.cell_known(cell->type)) {
98  for (auto &conn : cell->connections())
99  flag_signal(conn.second, false, false, false, ct.cell_output(cell->type, conn.first), ct.cell_input(cell->type, conn.first));
100  } else {
101  flag_found_something = false;
102  for (auto &conn : cell->connections())
103  flag_signal(conn.second, false, false, false, true, true);
104  if (flag_found_something)
105  log_warning("Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name.c_str(), cell->type.c_str());
106  }
107  }
108 
109  RTLIL::Module *new_mod = new RTLIL::Module;
110  new_mod->name = submod.full_name;
111  design->add(new_mod);
112  int auto_name_counter = 1;
113 
114  std::set<RTLIL::IdString> all_wire_names;
115  for (auto &it : wire_flags) {
116  all_wire_names.insert(it.first->name);
117  }
118 
119  for (auto &it : wire_flags)
120  {
121  RTLIL::Wire *wire = it.first;
122  wire_flags_t &flags = it.second;
123 
124  if (wire->port_input)
125  flags.is_ext_driven = true;
126  if (wire->port_output)
127  flags.is_ext_used = true;
128 
129  bool new_wire_port_input = false;
130  bool new_wire_port_output = false;
131 
132  if (flags.is_int_driven && flags.is_ext_used)
133  new_wire_port_output = true;
134  if (flags.is_ext_driven && flags.is_int_used)
135  new_wire_port_input = true;
136 
137  if (flags.is_int_driven && flags.is_ext_driven)
138  new_wire_port_input = true, new_wire_port_output = true;
139 
140  std::string new_wire_name = wire->name.str();
141  if (new_wire_port_input || new_wire_port_output) {
142  while (new_wire_name[0] == '$') {
143  std::string next_wire_name = stringf("\\n%d", auto_name_counter++);
144  if (all_wire_names.count(next_wire_name) == 0) {
145  all_wire_names.insert(next_wire_name);
146  new_wire_name = next_wire_name;
147  }
148  }
149  }
150 
151  RTLIL::Wire *new_wire = new_mod->addWire(new_wire_name, wire->width);
152  new_wire->port_input = new_wire_port_input;
153  new_wire->port_output = new_wire_port_output;
154  new_wire->start_offset = wire->start_offset;
155  new_wire->attributes = wire->attributes;
156 
157  if (new_wire->port_input && new_wire->port_output)
158  log(" signal %s: inout %s\n", wire->name.c_str(), new_wire->name.c_str());
159  else if (new_wire->port_input)
160  log(" signal %s: input %s\n", wire->name.c_str(), new_wire->name.c_str());
161  else if (new_wire->port_output)
162  log(" signal %s: output %s\n", wire->name.c_str(), new_wire->name.c_str());
163  else
164  log(" signal %s: internal\n", wire->name.c_str());
165 
166  flags.new_wire = new_wire;
167  }
168 
169  new_mod->fixup_ports();
170 
171  for (RTLIL::Cell *cell : submod.cells) {
172  RTLIL::Cell *new_cell = new_mod->addCell(cell->name, cell);
173  for (auto &conn : new_cell->connections_)
174  for (auto &bit : conn.second)
175  if (bit.wire != NULL) {
176  log_assert(wire_flags.count(bit.wire) > 0);
177  bit.wire = wire_flags[bit.wire].new_wire;
178  }
179  log(" cell %s (%s)\n", new_cell->name.c_str(), new_cell->type.c_str());
180  module->remove(cell);
181  }
182  submod.cells.clear();
183 
184  RTLIL::Cell *new_cell = module->addCell(submod.full_name, submod.full_name);
185  for (auto &it : wire_flags)
186  {
187  RTLIL::Wire *old_wire = it.first;
188  RTLIL::Wire *new_wire = it.second.new_wire;
189  if (new_wire->port_id > 0)
190  new_cell->setPort(new_wire->name, RTLIL::SigSpec(old_wire));
191  }
192  }
RTLIL::IdString::c_str
const char * c_str() const
Definition: rtlil.h:178
RTLIL::IdString::str
std::string str() const
Definition: rtlil.h:182
stringf
std::string stringf(const char *fmt,...)
Definition: yosys.cc:58
auto_name_counter
int auto_name_counter
Definition: verilog_backend.cc:41
log_warning
void log_warning(const char *format,...)
Definition: log.cc:196
SubmodWorker::module
RTLIL::Module * module
Definition: submod.cc:34
RTLIL::Module::addCell
RTLIL::Cell * addCell(RTLIL::IdString name, RTLIL::IdString type)
Definition: rtlil.cc:1353
RTLIL::Design::add
void add(RTLIL::Module *module)
Definition: rtlil.cc:259
SubmodWorker::wire_flags
std::map< RTLIL::Wire *, wire_flags_t > wire_flags
Definition: submod.cc:50
RTLIL::Cell::name
RTLIL::IdString name
Definition: rtlil.h:853
RTLIL::Cell::setPort
void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
Definition: rtlil.cc:1789
RTLIL::Wire::port_input
bool port_input
Definition: rtlil.h:827
RTLIL::Wire::width
int width
Definition: rtlil.h:826
RTLIL::Wire::port_id
int port_id
Definition: rtlil.h:826
RTLIL::Cell::type
RTLIL::IdString type
Definition: rtlil.h:854
RTLIL::Wire::port_output
bool port_output
Definition: rtlil.h:827
CellTypes::cell_known
bool cell_known(RTLIL::IdString type)
Definition: celltypes.h:188
CellTypes::cell_output
bool cell_output(RTLIL::IdString type, RTLIL::IdString port)
Definition: celltypes.h:193
RTLIL::Module::fixup_ports
void fixup_ports()
Definition: rtlil.cc:1312
log_assert
#define log_assert(_assert_expr_)
Definition: log.h:85
RTLIL::Module::addWire
RTLIL::Wire * addWire(RTLIL::IdString name, int width=1)
Definition: rtlil.cc:1331
RTLIL::Module::name
RTLIL::IdString name
Definition: rtlil.h:599
SubmodWorker::flag_found_something
bool flag_found_something
Definition: submod.cc:51
RTLIL::Wire::name
RTLIL::IdString name
Definition: rtlil.h:825
NULL
#define NULL
Definition: NumberlikeArray.hh:6
RTLIL::Module::cells_
std::map< RTLIL::IdString, RTLIL::Cell * > cells_
Definition: rtlil.h:596
RTLIL::Module::remove
void remove(const std::set< RTLIL::Wire * > &wires)
Definition: rtlil.cc:1158
log
void log(const char *format,...)
Definition: log.cc:180
RTLIL::Wire::start_offset
int start_offset
Definition: rtlil.h:826
CellTypes::cell_input
bool cell_input(RTLIL::IdString type, RTLIL::IdString port)
Definition: celltypes.h:199
RTLIL::Cell::connections_
std::map< RTLIL::IdString, RTLIL::SigSpec > connections_
Definition: rtlil.h:855
SubmodWorker::design
RTLIL::Design * design
Definition: submod.cc:33
SubmodWorker::ct
CellTypes ct
Definition: submod.cc:32
SubmodWorker::flag_signal
void flag_signal(const RTLIL::SigSpec &sig, bool create, bool set_int_driven, bool set_int_used, bool set_ext_driven, bool set_ext_used)
Definition: submod.cc:71
RTLIL::Cell::connections
const std::map< RTLIL::IdString, RTLIL::SigSpec > & connections() const
Definition: rtlil.cc:1814

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Field Documentation

CellTypes SubmodWorker::ct

Definition at line 32 of file submod.cc.

RTLIL::Design* SubmodWorker::design

Definition at line 33 of file submod.cc.

bool SubmodWorker::flag_found_something

Definition at line 51 of file submod.cc.

RTLIL::Module* SubmodWorker::module

Definition at line 34 of file submod.cc.

std::string SubmodWorker::opt_name

Definition at line 35 of file submod.cc.

std::map<std::string, SubModule> SubmodWorker::submodules

Definition at line 43 of file submod.cc.

std::map<RTLIL::Wire*, wire_flags_t> SubmodWorker::wire_flags

Definition at line 50 of file submod.cc.

The documentation for this struct was generated from the following file: