RTLIL::SigSpec Struct Reference

#include <rtlil.h>

Public Member Functions
	SigSpec ()
	SigSpec (const RTLIL::SigSpec &other)
	SigSpec (std::initializer_list< RTLIL::SigSpec > parts)
const RTLIL::SigSpec &	operator= (const RTLIL::SigSpec &other)
	SigSpec (const RTLIL::Const &value)
	SigSpec (const RTLIL::SigChunk &chunk)
	SigSpec (RTLIL::Wire *wire)
	SigSpec (RTLIL::Wire *wire, int offset, int width=1)
	SigSpec (const std::string &str)
	SigSpec (int val, int width=32)
	SigSpec (RTLIL::State bit, int width=1)
	SigSpec (RTLIL::SigBit bit, int width=1)
	SigSpec (std::vector< RTLIL::SigChunk > chunks)
	SigSpec (std::vector< RTLIL::SigBit > bits)
	SigSpec (std::set< RTLIL::SigBit > bits)
	SigSpec (bool bit)
	SigSpec (RTLIL::SigSpec &&other)
const RTLIL::SigSpec &	operator= (RTLIL::SigSpec &&other)
const std::vector < RTLIL::SigChunk > &	chunks () const
const std::vector < RTLIL::SigBit > &	bits () const
int	size () const
RTLIL::SigBit &	operator[] (int index)
const RTLIL::SigBit &	operator[] (int index) const
RTLIL::SigSpecIterator	begin ()
RTLIL::SigSpecIterator	end ()
RTLIL::SigSpecConstIterator	begin () const
RTLIL::SigSpecConstIterator	end () const
void	sort ()
void	sort_and_unify ()
void	replace (const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
void	replace (const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
void	replace (const std::map< RTLIL::SigBit, RTLIL::SigBit > &rules)
void	replace (const std::map< RTLIL::SigBit, RTLIL::SigBit > &rules, RTLIL::SigSpec *other) const
void	replace (int offset, const RTLIL::SigSpec &with)
void	remove (const RTLIL::SigSpec &pattern)
void	remove (const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
void	remove2 (const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
void	remove (const std::set< RTLIL::SigBit > &pattern)
void	remove (const std::set< RTLIL::SigBit > &pattern, RTLIL::SigSpec *other) const
void	remove2 (const std::set< RTLIL::SigBit > &pattern, RTLIL::SigSpec *other)
void	remove (int offset, int length=1)
void	remove_const ()
RTLIL::SigSpec	extract (const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other=NULL) const
RTLIL::SigSpec	extract (const std::set< RTLIL::SigBit > &pattern, const RTLIL::SigSpec *other=NULL) const
RTLIL::SigSpec	extract (int offset, int length=1) const
void	append (const RTLIL::SigSpec &signal)
void	append_bit (const RTLIL::SigBit &bit)
void	extend (int width, bool is_signed=false)
void	extend_u0 (int width, bool is_signed=false)
RTLIL::SigSpec	repeat (int num) const
bool	operator< (const RTLIL::SigSpec &other) const
bool	operator== (const RTLIL::SigSpec &other) const
bool	operator!= (const RTLIL::SigSpec &other) const
bool	is_wire () const
bool	is_chunk () const
bool	is_fully_const () const
bool	is_fully_def () const
bool	is_fully_undef () const
bool	has_marked_bits () const
bool	as_bool () const
int	as_int (bool is_signed=false) const
std::string	as_string () const
RTLIL::Const	as_const () const
RTLIL::Wire *	as_wire () const
RTLIL::SigChunk	as_chunk () const
bool	match (std::string pattern) const
std::set< RTLIL::SigBit >	to_sigbit_set () const
std::vector< RTLIL::SigBit >	to_sigbit_vector () const
std::map< RTLIL::SigBit, RTLIL::SigBit >	to_sigbit_map (const RTLIL::SigSpec &other) const
RTLIL::SigBit	to_single_sigbit () const
	operator std::vector< RTLIL::SigChunk > () const
	operator std::vector< RTLIL::SigBit > () const
void	check () const

Static Public Member Functions
static bool	parse (RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
static bool	parse_sel (RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
static bool	parse_rhs (const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)

Private Member Functions
void	pack () const
void	unpack () const
void	hash () const
bool	packed () const
void	inline_unpack () const

Private Attributes
int	width_
unsigned long	hash_
std::vector< RTLIL::SigChunk >	chunks_
std::vector< RTLIL::SigBit >	bits_

Detailed Description

Definition at line 961 of file rtlil.h.

Constructor & Destructor Documentation

RTLIL::SigSpec::SigSpec

(

)

Definition at line 2015 of file rtlil.cc.

{
    width_ = 0;
    hash_ = 0;
}

RTLIL::SigSpec::SigSpec

(

const RTLIL::SigSpec &

other

)

Definition at line 2021 of file rtlil.cc.

{
    *this = other;
}

RTLIL::SigSpec::SigSpec

(

std::initializer_list< RTLIL::SigSpec >

parts

)

Definition at line 2026 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.init.list");

    width_ = 0;
    hash_ = 0;

    std::vector<RTLIL::SigSpec> parts_vec(parts.begin(), parts.end());
    for (auto it = parts_vec.rbegin(); it != parts_vec.rend(); it++)
        append(*it);
}

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RTLIL::SigSpec::SigSpec

(

const RTLIL::Const &

value

)

Definition at line 2075 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.init.const");

    chunks_.push_back(RTLIL::SigChunk(value));
    width_ = chunks_.back().width;
    hash_ = 0;
    check();
}

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RTLIL::SigSpec::SigSpec

(

const RTLIL::SigChunk &

chunk

)

Definition at line 2085 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.init.chunk");

    chunks_.push_back(chunk);
    width_ = chunks_.back().width;
    hash_ = 0;
    check();
}

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RTLIL::SigSpec::SigSpec

(

RTLIL::Wire *

wire

)

Definition at line 2095 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.init.wire");

    chunks_.push_back(RTLIL::SigChunk(wire));
    width_ = chunks_.back().width;
    hash_ = 0;
    check();
}

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RTLIL::SigSpec::SigSpec	(	RTLIL::Wire *	wire,
		int	offset,
		int	width = 1
	)

Definition at line 2105 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.init.wire_part");

    chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
    width_ = chunks_.back().width;
    hash_ = 0;
    check();
}

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RTLIL::SigSpec::SigSpec

(

const std::string &

str

)

Definition at line 2115 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.init.str");

    chunks_.push_back(RTLIL::SigChunk(str));
    width_ = chunks_.back().width;
    hash_ = 0;
    check();
}

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RTLIL::SigSpec::SigSpec	(	int	val,
		int	width = 32
	)

Definition at line 2125 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.init.int");

    chunks_.push_back(RTLIL::SigChunk(val, width));
    width_ = width;
    hash_ = 0;
    check();
}

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RTLIL::SigSpec::SigSpec	(	RTLIL::State	bit,
		int	width = 1
	)

Definition at line 2135 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.init.state");

    chunks_.push_back(RTLIL::SigChunk(bit, width));
    width_ = width;
    hash_ = 0;
    check();
}

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RTLIL::SigSpec::SigSpec	(	RTLIL::SigBit	bit,
		int	width = 1
	)

Definition at line 2145 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.init.bit");

    if (bit.wire == NULL)
        chunks_.push_back(RTLIL::SigChunk(bit.data, width));
    else
        for (int i = 0; i < width; i++)
            chunks_.push_back(bit);
    width_ = width;
    hash_ = 0;
    check();
}

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RTLIL::SigSpec::SigSpec

(

std::vector< RTLIL::SigChunk >

chunks

)

Definition at line 2159 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.init.stdvec_chunks");

    width_ = 0;
    hash_ = 0;
    for (auto &c : chunks)
        append(c);
    check();
}

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RTLIL::SigSpec::SigSpec

(

std::vector< RTLIL::SigBit >

bits

)

Definition at line 2170 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.init.stdvec_bits");

    width_ = 0;
    hash_ = 0;
    for (auto &bit : bits)
        append_bit(bit);
    check();
}

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RTLIL::SigSpec::SigSpec

(

std::set< RTLIL::SigBit >

bits

)

Definition at line 2181 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.init.stdset_bits");

    width_ = 0;
    hash_ = 0;
    for (auto &bit : bits)
        append_bit(bit);
    check();
}

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RTLIL::SigSpec::SigSpec

(

bool

bit

)

Definition at line 2192 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.init.bool");

    width_ = 0;
    hash_ = 0;
    append_bit(bit);
    check();
}

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RTLIL::SigSpec::SigSpec ( RTLIL::SigSpec &&  other )

inline

Definition at line 1001 of file rtlil.h.

                                  {
        width_ = other.width_;
        hash_ = other.hash_;
        chunks_ = std::move(other.chunks_);
        bits_ = std::move(other.bits_);
    }

Member Function Documentation

void RTLIL::SigSpec::append

(

const RTLIL::SigSpec &

signal

)

Definition at line 2523 of file rtlil.cc.

{
    if (signal.width_ == 0)
        return;

    if (width_ == 0) {
        *this = signal;
        return;
    }

    cover("kernel.rtlil.sigspec.append");

    if (packed() != signal.packed()) {
        pack();
        signal.pack();
    }

    if (packed())
        for (auto &other_c : signal.chunks_)
        {
            auto &my_last_c = chunks_.back();
            if (my_last_c.wire == NULL && other_c.wire == NULL) {
                auto &this_data = my_last_c.data;
                auto &other_data = other_c.data;
                this_data.insert(this_data.end(), other_data.begin(), other_data.end());
                my_last_c.width += other_c.width;
            } else
            if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
                my_last_c.width += other_c.width;
            } else
                chunks_.push_back(other_c);
        }
    else
        bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());

    width_ += signal.width_;
    check();
}

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void RTLIL::SigSpec::append_bit

(

const RTLIL::SigBit &

bit

)

Definition at line 2562 of file rtlil.cc.

{
    if (packed())
    {
        cover("kernel.rtlil.sigspec.append_bit.packed");

        if (chunks_.size() == 0)
            chunks_.push_back(bit);
        else
            if (bit.wire == NULL)
                if (chunks_.back().wire == NULL) {
                    chunks_.back().data.push_back(bit.data);
                    chunks_.back().width++;
                } else
                    chunks_.push_back(bit);
            else
                if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
                    chunks_.back().width++;
                else
                    chunks_.push_back(bit);
    }
    else
    {
        cover("kernel.rtlil.sigspec.append_bit.unpacked");
        bits_.push_back(bit);
    }

    width_++;
    check();
}

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bool RTLIL::SigSpec::as_bool

(

)

const

Definition at line 2818 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.as_bool");

    pack();
    log_assert(is_fully_const() && GetSize(chunks_) <= 1);
    if (width_)
        return RTLIL::Const(chunks_[0].data).as_bool();
    return false;
}

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RTLIL::SigChunk RTLIL::SigSpec::as_chunk

(

)

const

Definition at line 2877 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.as_chunk");

    pack();
    log_assert(is_chunk());
    return chunks_[0];
}

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RTLIL::Const RTLIL::SigSpec::as_const

(

)

const

Definition at line 2857 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.as_const");

    pack();
    log_assert(is_fully_const() && GetSize(chunks_) <= 1);
    if (width_)
        return chunks_[0].data;
    return RTLIL::Const();
}

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int RTLIL::SigSpec::as_int

(

bool

is_signed = false

)

const

Definition at line 2829 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.as_int");

    pack();
    log_assert(is_fully_const() && GetSize(chunks_) <= 1);
    if (width_)
        return RTLIL::Const(chunks_[0].data).as_int(is_signed);
    return 0;
}

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std::string RTLIL::SigSpec::as_string

(

)

const

Definition at line 2840 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.as_string");

    pack();
    std::string str;
    for (size_t i = chunks_.size(); i > 0; i--) {
        const RTLIL::SigChunk &chunk = chunks_[i-1];
        if (chunk.wire != NULL)
            for (int j = 0; j < chunk.width; j++)
                str += "?";
        else
            str += RTLIL::Const(chunk.data).as_string();
    }
    return str;
}

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RTLIL::Wire * RTLIL::SigSpec::as_wire

(

)

const

Definition at line 2868 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.as_wire");

    pack();
    log_assert(is_wire());
    return chunks_[0].wire;
}

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RTLIL::SigSpecIterator RTLIL::SigSpec::begin ( )

inline

Definition at line 1024 of file rtlil.h.

{ RTLIL::SigSpecIterator it; it.sig_p = this; it.index = 0; return it; }

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RTLIL::SigSpecConstIterator RTLIL::SigSpec::begin ( ) const

inline

Definition at line 1027 of file rtlil.h.

{ RTLIL::SigSpecConstIterator it; it.sig_p = this; it.index = 0; return it; }

const std::vector<RTLIL::SigBit>& RTLIL::SigSpec::bits ( ) const

inline

Definition at line 1017 of file rtlil.h.

{ inline_unpack(); return bits_; }

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void RTLIL::SigSpec::check

(

)

const

Definition at line 2642 of file rtlil.cc.

{
    if (width_ > 64)
    {
        cover("kernel.rtlil.sigspec.check.skip");
    }
    else if (packed())
    {
        cover("kernel.rtlil.sigspec.check.packed");

        int w = 0;
        for (size_t i = 0; i < chunks_.size(); i++) {
            const RTLIL::SigChunk chunk = chunks_[i];
            if (chunk.wire == NULL) {
                if (i > 0)
                    log_assert(chunks_[i-1].wire != NULL);
                log_assert(chunk.offset == 0);
                log_assert(chunk.data.size() == (size_t)chunk.width);
            } else {
                if (i > 0 && chunks_[i-1].wire == chunk.wire)
                    log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
                log_assert(chunk.offset >= 0);
                log_assert(chunk.width >= 0);
                log_assert(chunk.offset + chunk.width <= chunk.wire->width);
                log_assert(chunk.data.size() == 0);
            }
            w += chunk.width;
        }
        log_assert(w == width_);
        log_assert(bits_.empty());
    }
    else
    {
        cover("kernel.rtlil.sigspec.check.unpacked");

        log_assert(width_ == GetSize(bits_));
        log_assert(chunks_.empty());
    }
}

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const std::vector<RTLIL::SigChunk>& RTLIL::SigSpec::chunks ( ) const

inline

Definition at line 1016 of file rtlil.h.

{ pack(); return chunks_; }

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RTLIL::SigSpecIterator RTLIL::SigSpec::end ( )

inline

Definition at line 1025 of file rtlil.h.

{ RTLIL::SigSpecIterator it; it.sig_p = this; it.index = width_; return it; }

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RTLIL::SigSpecConstIterator RTLIL::SigSpec::end ( ) const

inline

Definition at line 1028 of file rtlil.h.

{ RTLIL::SigSpecConstIterator it; it.sig_p = this; it.index = width_; return it; }

void RTLIL::SigSpec::extend	(	int	width,
		bool	is_signed = false
	)

Definition at line 2593 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.extend");

    pack();

    if (width_ > width)
        remove(width, width_ - width);
    
    if (width_ < width) {
        RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
        if (!is_signed && padding != RTLIL::SigSpec(RTLIL::State::Sx) && padding != RTLIL::SigSpec(RTLIL::State::Sz) &&
                padding != RTLIL::SigSpec(RTLIL::State::Sa) && padding != RTLIL::SigSpec(RTLIL::State::Sm))
            padding = RTLIL::SigSpec(RTLIL::State::S0);
        while (width_ < width)
            append(padding);
    }
}

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void RTLIL::SigSpec::extend_u0	(	int	width,
		bool	is_signed = false
	)

Definition at line 2612 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.extend_u0");

    pack();

    if (width_ > width)
        remove(width, width_ - width);
    
    if (width_ < width) {
        RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
        if (!is_signed)
            padding = RTLIL::SigSpec(RTLIL::State::S0);
        while (width_ < width)
            append(padding);
    }

}

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RTLIL::SigSpec RTLIL::SigSpec::extract	(	const RTLIL::SigSpec &	pattern,
		const RTLIL::SigSpec *	other = NULL
	)		const

Definition at line 2414 of file rtlil.cc.

{
    std::set<RTLIL::SigBit> pattern_bits = pattern.to_sigbit_set();
    return extract(pattern_bits, other);
}

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RTLIL::SigSpec RTLIL::SigSpec::extract	(	const std::set< RTLIL::SigBit > &	pattern,
		const RTLIL::SigSpec *	other = NULL
	)		const

Definition at line 2420 of file rtlil.cc.

{
    if (other)
        cover("kernel.rtlil.sigspec.extract_other");
    else
        cover("kernel.rtlil.sigspec.extract");

    log_assert(other == NULL || width_ == other->width_);

    std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
    RTLIL::SigSpec ret;

    if (other) {
        std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
        for (int i = 0; i < width_; i++)
            if (bits_match[i].wire && pattern.count(bits_match[i]))
                ret.append_bit(bits_other[i]);
    } else {
        for (int i = 0; i < width_; i++)
            if (bits_match[i].wire && pattern.count(bits_match[i]))
                ret.append_bit(bits_match[i]);
    }

    ret.check();
    return ret;
}

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RTLIL::SigSpec RTLIL::SigSpec::extract	(	int	offset,
		int	length = 1
	)		const

Definition at line 2516 of file rtlil.cc.

{
    unpack();
    cover("kernel.rtlil.sigspec.extract_pos");
    return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
}

bool RTLIL::SigSpec::has_marked_bits

(

)

const

Definition at line 2804 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.has_marked_bits");

    pack();
    for (auto it = chunks_.begin(); it != chunks_.end(); it++)
        if (it->width > 0 && it->wire == NULL) {
            for (size_t i = 0; i < it->data.size(); i++)
                if (it->data[i] == RTLIL::State::Sm)
                    return true;
        }
    return false;
}

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void RTLIL::SigSpec::hash ( ) const

private

Definition at line 2259 of file rtlil.cc.

{
    RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;

    if (that->hash_ != 0)
        return;

    cover("kernel.rtlil.sigspec.hash");
    that->pack();

    that->hash_ = 5381;
    for (auto &c : that->chunks_)
        if (c.wire == NULL) {
            for (auto &v : c.data)
                DJB2(that->hash_, v);
        } else {
            DJB2(that->hash_, c.wire->name.index_);
            DJB2(that->hash_, c.offset);
            DJB2(that->hash_, c.width);
        }

    if (that->hash_ == 0)
        that->hash_ = 1;
}

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void RTLIL::SigSpec::inline_unpack ( ) const

inlineprivate

Definition at line 977 of file rtlil.h.

                                      {
        if (!chunks_.empty())
            unpack();
    }

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bool RTLIL::SigSpec::is_chunk

(

)

const

Definition at line 2755 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.is_chunk");

    pack();
    return GetSize(chunks_) == 1;
}

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bool RTLIL::SigSpec::is_fully_const

(

)

const

Definition at line 2763 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.is_fully_const");

    pack();
    for (auto it = chunks_.begin(); it != chunks_.end(); it++)
        if (it->width > 0 && it->wire != NULL)
            return false;
    return true;
}

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bool RTLIL::SigSpec::is_fully_def

(

)

const

Definition at line 2774 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.is_fully_def");

    pack();
    for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
        if (it->width > 0 && it->wire != NULL)
            return false;
        for (size_t i = 0; i < it->data.size(); i++)
            if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
                return false;
    }
    return true;
}

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bool RTLIL::SigSpec::is_fully_undef

(

)

const

Definition at line 2789 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.is_fully_undef");

    pack();
    for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
        if (it->width > 0 && it->wire != NULL)
            return false;
        for (size_t i = 0; i < it->data.size(); i++)
            if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
                return false;
    }
    return true;
}

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bool RTLIL::SigSpec::is_wire

(

)

const

Definition at line 2747 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.is_wire");

    pack();
    return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
}

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bool RTLIL::SigSpec::match

(

std::string

pattern

)

const

Definition at line 2886 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.match");

    pack();
    std::string str = as_string();
    log_assert(pattern.size() == str.size());

    for (size_t i = 0; i < pattern.size(); i++) {
        if (pattern[i] == ' ')
            continue;
        if (pattern[i] == '*') {
            if (str[i] != 'z' && str[i] != 'x')
                return false;
            continue;
        }
        if (pattern[i] != str[i])
            return false;
    }

    return true;
}

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RTLIL::SigSpec::operator std::vector< RTLIL::SigBit > ( ) const

inline

Definition at line 1095 of file rtlil.h.

{ return bits(); }

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RTLIL::SigSpec::operator std::vector< RTLIL::SigChunk > ( ) const

inline

Definition at line 1094 of file rtlil.h.

{ return chunks(); }

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bool RTLIL::SigSpec::operator!= ( const RTLIL::SigSpec &  other ) const

inline

Definition at line 1066 of file rtlil.h.

{ return !(*this == other); }

bool RTLIL::SigSpec::operator<

(

const RTLIL::SigSpec &

other

)

const

Definition at line 2683 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.comp_lt");

    if (this == &other)
        return false;

    if (width_ != other.width_)
        return width_ < other.width_;

    pack();
    other.pack();

    if (chunks_.size() != other.chunks_.size())
        return chunks_.size() < other.chunks_.size();

    hash();
    other.hash();

    if (hash_ != other.hash_)
        return hash_ < other.hash_;

    for (size_t i = 0; i < chunks_.size(); i++)
        if (chunks_[i] != other.chunks_[i]) {
            cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
            return chunks_[i] < other.chunks_[i];
        }

    cover("kernel.rtlil.sigspec.comp_lt.equal");
    return false;
}

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const RTLIL::SigSpec & RTLIL::SigSpec::operator=

(

const RTLIL::SigSpec &

other

)

Definition at line 2038 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.assign");

    width_ = other.width_;
    hash_ = other.hash_;
    chunks_ = other.chunks_;
    bits_.clear();

    if (!other.bits_.empty())
    {
        RTLIL::SigChunk *last = NULL;
        int last_end_offset = 0;

        for (auto &bit : other.bits_) {
            if (last && bit.wire == last->wire) {
                if (bit.wire == NULL) {
                    last->data.push_back(bit.data);
                    last->width++;
                    continue;
                } else if (last_end_offset == bit.offset) {
                    last_end_offset++;
                    last->width++;
                    continue;
                }
            }
            chunks_.push_back(bit);
            last = &chunks_.back();
            last_end_offset = bit.offset + 1;
        }

        check();
    }

    return *this;
}

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const RTLIL::SigSpec& RTLIL::SigSpec::operator= ( RTLIL::SigSpec &&  other )

inline

Definition at line 1008 of file rtlil.h.

                                                        {
        width_ = other.width_;
        hash_ = other.hash_;
        chunks_ = std::move(other.chunks_);
        bits_ = std::move(other.bits_);
        return *this;
    }

bool RTLIL::SigSpec::operator==

(

const RTLIL::SigSpec &

other

)

const

Definition at line 2715 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.comp_eq");

    if (this == &other)
        return true;

    if (width_ != other.width_)
        return false;

    pack();
    other.pack();

    if (chunks_.size() != chunks_.size())
        return false;

    hash();
    other.hash();

    if (hash_ != other.hash_)
        return false;

    for (size_t i = 0; i < chunks_.size(); i++)
        if (chunks_[i] != other.chunks_[i]) {
            cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
            return false;
        }

    cover("kernel.rtlil.sigspec.comp_eq.equal");
    return true;
}

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RTLIL::SigBit& RTLIL::SigSpec::operator[] ( int  index )

inline

Definition at line 1021 of file rtlil.h.

{ inline_unpack(); return bits_.at(index); }

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const RTLIL::SigBit& RTLIL::SigSpec::operator[] ( int  index ) const

inline

Definition at line 1022 of file rtlil.h.

{ inline_unpack(); return bits_.at(index); }

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void RTLIL::SigSpec::pack ( ) const

private

Definition at line 2202 of file rtlil.cc.

{
    RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;

    if (that->bits_.empty())
        return;

    cover("kernel.rtlil.sigspec.convert.pack");
    log_assert(that->chunks_.empty());

    std::vector<RTLIL::SigBit> old_bits;
    old_bits.swap(that->bits_);

    RTLIL::SigChunk *last = NULL;
    int last_end_offset = 0;

    for (auto &bit : old_bits) {
        if (last && bit.wire == last->wire) {
            if (bit.wire == NULL) {
                last->data.push_back(bit.data);
                last->width++;
                continue;
            } else if (last_end_offset == bit.offset) {
                last_end_offset++;
                last->width++;
                continue;
            }
        }
        that->chunks_.push_back(bit);
        last = &that->chunks_.back();
        last_end_offset = bit.offset + 1;
    }

    check();
}

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bool RTLIL::SigSpec::packed ( ) const

inlineprivate

Definition at line 973 of file rtlil.h.

                               {
        return bits_.empty();
    }

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bool RTLIL::SigSpec::parse ( RTLIL::SigSpec &  sig, RTLIL::Module *  module, std::string  str  )

static

Definition at line 2972 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.parse");

    std::vector<std::string> tokens;
    sigspec_parse_split(tokens, str, ',');

    sig = RTLIL::SigSpec();
    for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
    {
        std::string netname = tokens[tokidx];
        std::string indices;

        if (netname.size() == 0)
            continue;

        if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
            cover("kernel.rtlil.sigspec.parse.const");
            AST::get_line_num = sigspec_parse_get_dummy_line_num;
            AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
            if (ast == NULL)
                return false;
            sig.append(RTLIL::Const(ast->bits));
            delete ast;
            continue;
        }

        if (module == NULL)
            return false;

        cover("kernel.rtlil.sigspec.parse.net");

        if (netname[0] != '$' && netname[0] != '\\')
            netname = "\\" + netname;

        if (module->wires_.count(netname) == 0) {
            size_t indices_pos = netname.size()-1;
            if (indices_pos > 2 && netname[indices_pos] == ']')
            {
                indices_pos--;
                while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
                if (indices_pos > 0 && netname[indices_pos] == ':') {
                    indices_pos--;
                    while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
                }
                if (indices_pos > 0 && netname[indices_pos] == '[') {
                    indices = netname.substr(indices_pos);
                    netname = netname.substr(0, indices_pos);
                }
            }
        }

        if (module->wires_.count(netname) == 0)
            return false;

        RTLIL::Wire *wire = module->wires_.at(netname);
        if (!indices.empty()) {
            std::vector<std::string> index_tokens;
            sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
            if (index_tokens.size() == 1) {
                cover("kernel.rtlil.sigspec.parse.bit_sel");
                int a = atoi(index_tokens.at(0).c_str());
                if (a < 0 || a >= wire->width)
                    return false;
                sig.append(RTLIL::SigSpec(wire, a));
            } else {
                cover("kernel.rtlil.sigspec.parse.part_sel");
                int a = atoi(index_tokens.at(0).c_str());
                int b = atoi(index_tokens.at(1).c_str());
                if (a > b) {
                    int tmp = a;
                    a = b, b = tmp;
                }
                if (a < 0 || a >= wire->width)
                    return false;
                if (b < 0 || b >= wire->width)
                    return false;
                sig.append(RTLIL::SigSpec(wire, a, b-a+1));
            }
        } else
            sig.append(wire);
    }

    return true;
}

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bool RTLIL::SigSpec::parse_rhs ( const RTLIL::SigSpec &  lhs, RTLIL::SigSpec &  sig, RTLIL::Module *  module, std::string  str  )

static

Definition at line 3078 of file rtlil.cc.

{
    if (str == "0") {
        cover("kernel.rtlil.sigspec.parse.rhs_zeros");
        sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
        return true;
    }

    if (str == "~0") {
        cover("kernel.rtlil.sigspec.parse.rhs_ones");
        sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
        return true;
    }

    if (lhs.chunks_.size() == 1) {
        char *p = (char*)str.c_str(), *endptr;
        long int val = strtol(p, &endptr, 10);
        if (endptr && endptr != p && *endptr == 0) {
            sig = RTLIL::SigSpec(val, lhs.width_);
            cover("kernel.rtlil.sigspec.parse.rhs_dec");
            return true;
        }
    }

    return parse(sig, module, str);
}

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bool RTLIL::SigSpec::parse_sel ( RTLIL::SigSpec &  sig, RTLIL::Design *  design, RTLIL::Module *  module, std::string  str  )

static

Definition at line 3058 of file rtlil.cc.

{
    if (str.empty() || str[0] != '@')
        return parse(sig, module, str);

    cover("kernel.rtlil.sigspec.parse.sel");

    str = RTLIL::escape_id(str.substr(1));
    if (design->selection_vars.count(str) == 0)
        return false;

    sig = RTLIL::SigSpec();
    RTLIL::Selection &sel = design->selection_vars.at(str);
    for (auto &it : module->wires_)
        if (sel.selected_member(module->name, it.first))
            sig.append(it.second);

    return true;
}

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void RTLIL::SigSpec::remove

(

const RTLIL::SigSpec &

pattern

)

Definition at line 2342 of file rtlil.cc.

{
    remove2(pattern, NULL);
}

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void RTLIL::SigSpec::remove	(	const RTLIL::SigSpec &	pattern,
		RTLIL::SigSpec *	other
	)		const

Definition at line 2347 of file rtlil.cc.

{
    RTLIL::SigSpec tmp = *this;
    tmp.remove2(pattern, other);
}

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void RTLIL::SigSpec::remove

(

const std::set< RTLIL::SigBit > &

pattern

)

Definition at line 2359 of file rtlil.cc.

{
    remove2(pattern, NULL);
}

void RTLIL::SigSpec::remove	(	const std::set< RTLIL::SigBit > &	pattern,
		RTLIL::SigSpec *	other
	)		const

Definition at line 2364 of file rtlil.cc.

{
    RTLIL::SigSpec tmp = *this;
    tmp.remove2(pattern, other);
}

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void RTLIL::SigSpec::remove	(	int	offset,
		int	length = 1
	)

Definition at line 2500 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.remove_pos");

    unpack();

    log_assert(offset >= 0);
    log_assert(length >= 0);
    log_assert(offset + length <= width_);

    bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
    width_ = bits_.size();

    check();
}

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void RTLIL::SigSpec::remove2	(	const RTLIL::SigSpec &	pattern,
		RTLIL::SigSpec *	other
	)

Definition at line 2353 of file rtlil.cc.

{
    std::set<RTLIL::SigBit> pattern_bits = pattern.to_sigbit_set();
    remove2(pattern_bits, other);
}

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void RTLIL::SigSpec::remove2	(	const std::set< RTLIL::SigBit > &	pattern,
		RTLIL::SigSpec *	other
	)

Definition at line 2370 of file rtlil.cc.

{
    if (other)
        cover("kernel.rtlil.sigspec.remove_other");
    else
        cover("kernel.rtlil.sigspec.remove");

    unpack();

    if (other != NULL) {
        log_assert(width_ == other->width_);
        other->unpack();
    }

    std::vector<RTLIL::SigBit> new_bits, new_other_bits;

    new_bits.resize(GetSize(bits_));
    if (other != NULL)
        new_other_bits.resize(GetSize(bits_));

    int k = 0;
    for (int i = 0; i < GetSize(bits_); i++) {
        if (bits_[i].wire != NULL && pattern.count(bits_[i]))
            continue;
        if (other != NULL)
            new_other_bits[k] = other->bits_[i];
        new_bits[k++] = bits_[i];
    }

    new_bits.resize(k);
    if (other != NULL)
        new_other_bits.resize(k);

    bits_.swap(new_bits);
    width_ = GetSize(bits_);

    if (other != NULL) {
        other->bits_.swap(new_other_bits);
        other->width_ = GetSize(other->bits_);
    }

    check();
}

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void RTLIL::SigSpec::remove_const

(

)

Definition at line 2464 of file rtlil.cc.

{
    if (packed())
    {
        cover("kernel.rtlil.sigspec.remove_const.packed");

        std::vector<RTLIL::SigChunk> new_chunks;
        new_chunks.reserve(GetSize(chunks_));

        width_ = 0;
        for (auto &chunk : chunks_)
            if (chunk.wire != NULL) {
                new_chunks.push_back(chunk);
                width_ += chunk.width;
            }

        chunks_.swap(new_chunks);
    }
    else
    {
        cover("kernel.rtlil.sigspec.remove_const.unpacked");

        std::vector<RTLIL::SigBit> new_bits;
        new_bits.reserve(width_);

        for (auto &bit : bits_)
            if (bit.wire != NULL)
                new_bits.push_back(bit);

        bits_.swap(new_bits);
        width_ = bits_.size();
    }

    check();
}

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RTLIL::SigSpec RTLIL::SigSpec::repeat

(

int

num

)

const

Definition at line 2631 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.repeat");

    RTLIL::SigSpec sig;
    for (int i = 0; i < num; i++)
        sig.append(*this);
    return sig;
}

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void RTLIL::SigSpec::replace	(	const RTLIL::SigSpec &	pattern,
		const RTLIL::SigSpec &	with
	)

Definition at line 2297 of file rtlil.cc.

{
    replace(pattern, with, this);
}

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void RTLIL::SigSpec::replace	(	const RTLIL::SigSpec &	pattern,
		const RTLIL::SigSpec &	with,
		RTLIL::SigSpec *	other
	)		const

Definition at line 2302 of file rtlil.cc.

{
    log_assert(pattern.width_ == with.width_);

    pattern.unpack();
    with.unpack();

    std::map<RTLIL::SigBit, RTLIL::SigBit> rules;

    for (int i = 0; i < GetSize(pattern.bits_); i++)
        if (pattern.bits_[i].wire != NULL)
            rules[pattern.bits_[i]] = with.bits_[i];

    replace(rules, other);
}

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void RTLIL::SigSpec::replace

(

const std::map< RTLIL::SigBit, RTLIL::SigBit > &

rules

)

Definition at line 2318 of file rtlil.cc.

{
    replace(rules, this);
}

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void RTLIL::SigSpec::replace	(	const std::map< RTLIL::SigBit, RTLIL::SigBit > &	rules,
		RTLIL::SigSpec *	other
	)		const

Definition at line 2323 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.replace");

    log_assert(other != NULL);
    log_assert(width_ == other->width_);

    unpack();
    other->unpack();

    for (int i = 0; i < GetSize(bits_); i++) {
        auto it = rules.find(bits_[i]);
        if (it != rules.end())
            other->bits_[i] = it->second;
    }

    other->check();
}

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void RTLIL::SigSpec::replace	(	int	offset,
		const RTLIL::SigSpec &	with
	)

Definition at line 2447 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.replace_pos");

    unpack();
    with.unpack();

    log_assert(offset >= 0);
    log_assert(with.width_ >= 0);
    log_assert(offset+with.width_ <= width_);

    for (int i = 0; i < with.width_; i++)
        bits_.at(offset + i) = with.bits_.at(i);

    check();
}

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int RTLIL::SigSpec::size ( ) const

inline

Definition at line 1019 of file rtlil.h.

{ return width_; }

void RTLIL::SigSpec::sort

(

)

Definition at line 2284 of file rtlil.cc.

{
    unpack();
    cover("kernel.rtlil.sigspec.sort");
    std::sort(bits_.begin(), bits_.end());
}

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void RTLIL::SigSpec::sort_and_unify

(

)

Definition at line 2291 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.sort_and_unify");
    *this = this->to_sigbit_set();
}

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std::map< RTLIL::SigBit, RTLIL::SigBit > RTLIL::SigSpec::to_sigbit_map

(

const RTLIL::SigSpec &

other

)

const

Definition at line 2929 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.to_sigbit_map");

    unpack();
    other.unpack();

    log_assert(width_ == other.width_);

    std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
    for (int i = 0; i < width_; i++)
        new_map[bits_[i]] = other.bits_[i];

    return new_map;
}

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std::set< RTLIL::SigBit > RTLIL::SigSpec::to_sigbit_set

(

)

const

Definition at line 2909 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.to_sigbit_set");

    pack();
    std::set<RTLIL::SigBit> sigbits;
    for (auto &c : chunks_)
        for (int i = 0; i < c.width; i++)
            sigbits.insert(RTLIL::SigBit(c, i));
    return sigbits;
}

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std::vector< RTLIL::SigBit > RTLIL::SigSpec::to_sigbit_vector

(

)

const

Definition at line 2921 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.to_sigbit_vector");

    unpack();
    return bits_;
}

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RTLIL::SigBit RTLIL::SigSpec::to_single_sigbit

(

)

const

Definition at line 2945 of file rtlil.cc.

{
    cover("kernel.rtlil.sigspec.to_single_sigbit");

    pack();
    log_assert(width_ == 1);
    for (auto &c : chunks_)
        if (c.width)
            return RTLIL::SigBit(c);
    log_abort();
}

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void RTLIL::SigSpec::unpack ( ) const

private

Definition at line 2238 of file rtlil.cc.

{
    RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;

    if (that->chunks_.empty())
        return;

    cover("kernel.rtlil.sigspec.convert.unpack");
    log_assert(that->bits_.empty());

    that->bits_.reserve(that->width_);
    for (auto &c : that->chunks_)
        for (int i = 0; i < c.width; i++)
            that->bits_.push_back(RTLIL::SigBit(c, i));

    that->chunks_.clear();
    that->hash_ = 0;
}

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Field Documentation

std::vector<RTLIL::SigBit> RTLIL::SigSpec::bits_

private

Definition at line 967 of file rtlil.h.

std::vector<RTLIL::SigChunk> RTLIL::SigSpec::chunks_

private

Definition at line 966 of file rtlil.h.

unsigned long RTLIL::SigSpec::hash_

private

Definition at line 965 of file rtlil.h.

int RTLIL::SigSpec::width_

private

Definition at line 964 of file rtlil.h.

---

The documentation for this struct was generated from the following files:

• rtlil.h
• rtlil.cc