VERILOG_FRONTEND Namespace Reference

Functions
AST::AstNode *	const2ast (std::string code, char case_type=0, bool warn_z=false)

Variables
struct AST::AstNode *	current_ast
bool	default_nettype_wire
bool	sv_mode
std::istream *	lexin
std::vector< std::string >	fn_stack
std::vector< int >	ln_stack
int	port_counter
std::map< std::string, int >	port_stubs
std::map< std::string, AstNode * >	attr_list
std::map< std::string, AstNode * >	default_attr_list
std::map< std::string, AstNode * > *	albuf
std::vector< AstNode * >	ast_stack
struct AstNode *	astbuf1
struct AstNode *	astbuf2
struct AstNode *	astbuf3
struct AstNode *	current_function_or_task
struct AstNode *	current_ast_mod
int	current_function_or_task_port_id
std::vector< char >	case_type_stack
bool	do_not_require_port_stubs

Function Documentation

AstNode * VERILOG_FRONTEND::const2ast	(	std::string	code,
		char	case_type = 0,
		bool	warn_z = false
	)

Definition at line 135 of file const2ast.cc.

{
    if (warn_z) {
        AstNode *ret = const2ast(code, case_type);
        if (std::find(ret->bits.begin(), ret->bits.end(), RTLIL::State::Sz) != ret->bits.end())
            log_warning("Yosys does not support tri-state logic at the moment. (%s:%d)\n",
                current_filename.c_str(), frontend_verilog_yyget_lineno());
        return ret;
    }

    const char *str = code.c_str();

    // Strings
    if (*str == '"') {
        int len = strlen(str) - 2;
        std::vector<RTLIL::State> data;
        data.reserve(len * 8);
        for (int i = 0; i < len; i++) {
            unsigned char ch = str[len - i];
            for (int j = 0; j < 8; j++) {
                data.push_back((ch & 1) ? RTLIL::S1 : RTLIL::S0);
                ch = ch >> 1;
            }
        }
        AstNode *ast = AstNode::mkconst_bits(data, false);
        ast->str = code;
        return ast;
    }

    for (size_t i = 0; i < code.size(); i++)
        if (code[i] == '_' || code[i] == ' ' || code[i] == '\t' || code[i] == '\r' || code[i] == '\n')
            code.erase(code.begin()+(i--));
    str = code.c_str();

    char *endptr;
    long len_in_bits = strtol(str, &endptr, 10);

    // Simple base-10 integer
    if (*endptr == 0) {
        std::vector<RTLIL::State> data;
        my_strtobin(data, str, -1, 10, case_type);
        if (data.back() == RTLIL::S1)
            data.push_back(RTLIL::S0);
        return AstNode::mkconst_bits(data, true);
    }

    // unsized constant
    if (str == endptr)
        len_in_bits = -1;

    // The "<bits>'s?[bodhBODH]<digits>" syntax
    if (*endptr == '\'')
    {
        std::vector<RTLIL::State> data;
        bool is_signed = false;
        if (*(endptr+1) == 's') {
            is_signed = true;
            endptr++;
        }
        switch (*(endptr+1))
        {
        case 'b':
        case 'B':
            my_strtobin(data, endptr+2, len_in_bits, 2, case_type);
            break;
        case 'o':
        case 'O':
            my_strtobin(data, endptr+2, len_in_bits, 8, case_type);
            break;
        case 'd':
        case 'D':
            my_strtobin(data, endptr+2, len_in_bits, 10, case_type);
            break;
        case 'h':
        case 'H':
            my_strtobin(data, endptr+2, len_in_bits, 16, case_type);
            break;
        default:
            return NULL;
        }
        if (len_in_bits < 0) {
            if (is_signed && data.back() == RTLIL::S1)
                data.push_back(RTLIL::S0);
            while (data.size() < 32)
                data.push_back(RTLIL::S0);
        }
        return AstNode::mkconst_bits(data, is_signed);
    }

    return NULL;
}

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Variable Documentation

std::map<std::string, AstNode*>* VERILOG_FRONTEND::albuf

Definition at line 89 of file verilog_parser.tab.cc.

std::vector<AstNode*> VERILOG_FRONTEND::ast_stack

Definition at line 90 of file verilog_parser.tab.cc.

struct AstNode* VERILOG_FRONTEND::astbuf1

Definition at line 91 of file verilog_parser.tab.cc.

struct AstNode * VERILOG_FRONTEND::astbuf2

Definition at line 91 of file verilog_parser.tab.cc.

struct AstNode * VERILOG_FRONTEND::astbuf3

Definition at line 91 of file verilog_parser.tab.cc.

std::map<std::string, AstNode*> VERILOG_FRONTEND::attr_list

Definition at line 88 of file verilog_parser.tab.cc.

std::vector<char> VERILOG_FRONTEND::case_type_stack

Definition at line 95 of file verilog_parser.tab.cc.

struct AstNode * VERILOG_FRONTEND::current_ast

Definition at line 93 of file verilog_parser.tab.cc.

struct AstNode * VERILOG_FRONTEND::current_ast_mod

Definition at line 93 of file verilog_parser.tab.cc.

struct AstNode* VERILOG_FRONTEND::current_function_or_task

Definition at line 92 of file verilog_parser.tab.cc.

int VERILOG_FRONTEND::current_function_or_task_port_id

Definition at line 94 of file verilog_parser.tab.cc.

std::map<std::string, AstNode*> VERILOG_FRONTEND::default_attr_list

Definition at line 88 of file verilog_parser.tab.cc.

bool VERILOG_FRONTEND::default_nettype_wire

Definition at line 97 of file verilog_parser.tab.cc.

bool VERILOG_FRONTEND::do_not_require_port_stubs

Definition at line 96 of file verilog_parser.tab.cc.

std::vector<std::string> VERILOG_FRONTEND::fn_stack

Definition at line 998 of file verilog_lexer.cc.

std::istream * VERILOG_FRONTEND::lexin

Definition at line 99 of file verilog_parser.tab.cc.

std::vector<int> VERILOG_FRONTEND::ln_stack

Definition at line 999 of file verilog_lexer.cc.

int VERILOG_FRONTEND::port_counter

Definition at line 86 of file verilog_parser.tab.cc.

std::map<std::string, int> VERILOG_FRONTEND::port_stubs

Definition at line 87 of file verilog_parser.tab.cc.

bool VERILOG_FRONTEND::sv_mode

Definition at line 98 of file verilog_parser.tab.cc.