188     std::vector<RTLIL::IdString> del_list, add_list;
 
  192         if (design->
modules_.count(mod_name) == 0)
 
  193             del_list.push_back(mod_name);
 
  196     for (
auto mod_name : del_list)
 
  197         selected_modules.erase(mod_name);
 
  201         if (design->
modules_.count(it.first) == 0)
 
  202             del_list.push_back(it.first);
 
  203     for (
auto mod_name : del_list)
 
  204         selected_members.erase(mod_name);
 
  206     for (
auto &it : selected_members) {
 
  208         for (
auto memb_name : it.second)
 
  209             if (design->
modules_[it.first]->count_id(memb_name) == 0)
 
  210                 del_list.push_back(memb_name);
 
  211         for (
auto memb_name : del_list)
 
  212             it.second.erase(memb_name);
 
  217     for (
auto &it : selected_members)
 
  218         if (it.second.size() == 0)
 
  219             del_list.push_back(it.first);
 
  220         else if (it.second.size() == design->
modules_[it.first]->wires_.size() + design->
modules_[it.first]->memories.size() +
 
  221                 design->
modules_[it.first]->cells_.size() + design->
modules_[it.first]->processes.size())
 
  222             add_list.push_back(it.first);
 
  223     for (
auto mod_name : del_list)
 
  224         selected_members.erase(mod_name);
 
  225     for (
auto mod_name : add_list) {
 
  226         selected_members.erase(mod_name);
 
  227         selected_modules.insert(mod_name);
 
  230     if (selected_modules.size() == design->
modules_.size()) {
 
  232         selected_modules.clear();
 
  233         selected_members.clear();
 
std::set< RTLIL::IdString > selected_modules
 
std::map< RTLIL::IdString, std::set< RTLIL::IdString > > selected_members
 
std::map< RTLIL::IdString, RTLIL::Module * > modules_