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abc.cc File Reference
#include "kernel/register.h"
#include "kernel/sigtools.h"
#include "kernel/cost.h"
#include "kernel/log.h"
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <cerrno>
#include <sstream>
#include <climits>
#include <unistd.h>
#include <dirent.h>
#include "blifparse.h"
+ Include dependency graph for abc.cc:

Go to the source code of this file.

Data Structures

struct  gate_t
 
struct  abc_output_filter
 
struct  AbcPass
 

Macros

#define ABC_COMMAND_LIB   "strash; scorr -v; ifraig -v; retime -v {D}; strash; dch -vf; map -v {D}"
 
#define ABC_COMMAND_CTR   "strash; scorr -v; ifraig -v; retime -v {D}; strash; dch -vf; map -v {D}; buffer -v; upsize -v {D}; dnsize -v {D}; stime -p"
 
#define ABC_COMMAND_LUT   "strash; scorr -v; ifraig -v; retime -v; strash; dch -vf; if -v"
 
#define ABC_COMMAND_DFL   "strash; scorr -v; ifraig -v; retime -v; strash; dch -vf; map -v"
 
#define ABC_FAST_COMMAND_LIB   "retime -v {D}; map -v {D}"
 
#define ABC_FAST_COMMAND_CTR   "retime -v {D}; map -v {D}; buffer -v; upsize -v {D}; dnsize -v {D}; stime -p"
 
#define ABC_FAST_COMMAND_LUT   "retime -v; if -v"
 
#define ABC_FAST_COMMAND_DFL   "retime -v; map -v"
 
#define G(_name)   gate_type_t::G_ ## _name
 

Enumerations

enum  gate_type_t {
  gate_type_t::G_NONE, gate_type_t::G_FF, gate_type_t::G_BUF, gate_type_t::G_NOT,
  gate_type_t::G_AND, gate_type_t::G_NAND, gate_type_t::G_OR, gate_type_t::G_NOR,
  gate_type_t::G_XOR, gate_type_t::G_XNOR, gate_type_t::G_MUX, gate_type_t::G_AOI3,
  gate_type_t::G_OAI3, gate_type_t::G_AOI4, gate_type_t::G_OAI4
}
 

Functions

int map_signal (RTLIL::SigBit bit, gate_type_t gate_type=G(NONE), int in1=-1, int in2=-1, int in3=-1, int in4=-1)
 
void mark_port (RTLIL::SigSpec sig)
 
void extract_cell (RTLIL::Cell *cell, bool keepff)
 
std::string remap_name (RTLIL::IdString abc_name)
 
void dump_loop_graph (FILE *f, int &nr, std::map< int, std::set< int >> &edges, std::set< int > &workpool, std::vector< int > &in_counts)
 
void handle_loops ()
 
std::string add_echos_to_abc_cmd (std::string str)
 
std::string fold_abc_cmd (std::string str)
 
void abc_module (RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file, std::string liberty_file, std::string constr_file, bool cleanup, int lut_mode, bool dff_mode, std::string clk_str, bool keepff, std::string delay_target, bool fast_mode)
 

Variables

int map_autoidx
 
SigMap assign_map
 
RTLIL::Module * module
 
std::vector< gate_t > signal_list
 
std::map< RTLIL::SigBit, int > signal_map
 
bool clk_polarity
 
RTLIL::SigSpec clk_sig
 
AbcPass AbcPass
 

Macro Definition Documentation

#define ABC_COMMAND_CTR   "strash; scorr -v; ifraig -v; retime -v {D}; strash; dch -vf; map -v {D}; buffer -v; upsize -v {D}; dnsize -v {D}; stime -p"

Definition at line 33 of file abc.cc.

#define ABC_COMMAND_DFL   "strash; scorr -v; ifraig -v; retime -v; strash; dch -vf; map -v"

Definition at line 35 of file abc.cc.

#define ABC_COMMAND_LIB   "strash; scorr -v; ifraig -v; retime -v {D}; strash; dch -vf; map -v {D}"

Definition at line 32 of file abc.cc.

#define ABC_COMMAND_LUT   "strash; scorr -v; ifraig -v; retime -v; strash; dch -vf; if -v"

Definition at line 34 of file abc.cc.

#define ABC_FAST_COMMAND_CTR   "retime -v {D}; map -v {D}; buffer -v; upsize -v {D}; dnsize -v {D}; stime -p"

Definition at line 38 of file abc.cc.

#define ABC_FAST_COMMAND_DFL   "retime -v; map -v"

Definition at line 40 of file abc.cc.

#define ABC_FAST_COMMAND_LIB   "retime -v {D}; map -v {D}"

Definition at line 37 of file abc.cc.

#define ABC_FAST_COMMAND_LUT   "retime -v; if -v"

Definition at line 39 of file abc.cc.

#define G (   _name)    gate_type_t::G_ ## _name

Definition at line 81 of file abc.cc.

Enumeration Type Documentation

enum gate_type_t
strong
Enumerator
G_NONE 
G_FF 
G_BUF 
G_NOT 
G_AND 
G_NAND 
G_OR 
G_NOR 
G_XOR 
G_XNOR 
G_MUX 
G_AOI3 
G_OAI3 
G_AOI4 
G_OAI4 

Definition at line 63 of file abc.cc.

63  {
64  G_NONE,
65  G_FF,
66  G_BUF,
67  G_NOT,
68  G_AND,
69  G_NAND,
70  G_OR,
71  G_NOR,
72  G_XOR,
73  G_XNOR,
74  G_MUX,
75  G_AOI3,
76  G_OAI3,
77  G_AOI4,
78  G_OAI4
79 };

Function Documentation

void abc_module ( RTLIL::Design *  design,
RTLIL::Module *  current_module,
std::string  script_file,
std::string  exe_file,
std::string  liberty_file,
std::string  constr_file,
bool  cleanup,
int  lut_mode,
bool  dff_mode,
std::string  clk_str,
bool  keepff,
std::string  delay_target,
bool  fast_mode 
)

Definition at line 545 of file abc.cc.

548 {
549  module = current_module;
550  map_autoidx = autoidx++;
551 
552  signal_map.clear();
553  signal_list.clear();
554  assign_map.set(module);
555 
556  clk_polarity = true;
557  clk_sig = RTLIL::SigSpec();
558 
559  std::string tempdir_name = "/tmp/yosys-abc-XXXXXX";
560  if (!cleanup)
561  tempdir_name[0] = tempdir_name[4] = '_';
562  tempdir_name = make_temp_dir(tempdir_name);
563  log_header("Extracting gate netlist of module `%s' to `%s/input.blif'..\n", module->name.c_str(), tempdir_name.c_str());
564 
565  std::string abc_script = stringf("read_blif %s/input.blif; ", tempdir_name.c_str());
566 
567  if (!liberty_file.empty()) {
568  abc_script += stringf("read_lib -w %s; ", liberty_file.c_str());
569  if (!constr_file.empty())
570  abc_script += stringf("read_constr -v %s; ", constr_file.c_str());
571  } else
572  if (lut_mode)
573  abc_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name.c_str());
574  else
575  abc_script += stringf("read_library %s/stdcells.genlib; ", tempdir_name.c_str());
576 
577  if (!script_file.empty()) {
578  if (script_file[0] == '+') {
579  for (size_t i = 1; i < script_file.size(); i++)
580  if (script_file[i] == '\'')
581  abc_script += "'\\''";
582  else if (script_file[i] == ',')
583  abc_script += " ";
584  else
585  abc_script += script_file[i];
586  } else
587  abc_script += stringf("source %s", script_file.c_str());
588  } else if (lut_mode)
589  abc_script += fast_mode ? ABC_FAST_COMMAND_LUT : ABC_COMMAND_LUT;
590  else if (!liberty_file.empty())
591  abc_script += constr_file.empty() ? (fast_mode ? ABC_FAST_COMMAND_LIB : ABC_COMMAND_LIB) : (fast_mode ? ABC_FAST_COMMAND_CTR : ABC_COMMAND_CTR);
592  else
593  abc_script += fast_mode ? ABC_FAST_COMMAND_DFL : ABC_COMMAND_DFL;
594 
595  for (size_t pos = abc_script.find("{D}"); pos != std::string::npos; pos = abc_script.find("{D}", pos))
596  abc_script = abc_script.substr(0, pos) + delay_target + abc_script.substr(pos+3);
597 
598  abc_script += stringf("; write_blif %s/output.blif", tempdir_name.c_str());
599  abc_script = add_echos_to_abc_cmd(abc_script);
600 
601  for (size_t i = 0; i+1 < abc_script.size(); i++)
602  if (abc_script[i] == ';' && abc_script[i+1] == ' ')
603  abc_script[i+1] = '\n';
604 
605  FILE *f = fopen(stringf("%s/abc.script", tempdir_name.c_str()).c_str(), "wt");
606  fprintf(f, "%s\n", abc_script.c_str());
607  fclose(f);
608 
609  if (clk_str.empty()) {
610  if (clk_str[0] == '!') {
611  clk_polarity = false;
612  clk_str = clk_str.substr(1);
613  }
614  if (module->wires_.count(RTLIL::escape_id(clk_str)) != 0)
615  clk_sig = assign_map(RTLIL::SigSpec(module->wires_.at(RTLIL::escape_id(clk_str)), 0));
616  }
617 
618  if (dff_mode && clk_sig.size() == 0)
619  {
620  int best_dff_counter = 0;
621  std::map<std::pair<bool, RTLIL::SigSpec>, int> dff_counters;
622 
623  for (auto &it : module->cells_)
624  {
625  RTLIL::Cell *cell = it.second;
626  if (cell->type != "$_DFF_N_" && cell->type != "$_DFF_P_")
627  continue;
628 
629  std::pair<bool, RTLIL::SigSpec> key(cell->type == "$_DFF_P_", assign_map(cell->getPort("\\C")));
630  if (++dff_counters[key] > best_dff_counter) {
631  best_dff_counter = dff_counters[key];
632  clk_polarity = key.first;
633  clk_sig = key.second;
634  }
635  }
636  }
637 
638  if (dff_mode || !clk_str.empty()) {
639  if (clk_sig.size() == 0)
640  log("No (matching) clock domain found. Not extracting any FF cells.\n");
641  else
642  log("Found (matching) %s clock domain: %s\n", clk_polarity ? "posedge" : "negedge", log_signal(clk_sig));
643  }
644 
645  if (clk_sig.size() != 0)
646  mark_port(clk_sig);
647 
648  std::vector<RTLIL::Cell*> cells;
649  cells.reserve(module->cells_.size());
650  for (auto &it : module->cells_)
651  if (design->selected(current_module, it.second))
652  cells.push_back(it.second);
653  for (auto c : cells)
654  extract_cell(c, keepff);
655 
656  for (auto &wire_it : module->wires_) {
657  if (wire_it.second->port_id > 0 || wire_it.second->get_bool_attribute("\\keep"))
658  mark_port(RTLIL::SigSpec(wire_it.second));
659  }
660 
661  for (auto &cell_it : module->cells_)
662  for (auto &port_it : cell_it.second->connections())
663  mark_port(port_it.second);
664 
665  handle_loops();
666 
667  std::string buffer = stringf("%s/input.blif", tempdir_name.c_str());
668  f = fopen(buffer.c_str(), "wt");
669  if (f == NULL)
670  log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
671 
672  fprintf(f, ".model netlist\n");
673 
674  int count_input = 0;
675  fprintf(f, ".inputs");
676  for (auto &si : signal_list) {
677  if (!si.is_port || si.type != G(NONE))
678  continue;
679  fprintf(f, " n%d", si.id);
680  count_input++;
681  }
682  if (count_input == 0)
683  fprintf(f, " dummy_input\n");
684  fprintf(f, "\n");
685 
686  int count_output = 0;
687  fprintf(f, ".outputs");
688  for (auto &si : signal_list) {
689  if (!si.is_port || si.type == G(NONE))
690  continue;
691  fprintf(f, " n%d", si.id);
692  count_output++;
693  }
694  fprintf(f, "\n");
695 
696  for (auto &si : signal_list)
697  fprintf(f, "# n%-5d %s\n", si.id, log_signal(si.bit));
698 
699  for (auto &si : signal_list) {
700  if (si.bit.wire == NULL) {
701  fprintf(f, ".names n%d\n", si.id);
702  if (si.bit == RTLIL::State::S1)
703  fprintf(f, "1\n");
704  }
705  }
706 
707  int count_gates = 0;
708  for (auto &si : signal_list) {
709  if (si.type == G(BUF)) {
710  fprintf(f, ".names n%d n%d\n", si.in1, si.id);
711  fprintf(f, "1 1\n");
712  } else if (si.type == G(NOT)) {
713  fprintf(f, ".names n%d n%d\n", si.in1, si.id);
714  fprintf(f, "0 1\n");
715  } else if (si.type == G(AND)) {
716  fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
717  fprintf(f, "11 1\n");
718  } else if (si.type == G(NAND)) {
719  fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
720  fprintf(f, "0- 1\n");
721  fprintf(f, "-0 1\n");
722  } else if (si.type == G(OR)) {
723  fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
724  fprintf(f, "-1 1\n");
725  fprintf(f, "1- 1\n");
726  } else if (si.type == G(NOR)) {
727  fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
728  fprintf(f, "00 1\n");
729  } else if (si.type == G(XOR)) {
730  fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
731  fprintf(f, "01 1\n");
732  fprintf(f, "10 1\n");
733  } else if (si.type == G(XNOR)) {
734  fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
735  fprintf(f, "00 1\n");
736  fprintf(f, "11 1\n");
737  } else if (si.type == G(MUX)) {
738  fprintf(f, ".names n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.id);
739  fprintf(f, "1-0 1\n");
740  fprintf(f, "-11 1\n");
741  } else if (si.type == G(AOI3)) {
742  fprintf(f, ".names n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.id);
743  fprintf(f, "-00 1\n");
744  fprintf(f, "0-0 1\n");
745  } else if (si.type == G(OAI3)) {
746  fprintf(f, ".names n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.id);
747  fprintf(f, "00- 1\n");
748  fprintf(f, "--0 1\n");
749  } else if (si.type == G(AOI4)) {
750  fprintf(f, ".names n%d n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.in4, si.id);
751  fprintf(f, "-0-0 1\n");
752  fprintf(f, "-00- 1\n");
753  fprintf(f, "0--0 1\n");
754  fprintf(f, "0-0- 1\n");
755  } else if (si.type == G(OAI4)) {
756  fprintf(f, ".names n%d n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.in4, si.id);
757  fprintf(f, "00-- 1\n");
758  fprintf(f, "--00 1\n");
759  } else if (si.type == G(FF)) {
760  fprintf(f, ".latch n%d n%d\n", si.in1, si.id);
761  } else if (si.type != G(NONE))
762  log_abort();
763  if (si.type != G(NONE))
764  count_gates++;
765  }
766 
767  fprintf(f, ".end\n");
768  fclose(f);
769 
770  log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
771  count_gates, GetSize(signal_list), count_input, count_output);
772  log_push();
773 
774  if (count_output > 0)
775  {
776  log_header("Executing ABC.\n");
777 
778  buffer = stringf("%s/stdcells.genlib", tempdir_name.c_str());
779  f = fopen(buffer.c_str(), "wt");
780  if (f == NULL)
781  log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
782  fprintf(f, "GATE ZERO 1 Y=CONST0;\n");
783  fprintf(f, "GATE ONE 1 Y=CONST1;\n");
784  fprintf(f, "GATE BUF %d Y=A; PIN * NONINV 1 999 1 0 1 0\n", get_cell_cost("$_BUF_"));
785  fprintf(f, "GATE NOT %d Y=!A; PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_NOT_"));
786  fprintf(f, "GATE AND %d Y=A*B; PIN * NONINV 1 999 1 0 1 0\n", get_cell_cost("$_AND_"));
787  fprintf(f, "GATE NAND %d Y=!(A*B); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_NAND_"));
788  fprintf(f, "GATE OR %d Y=A+B; PIN * NONINV 1 999 1 0 1 0\n", get_cell_cost("$_OR_"));
789  fprintf(f, "GATE NOR %d Y=!(A+B); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_NOR_"));
790  fprintf(f, "GATE XOR %d Y=(A*!B)+(!A*B); PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_XOR_"));
791  fprintf(f, "GATE XNOR %d Y=(A*B)+(!A*!B); PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_XNOR_"));
792  fprintf(f, "GATE AOI3 %d Y=!((A*B)+C); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_AOI3_"));
793  fprintf(f, "GATE OAI3 %d Y=!((A+B)*C); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_OAI3_"));
794  fprintf(f, "GATE AOI4 %d Y=!((A*B)+(C*D)); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_AOI4_"));
795  fprintf(f, "GATE OAI4 %d Y=!((A+B)*(C+D)); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_OAI4_"));
796  fprintf(f, "GATE MUX %d Y=(A*B)+(S*B)+(!S*A); PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_MUX_"));
797  fclose(f);
798 
799  if (lut_mode) {
800  buffer = stringf("%s/lutdefs.txt", tempdir_name.c_str());
801  f = fopen(buffer.c_str(), "wt");
802  if (f == NULL)
803  log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
804  for (int i = 0; i < lut_mode; i++)
805  fprintf(f, "%d 1.00 1.00\n", i+1);
806  fclose(f);
807  }
808 
809  buffer = stringf("%s -s -f %s/abc.script 2>&1", exe_file.c_str(), tempdir_name.c_str());
810  log("Running ABC command: %s\n", buffer.c_str());
811 
812  abc_output_filter filt;
813  int ret = run_command(buffer, std::bind(&abc_output_filter::next_line, filt, std::placeholders::_1));
814  if (ret != 0)
815  log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret);
816 
817  buffer = stringf("%s/%s", tempdir_name.c_str(), "output.blif");
818  f = fopen(buffer.c_str(), "rt");
819  if (f == NULL)
820  log_error("Can't open ABC output file `%s'.\n", buffer.c_str());
821 
822  bool builtin_lib = liberty_file.empty() && script_file.empty() && !lut_mode;
823  RTLIL::Design *mapped_design = abc_parse_blif(f, builtin_lib ? "\\DFF" : "\\_dff_");
824 
825  fclose(f);
826 
827  log_header("Re-integrating ABC results.\n");
828  RTLIL::Module *mapped_mod = mapped_design->modules_["\\netlist"];
829  if (mapped_mod == NULL)
830  log_error("ABC output file does not contain a module `netlist'.\n");
831  for (auto &it : mapped_mod->wires_) {
832  RTLIL::Wire *w = it.second;
833  RTLIL::Wire *wire = module->addWire(remap_name(w->name));
834  design->select(module, wire);
835  }
836 
837  std::map<std::string, int> cell_stats;
838  if (builtin_lib)
839  {
840  for (auto &it : mapped_mod->cells_) {
841  RTLIL::Cell *c = it.second;
842  cell_stats[RTLIL::unescape_id(c->type)]++;
843  if (c->type == "\\ZERO" || c->type == "\\ONE") {
844  RTLIL::SigSig conn;
845  conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]);
846  conn.second = RTLIL::SigSpec(c->type == "\\ZERO" ? 0 : 1, 1);
847  module->connect(conn);
848  continue;
849  }
850  if (c->type == "\\BUF") {
851  RTLIL::SigSig conn;
852  conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]);
853  conn.second = RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]);
854  module->connect(conn);
855  continue;
856  }
857  if (c->type == "\\NOT") {
858  RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_NOT_");
859  cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
860  cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
861  design->select(module, cell);
862  continue;
863  }
864  if (c->type == "\\AND" || c->type == "\\OR" || c->type == "\\XOR" || c->type == "\\NAND" || c->type == "\\NOR" || c->type == "\\XNOR") {
865  RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_");
866  cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
867  cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
868  cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
869  design->select(module, cell);
870  continue;
871  }
872  if (c->type == "\\MUX") {
873  RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX_");
874  cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
875  cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
876  cell->setPort("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\S").as_wire()->name)]));
877  cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
878  design->select(module, cell);
879  continue;
880  }
881  if (c->type == "\\AOI3" || c->type == "\\OAI3") {
882  RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_");
883  cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
884  cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
885  cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)]));
886  cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
887  design->select(module, cell);
888  continue;
889  }
890  if (c->type == "\\AOI4" || c->type == "\\OAI4") {
891  RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_");
892  cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
893  cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
894  cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)]));
895  cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
896  cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
897  design->select(module, cell);
898  continue;
899  }
900  if (c->type == "\\DFF") {
901  log_assert(clk_sig.size() == 1);
902  RTLIL::Cell *cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_");
903  cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
904  cell->setPort("\\Q", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Q").as_wire()->name)]));
905  cell->setPort("\\C", clk_sig);
906  design->select(module, cell);
907  continue;
908  }
909  log_abort();
910  }
911  }
912  else
913  {
914  for (auto &it : mapped_mod->cells_)
915  {
916  RTLIL::Cell *c = it.second;
917  cell_stats[RTLIL::unescape_id(c->type)]++;
918  if (c->type == "\\_const0_" || c->type == "\\_const1_") {
919  RTLIL::SigSig conn;
920  conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->connections().begin()->second.as_wire()->name)]);
921  conn.second = RTLIL::SigSpec(c->type == "\\_const0_" ? 0 : 1, 1);
922  module->connect(conn);
923  continue;
924  }
925  if (c->type == "\\_dff_") {
926  log_assert(clk_sig.size() == 1);
927  RTLIL::Cell *cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_");
928  cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
929  cell->setPort("\\Q", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Q").as_wire()->name)]));
930  cell->setPort("\\C", clk_sig);
931  design->select(module, cell);
932  continue;
933  }
934  RTLIL::Cell *cell = module->addCell(remap_name(c->name), c->type);
935  cell->parameters = c->parameters;
936  for (auto &conn : c->connections()) {
937  RTLIL::SigSpec newsig;
938  for (auto &c : conn.second.chunks()) {
939  if (c.width == 0)
940  continue;
941  log_assert(c.width == 1);
942  newsig.append(module->wires_[remap_name(c.wire->name)]);
943  }
944  cell->setPort(conn.first, newsig);
945  }
946  design->select(module, cell);
947  }
948  }
949 
950  for (auto conn : mapped_mod->connections()) {
951  if (!conn.first.is_fully_const())
952  conn.first = RTLIL::SigSpec(module->wires_[remap_name(conn.first.as_wire()->name)]);
953  if (!conn.second.is_fully_const())
954  conn.second = RTLIL::SigSpec(module->wires_[remap_name(conn.second.as_wire()->name)]);
955  module->connect(conn);
956  }
957 
958  for (auto &it : cell_stats)
959  log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second);
960  int in_wires = 0, out_wires = 0;
961  for (auto &si : signal_list)
962  if (si.is_port) {
963  char buffer[100];
964  snprintf(buffer, 100, "\\n%d", si.id);
965  RTLIL::SigSig conn;
966  if (si.type != G(NONE)) {
967  conn.first = si.bit;
968  conn.second = RTLIL::SigSpec(module->wires_[remap_name(buffer)]);
969  out_wires++;
970  } else {
971  conn.first = RTLIL::SigSpec(module->wires_[remap_name(buffer)]);
972  conn.second = si.bit;
973  in_wires++;
974  }
975  module->connect(conn);
976  }
977  log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
978  log("ABC RESULTS: input signals: %8d\n", in_wires);
979  log("ABC RESULTS: output signals: %8d\n", out_wires);
980 
981  delete mapped_design;
982  }
983  else
984  {
985  log("Don't call ABC as there is nothing to map.\n");
986  }
987 
988  if (cleanup)
989  {
990  log_header("Removing temp directory `%s':\n", tempdir_name.c_str());
991  remove_directory(tempdir_name);
992  }
993 
994  log_pop();
995 }
RTLIL::IdString::c_str
const char * c_str() const
Definition: rtlil.h:178
RTLIL::Design::selected
bool selected(T1 *module) const
Definition: rtlil.h:551
map_autoidx
int map_autoidx
Definition: abc.cc:92
ABC_FAST_COMMAND_DFL
#define ABC_FAST_COMMAND_DFL
Definition: abc.cc:40
add_echos_to_abc_cmd
std::string add_echos_to_abc_cmd(std::string str)
Definition: abc.cc:453
stringf
std::string stringf(const char *fmt,...)
Definition: yosys.cc:58
remove_directory
void remove_directory(std::string dirname)
Definition: yosys.cc:308
extract_cell
void extract_cell(RTLIL::Cell *cell, bool keepff)
Definition: abc.cc:142
RTLIL::Module::addCell
RTLIL::Cell * addCell(RTLIL::IdString name, RTLIL::IdString type)
Definition: rtlil.cc:1353
clk_polarity
bool clk_polarity
Definition: abc.cc:98
log_header
void log_header(const char *format,...)
Definition: log.cc:188
RTLIL::Module::connections
const std::vector< RTLIL::SigSig > & connections() const
Definition: rtlil.cc:1307
RTLIL::Module::wires_
std::map< RTLIL::IdString, RTLIL::Wire * > wires_
Definition: rtlil.h:595
RTLIL::unescape_id
static std::string unescape_id(std::string str)
Definition: rtlil.h:257
mark_port
void mark_port(RTLIL::SigSpec sig)
Definition: abc.cc:135
log_signal
const char * log_signal(const RTLIL::SigSpec &sig, bool autoint)
Definition: log.cc:269
RTLIL::Cell::name
RTLIL::IdString name
Definition: rtlil.h:853
RTLIL::Cell::setPort
void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
Definition: rtlil.cc:1789
log_error
void log_error(const char *format,...)
Definition: log.cc:204
module
RTLIL::Module * module
Definition: abc.cc:94
RTLIL::Cell::type
RTLIL::IdString type
Definition: rtlil.h:854
RTLIL::Cell::parameters
std::map< RTLIL::IdString, RTLIL::Const > parameters
Definition: rtlil.h:856
log_pop
void log_pop()
Definition: log.cc:237
handle_loops
void handle_loops()
Definition: abc.cc:320
RTLIL::SigSpec::size
int size() const
Definition: rtlil.h:1019
log_abort
#define log_abort()
Definition: log.h:84
RTLIL::Design::select
void select(T1 *module, T2 *member)
Definition: rtlil.h:559
run_command
int run_command(const std::string &command, std::function< void(const std::string &)> process_line)
Definition: yosys.cc:195
assign_map
SigMap assign_map
Definition: abc.cc:93
RTLIL::escape_id
static std::string escape_id(std::string str)
Definition: rtlil.h:251
abc_parse_blif
RTLIL::Design * abc_parse_blif(FILE *f, std::string dff_name)
Definition: blifparse.cc:52
ABC_COMMAND_LIB
#define ABC_COMMAND_LIB
Definition: abc.cc:32
ABC_COMMAND_CTR
#define ABC_COMMAND_CTR
Definition: abc.cc:33
SigMap::set
void set(RTLIL::Module *module)
Definition: sigtools.h:273
RTLIL::Module::connect
void connect(const RTLIL::SigSig &conn)
Definition: rtlil.cc:1278
G
#define G(_name)
Definition: abc.cc:81
RTLIL::Cell::getPort
const RTLIL::SigSpec & getPort(RTLIL::IdString portname) const
Definition: rtlil.cc:1809
GetSize
int GetSize(RTLIL::Wire *wire)
Definition: yosys.cc:334
log_assert
#define log_assert(_assert_expr_)
Definition: log.h:85
RTLIL::Module::addWire
RTLIL::Wire * addWire(RTLIL::IdString name, int width=1)
Definition: rtlil.cc:1331
RTLIL::Module::name
RTLIL::IdString name
Definition: rtlil.h:599
signal_list
std::vector< gate_t > signal_list
Definition: abc.cc:95
get_cell_cost
YOSYS_NAMESPACE_BEGIN int get_cell_cost(RTLIL::Cell *cell, std::map< RTLIL::Module *, int > *mod_cost_cache=nullptr)
Definition: cost.h:77
make_temp_dir
std::string make_temp_dir(std::string template_str)
Definition: yosys.cc:273
clk_sig
RTLIL::SigSpec clk_sig
Definition: abc.cc:99
RTLIL::Wire::name
RTLIL::IdString name
Definition: rtlil.h:825
abc_output_filter
Definition: abc.cc:496
ABC_FAST_COMMAND_LUT
#define ABC_FAST_COMMAND_LUT
Definition: abc.cc:39
RTLIL::IdString::substr
std::string substr(size_t pos=0, size_t len=std::string::npos) const
Definition: rtlil.h:208
signal_map
std::map< RTLIL::SigBit, int > signal_map
Definition: abc.cc:96
RTLIL::Design::modules_
std::map< RTLIL::IdString, RTLIL::Module * > modules_
Definition: rtlil.h:507
abc_output_filter::next_line
void next_line(const std::string &line)
Definition: abc.cc:538
NULL
#define NULL
Definition: NumberlikeArray.hh:6
RTLIL::Module::cells_
std::map< RTLIL::IdString, RTLIL::Cell * > cells_
Definition: rtlil.h:596
log
void log(const char *format,...)
Definition: log.cc:180
ABC_FAST_COMMAND_CTR
#define ABC_FAST_COMMAND_CTR
Definition: abc.cc:38
remap_name
std::string remap_name(RTLIL::IdString abc_name)
Definition: abc.cc:284
log_push
void log_push()
Definition: log.cc:232
RTLIL::SigSpec::append
void append(const RTLIL::SigSpec &signal)
Definition: rtlil.cc:2523
ABC_FAST_COMMAND_LIB
#define ABC_FAST_COMMAND_LIB
Definition: abc.cc:37
AST_INTERNAL::current_module
AstModule * current_module
Definition: ast.cc:62
RTLIL::SigSpec::as_wire
RTLIL::Wire * as_wire() const
Definition: rtlil.cc:2868
RTLIL::SigSig
std::pair< SigSpec, SigSpec > SigSig
Definition: rtlil.h:71
RTLIL::Cell::connections
const std::map< RTLIL::IdString, RTLIL::SigSpec > & connections() const
Definition: rtlil.cc:1814
autoidx
YOSYS_NAMESPACE_BEGIN int autoidx
Definition: yosys.cc:51
ABC_COMMAND_DFL
#define ABC_COMMAND_DFL
Definition: abc.cc:35
ABC_COMMAND_LUT
#define ABC_COMMAND_LUT
Definition: abc.cc:34

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std::string add_echos_to_abc_cmd ( std::string  str)

Definition at line 453 of file abc.cc.

454 {
455  std::string new_str, token;
456  for (size_t i = 0; i < str.size(); i++) {
457  token += str[i];
458  if (str[i] == ';') {
459  while (i+1 < str.size() && str[i+1] == ' ')
460  i++;
461  if (!new_str.empty())
462  new_str += "echo; ";
463  new_str += "echo + " + token + " " + token + " ";
464  token.clear();
465  }
466  }
467 
468  if (!token.empty()) {
469  if (!new_str.empty())
470  new_str += "echo; echo + " + token + "; ";
471  new_str += token;
472  }
473 
474  return new_str;
475 }

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void dump_loop_graph ( FILE *  f,
int &  nr,
std::map< int, std::set< int >> &  edges,
std::set< int > &  workpool,
std::vector< int > &  in_counts 
)

Definition at line 291 of file abc.cc.

292 {
293  if (f == NULL)
294  return;
295 
296  log("Dumping loop state graph to slide %d.\n", ++nr);
297 
298  fprintf(f, "digraph \"slide%d\" {\n", nr);
299  fprintf(f, " label=\"slide%d\";\n", nr);
300  fprintf(f, " rankdir=\"TD\";\n");
301 
302  std::set<int> nodes;
303  for (auto &e : edges) {
304  nodes.insert(e.first);
305  for (auto n : e.second)
306  nodes.insert(n);
307  }
308 
309  for (auto n : nodes)
310  fprintf(f, " n%d [label=\"%s\\nid=%d, count=%d\"%s];\n", n, log_signal(signal_list[n].bit),
311  n, in_counts[n], workpool.count(n) ? ", shape=box" : "");
312 
313  for (auto &e : edges)
314  for (auto n : e.second)
315  fprintf(f, " n%d -> n%d;\n", e.first, n);
316 
317  fprintf(f, "}\n");
318 }
log_signal
const char * log_signal(const RTLIL::SigSpec &sig, bool autoint)
Definition: log.cc:269
generate.n
tuple n
Definition: fsm/generate.py:59
signal_list
std::vector< gate_t > signal_list
Definition: abc.cc:95
NULL
#define NULL
Definition: NumberlikeArray.hh:6
log
void log(const char *format,...)
Definition: log.cc:180

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void extract_cell ( RTLIL::Cell *  cell,
bool  keepff 
)

Definition at line 142 of file abc.cc.

143 {
144  if (cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_")
145  {
146  if (clk_polarity != (cell->type == "$_DFF_P_"))
147  return;
148  if (clk_sig != assign_map(cell->getPort("\\C")))
149  return;
150 
151  RTLIL::SigSpec sig_d = cell->getPort("\\D");
152  RTLIL::SigSpec sig_q = cell->getPort("\\Q");
153 
154  if (keepff)
155  for (auto &c : sig_q.chunks())
156  if (c.wire != NULL)
157  c.wire->attributes["\\keep"] = 1;
158 
159  assign_map.apply(sig_d);
160  assign_map.apply(sig_q);
161 
162  map_signal(sig_q, G(FF), map_signal(sig_d));
163 
164  module->remove(cell);
165  return;
166  }
167 
168  if (cell->type.in("$_BUF_", "$_NOT_"))
169  {
170  RTLIL::SigSpec sig_a = cell->getPort("\\A");
171  RTLIL::SigSpec sig_y = cell->getPort("\\Y");
172 
173  assign_map.apply(sig_a);
174  assign_map.apply(sig_y);
175 
176  map_signal(sig_y, cell->type == "$_BUF_" ? G(BUF) : G(NOT), map_signal(sig_a));
177 
178  module->remove(cell);
179  return;
180  }
181 
182  if (cell->type.in("$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_"))
183  {
184  RTLIL::SigSpec sig_a = cell->getPort("\\A");
185  RTLIL::SigSpec sig_b = cell->getPort("\\B");
186  RTLIL::SigSpec sig_y = cell->getPort("\\Y");
187 
188  assign_map.apply(sig_a);
189  assign_map.apply(sig_b);
190  assign_map.apply(sig_y);
191 
192  int mapped_a = map_signal(sig_a);
193  int mapped_b = map_signal(sig_b);
194 
195  if (cell->type == "$_AND_")
196  map_signal(sig_y, G(AND), mapped_a, mapped_b);
197  else if (cell->type == "$_NAND_")
198  map_signal(sig_y, G(NAND), mapped_a, mapped_b);
199  else if (cell->type == "$_OR_")
200  map_signal(sig_y, G(OR), mapped_a, mapped_b);
201  else if (cell->type == "$_NOR_")
202  map_signal(sig_y, G(NOR), mapped_a, mapped_b);
203  else if (cell->type == "$_XOR_")
204  map_signal(sig_y, G(XOR), mapped_a, mapped_b);
205  else if (cell->type == "$_XNOR_")
206  map_signal(sig_y, G(XNOR), mapped_a, mapped_b);
207  else
208  log_abort();
209 
210  module->remove(cell);
211  return;
212  }
213 
214  if (cell->type == "$_MUX_")
215  {
216  RTLIL::SigSpec sig_a = cell->getPort("\\A");
217  RTLIL::SigSpec sig_b = cell->getPort("\\B");
218  RTLIL::SigSpec sig_s = cell->getPort("\\S");
219  RTLIL::SigSpec sig_y = cell->getPort("\\Y");
220 
221  assign_map.apply(sig_a);
222  assign_map.apply(sig_b);
223  assign_map.apply(sig_s);
224  assign_map.apply(sig_y);
225 
226  int mapped_a = map_signal(sig_a);
227  int mapped_b = map_signal(sig_b);
228  int mapped_s = map_signal(sig_s);
229 
230  map_signal(sig_y, G(MUX), mapped_a, mapped_b, mapped_s);
231 
232  module->remove(cell);
233  return;
234  }
235 
236  if (cell->type.in("$_AOI3_", "$_OAI3_"))
237  {
238  RTLIL::SigSpec sig_a = cell->getPort("\\A");
239  RTLIL::SigSpec sig_b = cell->getPort("\\B");
240  RTLIL::SigSpec sig_c = cell->getPort("\\C");
241  RTLIL::SigSpec sig_y = cell->getPort("\\Y");
242 
243  assign_map.apply(sig_a);
244  assign_map.apply(sig_b);
245  assign_map.apply(sig_c);
246  assign_map.apply(sig_y);
247 
248  int mapped_a = map_signal(sig_a);
249  int mapped_b = map_signal(sig_b);
250  int mapped_c = map_signal(sig_c);
251 
252  map_signal(sig_y, cell->type == "$_AOI3_" ? G(AOI3) : G(OAI3), mapped_a, mapped_b, mapped_c);
253 
254  module->remove(cell);
255  return;
256  }
257 
258  if (cell->type.in("$_AOI4_", "$_OAI4_"))
259  {
260  RTLIL::SigSpec sig_a = cell->getPort("\\A");
261  RTLIL::SigSpec sig_b = cell->getPort("\\B");
262  RTLIL::SigSpec sig_c = cell->getPort("\\C");
263  RTLIL::SigSpec sig_d = cell->getPort("\\D");
264  RTLIL::SigSpec sig_y = cell->getPort("\\Y");
265 
266  assign_map.apply(sig_a);
267  assign_map.apply(sig_b);
268  assign_map.apply(sig_c);
269  assign_map.apply(sig_d);
270  assign_map.apply(sig_y);
271 
272  int mapped_a = map_signal(sig_a);
273  int mapped_b = map_signal(sig_b);
274  int mapped_c = map_signal(sig_c);
275  int mapped_d = map_signal(sig_d);
276 
277  map_signal(sig_y, cell->type == "$_AOI4_" ? G(AOI4) : G(OAI4), mapped_a, mapped_b, mapped_c, mapped_d);
278 
279  module->remove(cell);
280  return;
281  }
282 }
clk_polarity
bool clk_polarity
Definition: abc.cc:98
module
RTLIL::Module * module
Definition: abc.cc:94
RTLIL::Cell::type
RTLIL::IdString type
Definition: rtlil.h:854
log_abort
#define log_abort()
Definition: log.h:84
RTLIL::IdString::in
bool in(T first, Args...rest)
Definition: rtlil.h:241
SigMap::apply
void apply(RTLIL::SigBit &bit) const
Definition: sigtools.h:383
assign_map
SigMap assign_map
Definition: abc.cc:93
G
#define G(_name)
Definition: abc.cc:81
RTLIL::Cell::getPort
const RTLIL::SigSpec & getPort(RTLIL::IdString portname) const
Definition: rtlil.cc:1809
map_signal
int map_signal(RTLIL::SigBit bit, gate_type_t gate_type=G(NONE), int in1=-1, int in2=-1, int in3=-1, int in4=-1)
Definition: abc.cc:101
clk_sig
RTLIL::SigSpec clk_sig
Definition: abc.cc:99
NULL
#define NULL
Definition: NumberlikeArray.hh:6
RTLIL::Module::remove
void remove(const std::set< RTLIL::Wire * > &wires)
Definition: rtlil.cc:1158
RTLIL::SigSpec::chunks
const std::vector< RTLIL::SigChunk > & chunks() const
Definition: rtlil.h:1016

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std::string fold_abc_cmd ( std::string  str)

Definition at line 477 of file abc.cc.

478 {
479  std::string token, new_str = " ";
480  int char_counter = 10;
481 
482  for (size_t i = 0; i <= str.size(); i++) {
483  if (i < str.size())
484  token += str[i];
485  if (i == str.size() || str[i] == ';') {
486  if (char_counter + token.size() > 75)
487  new_str += "\n ", char_counter = 14;
488  new_str += token, char_counter += token.size();
489  token.clear();
490  }
491  }
492 
493  return new_str;
494 }

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void handle_loops ( )

Definition at line 320 of file abc.cc.

321 {
322  // http://en.wikipedia.org/wiki/Topological_sorting
323  // (Kahn, Arthur B. (1962), "Topological sorting of large networks")
324 
325  std::map<int, std::set<int>> edges;
326  std::vector<int> in_edges_count(signal_list.size());
327  std::set<int> workpool;
328 
329  FILE *dot_f = NULL;
330  int dot_nr = 0;
331 
332  // uncomment for troubleshooting the loop detection code
333  // dot_f = fopen("test.dot", "w");
334 
335  for (auto &g : signal_list) {
336  if (g.type == G(NONE) || g.type == G(FF)) {
337  workpool.insert(g.id);
338  } else {
339  if (g.in1 >= 0) {
340  edges[g.in1].insert(g.id);
341  in_edges_count[g.id]++;
342  }
343  if (g.in2 >= 0 && g.in2 != g.in1) {
344  edges[g.in2].insert(g.id);
345  in_edges_count[g.id]++;
346  }
347  if (g.in3 >= 0 && g.in3 != g.in2 && g.in3 != g.in1) {
348  edges[g.in3].insert(g.id);
349  in_edges_count[g.id]++;
350  }
351  if (g.in4 >= 0 && g.in4 != g.in3 && g.in4 != g.in2 && g.in4 != g.in1) {
352  edges[g.in4].insert(g.id);
353  in_edges_count[g.id]++;
354  }
355  }
356  }
357 
358  dump_loop_graph(dot_f, dot_nr, edges, workpool, in_edges_count);
359 
360  while (workpool.size() > 0)
361  {
362  int id = *workpool.begin();
363  workpool.erase(id);
364 
365  // log("Removing non-loop node %d from graph: %s\n", id, log_signal(signal_list[id].bit));
366 
367  for (int id2 : edges[id]) {
368  log_assert(in_edges_count[id2] > 0);
369  if (--in_edges_count[id2] == 0)
370  workpool.insert(id2);
371  }
372  edges.erase(id);
373 
374  dump_loop_graph(dot_f, dot_nr, edges, workpool, in_edges_count);
375 
376  while (workpool.size() == 0)
377  {
378  if (edges.size() == 0)
379  break;
380 
381  int id1 = edges.begin()->first;
382 
383  for (auto &edge_it : edges) {
384  int id2 = edge_it.first;
385  RTLIL::Wire *w1 = signal_list[id1].bit.wire;
386  RTLIL::Wire *w2 = signal_list[id2].bit.wire;
387  if (w1 == NULL)
388  id1 = id2;
389  else if (w2 == NULL)
390  continue;
391  else if (w1->name[0] == '$' && w2->name[0] == '\\')
392  id1 = id2;
393  else if (w1->name[0] == '\\' && w2->name[0] == '$')
394  continue;
395  else if (edges[id1].size() < edges[id2].size())
396  id1 = id2;
397  else if (edges[id1].size() > edges[id2].size())
398  continue;
399  else if (w2->name.str() < w1->name.str())
400  id1 = id2;
401  }
402 
403  if (edges[id1].size() == 0) {
404  edges.erase(id1);
405  continue;
406  }
407 
408  log_assert(signal_list[id1].bit.wire != NULL);
409 
410  std::stringstream sstr;
411  sstr << "$abcloop$" << (autoidx++);
412  RTLIL::Wire *wire = module->addWire(sstr.str());
413 
414  bool first_line = true;
415  for (int id2 : edges[id1]) {
416  if (first_line)
417  log("Breaking loop using new signal %s: %s -> %s\n", log_signal(RTLIL::SigSpec(wire)),
418  log_signal(signal_list[id1].bit), log_signal(signal_list[id2].bit));
419  else
420  log(" %*s %s -> %s\n", int(strlen(log_signal(RTLIL::SigSpec(wire)))), "",
421  log_signal(signal_list[id1].bit), log_signal(signal_list[id2].bit));
422  first_line = false;
423  }
424 
425  int id3 = map_signal(RTLIL::SigSpec(wire));
426  signal_list[id1].is_port = true;
427  signal_list[id3].is_port = true;
428  log_assert(id3 == int(in_edges_count.size()));
429  in_edges_count.push_back(0);
430  workpool.insert(id3);
431 
432  for (int id2 : edges[id1]) {
433  if (signal_list[id2].in1 == id1)
434  signal_list[id2].in1 = id3;
435  if (signal_list[id2].in2 == id1)
436  signal_list[id2].in2 = id3;
437  if (signal_list[id2].in3 == id1)
438  signal_list[id2].in3 = id3;
439  if (signal_list[id2].in4 == id1)
440  signal_list[id2].in4 = id3;
441  }
442  edges[id1].swap(edges[id3]);
443 
444  module->connect(RTLIL::SigSig(signal_list[id3].bit, signal_list[id1].bit));
445  dump_loop_graph(dot_f, dot_nr, edges, workpool, in_edges_count);
446  }
447  }
448 
449  if (dot_f != NULL)
450  fclose(dot_f);
451 }
RTLIL::IdString::str
std::string str() const
Definition: rtlil.h:182
log_signal
const char * log_signal(const RTLIL::SigSpec &sig, bool autoint)
Definition: log.cc:269
module
RTLIL::Module * module
Definition: abc.cc:94
RTLIL::Module::connect
void connect(const RTLIL::SigSig &conn)
Definition: rtlil.cc:1278
G
#define G(_name)
Definition: abc.cc:81
log_assert
#define log_assert(_assert_expr_)
Definition: log.h:85
dump_loop_graph
void dump_loop_graph(FILE *f, int &nr, std::map< int, std::set< int >> &edges, std::set< int > &workpool, std::vector< int > &in_counts)
Definition: abc.cc:291
RTLIL::Module::addWire
RTLIL::Wire * addWire(RTLIL::IdString name, int width=1)
Definition: rtlil.cc:1331
map_signal
int map_signal(RTLIL::SigBit bit, gate_type_t gate_type=G(NONE), int in1=-1, int in2=-1, int in3=-1, int in4=-1)
Definition: abc.cc:101
signal_list
std::vector< gate_t > signal_list
Definition: abc.cc:95
RTLIL::Wire::name
RTLIL::IdString name
Definition: rtlil.h:825
NULL
#define NULL
Definition: NumberlikeArray.hh:6
log
void log(const char *format,...)
Definition: log.cc:180
RTLIL::SigSig
std::pair< SigSpec, SigSpec > SigSig
Definition: rtlil.h:71
autoidx
YOSYS_NAMESPACE_BEGIN int autoidx
Definition: yosys.cc:51

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int map_signal ( RTLIL::SigBit  bit,
gate_type_t  gate_type = G(NONE),
int  in1 = -1,
int  in2 = -1,
int  in3 = -1,
int  in4 = -1 
)

Definition at line 101 of file abc.cc.

102 {
103  assign_map.apply(bit);
104 
105  if (signal_map.count(bit) == 0) {
106  gate_t gate;
107  gate.id = signal_list.size();
108  gate.type = G(NONE);
109  gate.in1 = -1;
110  gate.in2 = -1;
111  gate.in3 = -1;
112  gate.in4 = -1;
113  gate.is_port = false;
114  gate.bit = bit;
115  signal_list.push_back(gate);
116  signal_map[bit] = gate.id;
117  }
118 
119  gate_t &gate = signal_list[signal_map[bit]];
120 
121  if (gate_type != G(NONE))
122  gate.type = gate_type;
123  if (in1 >= 0)
124  gate.in1 = in1;
125  if (in2 >= 0)
126  gate.in2 = in2;
127  if (in3 >= 0)
128  gate.in3 = in3;
129  if (in4 >= 0)
130  gate.in4 = in4;
131 
132  return gate.id;
133 }
gate_t::bit
RTLIL::SigBit bit
Definition: abc.cc:89
gate_t::is_port
bool is_port
Definition: abc.cc:88
gate_t
Definition: abc.cc:83
gate_t::in4
int in4
Definition: abc.cc:87
gate_t::in2
int in2
Definition: abc.cc:87
SigMap::apply
void apply(RTLIL::SigBit &bit) const
Definition: sigtools.h:383
assign_map
SigMap assign_map
Definition: abc.cc:93
gate_t::type
gate_type_t type
Definition: abc.cc:86
G
#define G(_name)
Definition: abc.cc:81
gate_t::in3
int in3
Definition: abc.cc:87
signal_list
std::vector< gate_t > signal_list
Definition: abc.cc:95
signal_map
std::map< RTLIL::SigBit, int > signal_map
Definition: abc.cc:96
gate_t::id
int id
Definition: abc.cc:85
gate_t::in1
int in1
Definition: abc.cc:87

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void mark_port ( RTLIL::SigSpec  sig)

Definition at line 135 of file abc.cc.

136 {
137  for (auto &bit : assign_map(sig))
138  if (bit.wire != NULL && signal_map.count(bit) > 0)
139  signal_list[signal_map[bit]].is_port = true;
140 }
assign_map
SigMap assign_map
Definition: abc.cc:93
signal_list
std::vector< gate_t > signal_list
Definition: abc.cc:95
signal_map
std::map< RTLIL::SigBit, int > signal_map
Definition: abc.cc:96
NULL
#define NULL
Definition: NumberlikeArray.hh:6

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std::string remap_name ( RTLIL::IdString  abc_name)

Definition at line 284 of file abc.cc.

285 {
286  std::stringstream sstr;
287  sstr << "$abc$" << map_autoidx << "$" << abc_name.substr(1);
288  return sstr.str();
289 }
map_autoidx
int map_autoidx
Definition: abc.cc:92
RTLIL::IdString::substr
std::string substr(size_t pos=0, size_t len=std::string::npos) const
Definition: rtlil.h:208

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Variable Documentation

AbcPass AbcPass
SigMap assign_map

Definition at line 93 of file abc.cc.

bool clk_polarity

Definition at line 98 of file abc.cc.

RTLIL::SigSpec clk_sig

Definition at line 99 of file abc.cc.

int map_autoidx

Definition at line 92 of file abc.cc.

RTLIL::Module* module

Definition at line 94 of file abc.cc.

std::vector<gate_t> signal_list

Definition at line 95 of file abc.cc.

std::map<RTLIL::SigBit, int> signal_map

Definition at line 96 of file abc.cc.