Go to the source code of this file.
Definition at line 77 of file cost.h.
std::map< RTLIL::IdString, RTLIL::Const > parameters
YOSYS_NAMESPACE_BEGIN int get_cell_cost(RTLIL::Cell *cell, std::map< RTLIL::Module *, int > *mod_cost_cache=nullptr)
Definition at line 29 of file cost.h.
32 static std::map<RTLIL::IdString, int> gate_cost = {
48 if (gate_cost.count(type))
49 return gate_cost.at(type);
51 if (parameters.empty() && design && design->
module(type))
55 if (mod->attributes.count(
"\\cost"))
56 return mod->attributes.at(
"\\cost").as_int();
58 std::map<RTLIL::Module*, int> local_mod_cost_cache;
59 if (mod_cost_cache ==
nullptr)
60 mod_cost_cache = &local_mod_cost_cache;
62 if (mod_cost_cache->count(mod))
63 return mod_cost_cache->at(mod);
66 for (
auto c : mod->
cells())
69 (*mod_cost_cache)[mod] = module_cost;
void log_warning(const char *format,...)
int GetSize(RTLIL::Wire *wire)
YOSYS_NAMESPACE_BEGIN int get_cell_cost(RTLIL::Cell *cell, std::map< RTLIL::Module *, int > *mod_cost_cache=nullptr)
RTLIL::Module * module(RTLIL::IdString name)
RTLIL::ObjRange< RTLIL::Cell * > cells()
const char * log_id(RTLIL::IdString str)