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Public Member Functions | Data Fields
AST_INTERNAL::ProcessGenerator Struct Reference
+ Collaboration diagram for AST_INTERNAL::ProcessGenerator:

Public Member Functions

 ProcessGenerator (AstNode *always, RTLIL::SigSpec initSyncSignalsArg=RTLIL::SigSpec())
 
void remove_unwanted_lvalue_bits (RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs)
 
RTLIL::SigSpec new_temp_signal (RTLIL::SigSpec sig)
 
void collect_lvalues (RTLIL::SigSpec &reg, AstNode *ast, bool type_eq, bool type_le, bool run_sort_and_unify=true)
 
void removeSignalFromCaseTree (const std::set< RTLIL::SigBit > &pattern, RTLIL::CaseRule *cs)
 
void addChunkActions (std::vector< RTLIL::SigSig > &actions, RTLIL::SigSpec lvalue, RTLIL::SigSpec rvalue, bool inSyncRule=false)
 
void processAst (AstNode *ast)
 

Data Fields

AstNode * always
 
RTLIL::SigSpec initSyncSignals
 
RTLIL::Process * proc
 
RTLIL::SigSpec outputSignals
 
RTLIL::CaseRule * current_case
 
stackmap< RTLIL::SigBit,
RTLIL::SigBit > 		subst_rvalue_map
 
stackmap< RTLIL::SigBit,
RTLIL::SigBit > 		subst_lvalue_map
 
std::map< RTLIL::Wire *, int > new_temp_count
 
RTLIL::SigSpec init_lvalue
 
RTLIL::SigSpec init_rvalue
 

Detailed Description

Definition at line 171 of file genrtlil.cc.

Constructor & Destructor Documentation

AST_INTERNAL::ProcessGenerator::ProcessGenerator ( AstNode *  always,
RTLIL::SigSpec  initSyncSignalsArg = RTLIL::SigSpec() 
)
inline

Definition at line 202 of file genrtlil.cc.

202  : always(always), initSyncSignals(initSyncSignalsArg)
203  {
204  // generate process and simple root case
205  proc = new RTLIL::Process;
206  proc->attributes["\\src"] = stringf("%s:%d", always->filename.c_str(), always->linenum);
207  proc->name = stringf("$proc$%s:%d$%d", always->filename.c_str(), always->linenum, autoidx++);
208  for (auto &attr : always->attributes) {
209  if (attr.second->type != AST_CONSTANT)
210  log_error("Attribute `%s' with non-constant value at %s:%d!\n",
211  attr.first.c_str(), always->filename.c_str(), always->linenum);
212  proc->attributes[attr.first] = attr.second->asAttrConst();
213  }
214  current_module->processes[proc->name] = proc;
215  current_case = &proc->root_case;
216 
217  // create initial temporary signal for all output registers
218  RTLIL::SigSpec subst_lvalue_from, subst_lvalue_to;
219  collect_lvalues(subst_lvalue_from, always, true, true);
220  subst_lvalue_to = new_temp_signal(subst_lvalue_from);
221  subst_lvalue_map = subst_lvalue_from.to_sigbit_map(subst_lvalue_to);
222 
223  bool found_anyedge_syncs = false;
224  for (auto child : always->children)
225  if (child->type == AST_EDGE)
226  found_anyedge_syncs = true;
227 
228  if (found_anyedge_syncs) {
229  log("Note: Assuming pure combinatorial block at %s:%d in\n", always->filename.c_str(), always->linenum);
230  log("compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending\n");
231  log("use of @* instead of @(...) for better match of synthesis and simulation.\n");
232  }
233 
234  // create syncs for the process
235  bool found_clocked_sync = false;
236  for (auto child : always->children)
237  if (child->type == AST_POSEDGE || child->type == AST_NEGEDGE) {
238  found_clocked_sync = true;
239  if (found_anyedge_syncs)
240  log_error("Found non-synthesizable event list at %s:%d!\n", always->filename.c_str(), always->linenum);
241  RTLIL::SyncRule *syncrule = new RTLIL::SyncRule;
242  syncrule->type = child->type == AST_POSEDGE ? RTLIL::STp : RTLIL::STn;
243  syncrule->signal = child->children[0]->genRTLIL();
244  addChunkActions(syncrule->actions, subst_lvalue_from, subst_lvalue_to, true);
245  proc->syncs.push_back(syncrule);
246  }
247  if (proc->syncs.empty()) {
248  RTLIL::SyncRule *syncrule = new RTLIL::SyncRule;
249  syncrule->type = RTLIL::STa;
250  syncrule->signal = RTLIL::SigSpec();
251  addChunkActions(syncrule->actions, subst_lvalue_from, subst_lvalue_to, true);
252  proc->syncs.push_back(syncrule);
253  }
254 
255  // create initial assignments for the temporary signals
256  if ((flag_nolatches || always->get_bool_attribute("\\nolatches") || current_module->get_bool_attribute("\\nolatches")) && !found_clocked_sync) {
257  subst_rvalue_map = subst_lvalue_from.to_sigbit_map(RTLIL::SigSpec(RTLIL::State::Sx, GetSize(subst_lvalue_from)));
258  } else {
259  addChunkActions(current_case->actions, subst_lvalue_to, subst_lvalue_from);
260  }
261 
262  // process the AST
263  for (auto child : always->children)
264  if (child->type == AST_BLOCK)
265  processAst(child);
266 
267  if (initSyncSignals.size() > 0)
268  {
269  RTLIL::SyncRule *sync = new RTLIL::SyncRule;
270  sync->type = RTLIL::SyncType::STi;
271  proc->syncs.push_back(sync);
272 
273  log_assert(init_lvalue.size() == init_rvalue.size());
274 
275  int offset = 0;
276  for (auto &init_lvalue_c : init_lvalue.chunks()) {
277  RTLIL::SigSpec lhs = init_lvalue_c;
278  RTLIL::SigSpec rhs = init_rvalue.extract(offset, init_lvalue_c.width);
279  remove_unwanted_lvalue_bits(lhs, rhs);
280  sync->actions.push_back(RTLIL::SigSig(lhs, rhs));
281  offset += lhs.size();
282  }
283  }
284 
285  outputSignals = RTLIL::SigSpec(subst_lvalue_from);
286  }
AST_INTERNAL::ProcessGenerator::subst_lvalue_map
stackmap< RTLIL::SigBit, RTLIL::SigBit > subst_lvalue_map
Definition: genrtlil.cc:193
stringf
std::string stringf(const char *fmt,...)
Definition: yosys.cc:58
AST_INTERNAL::ProcessGenerator::outputSignals
RTLIL::SigSpec outputSignals
Definition: genrtlil.cc:177
AST_INTERNAL::ProcessGenerator::init_lvalue
RTLIL::SigSpec init_lvalue
Definition: genrtlil.cc:200
AST_INTERNAL::ProcessGenerator::addChunkActions
void addChunkActions(std::vector< RTLIL::SigSig > &actions, RTLIL::SigSpec lvalue, RTLIL::SigSpec rvalue, bool inSyncRule=false)
Definition: genrtlil.cc:394
RTLIL::SyncRule::type
RTLIL::SyncType type
Definition: rtlil.h:1144
AST::AstNode::attributes
std::map< RTLIL::IdString, AstNode * > attributes
Definition: ast.h:152
log_error
void log_error(const char *format,...)
Definition: log.cc:204
RTLIL::SyncRule::signal
RTLIL::SigSpec signal
Definition: rtlil.h:1145
RTLIL::SigSpec::size
int size() const
Definition: rtlil.h:1019
AST_INTERNAL::ProcessGenerator::remove_unwanted_lvalue_bits
void remove_unwanted_lvalue_bits(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs)
Definition: genrtlil.cc:288
AST::AstNode::get_bool_attribute
bool get_bool_attribute(RTLIL::IdString id)
Definition: ast.cc:166
AST_INTERNAL::ProcessGenerator::proc
RTLIL::Process * proc
Definition: genrtlil.cc:176
AST_INTERNAL::ProcessGenerator::always
AstNode * always
Definition: genrtlil.cc:174
AST_INTERNAL::ProcessGenerator::collect_lvalues
void collect_lvalues(RTLIL::SigSpec &reg, AstNode *ast, bool type_eq, bool type_le, bool run_sort_and_unify=true)
Definition: genrtlil.cc:334
AST_INTERNAL::ProcessGenerator::current_case
RTLIL::CaseRule * current_case
Definition: genrtlil.cc:180
GetSize
int GetSize(RTLIL::Wire *wire)
Definition: yosys.cc:334
log_assert
#define log_assert(_assert_expr_)
Definition: log.h:85
AST_INTERNAL::ProcessGenerator::processAst
void processAst(AstNode *ast)
Definition: genrtlil.cc:416
RTLIL::SyncRule::actions
std::vector< RTLIL::SigSig > actions
Definition: rtlil.h:1146
AST_INTERNAL::ProcessGenerator::new_temp_signal
RTLIL::SigSpec new_temp_signal(RTLIL::SigSpec sig)
Definition: genrtlil.cc:305
RTLIL::Process::name
RTLIL::IdString name
Definition: rtlil.h:1154
RTLIL::Module::processes
std::map< RTLIL::IdString, RTLIL::Process * > processes
Definition: rtlil.h:602
AST_INTERNAL::ProcessGenerator::subst_rvalue_map
stackmap< RTLIL::SigBit, RTLIL::SigBit > subst_rvalue_map
Definition: genrtlil.cc:187
AST_INTERNAL::ProcessGenerator::init_rvalue
RTLIL::SigSpec init_rvalue
Definition: genrtlil.cc:200
AST::AstNode::filename
std::string filename
Definition: ast.h:175
log
void log(const char *format,...)
Definition: log.cc:180
RTLIL::Process::syncs
std::vector< RTLIL::SyncRule * > syncs
Definition: rtlil.h:1157
RTLIL::SigSpec::extract
RTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other=NULL) const
Definition: rtlil.cc:2414
AST_INTERNAL::flag_nolatches
bool flag_nolatches
Definition: ast.cc:56
AST::AstNode::children
std::vector< AstNode * > children
Definition: ast.h:149
RTLIL::CaseRule::actions
std::vector< RTLIL::SigSig > actions
Definition: rtlil.h:1120
AST::AstNode::linenum
int linenum
Definition: ast.h:176
AST_INTERNAL::current_module
AstModule * current_module
Definition: ast.cc:62
RTLIL::SigSpec::to_sigbit_map
std::map< RTLIL::SigBit, RTLIL::SigBit > to_sigbit_map(const RTLIL::SigSpec &other) const
Definition: rtlil.cc:2929
RTLIL::SigSig
std::pair< SigSpec, SigSpec > SigSig
Definition: rtlil.h:71
autoidx
YOSYS_NAMESPACE_BEGIN int autoidx
Definition: yosys.cc:51
RTLIL::SigSpec::chunks
const std::vector< RTLIL::SigChunk > & chunks() const
Definition: rtlil.h:1016
RTLIL::Process::root_case
RTLIL_ATTRIBUTE_MEMBERS RTLIL::CaseRule root_case
Definition: rtlil.h:1156
AST_INTERNAL::ProcessGenerator::initSyncSignals
RTLIL::SigSpec initSyncSignals
Definition: genrtlil.cc:175

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Member Function Documentation

void AST_INTERNAL::ProcessGenerator::addChunkActions ( std::vector< RTLIL::SigSig > &  actions,
RTLIL::SigSpec  lvalue,
RTLIL::SigSpec  rvalue,
bool  inSyncRule = false 
)
inline

Definition at line 394 of file genrtlil.cc.

395  {
396  if (inSyncRule && initSyncSignals.size() > 0) {
397  init_lvalue.append(lvalue.extract(initSyncSignals));
398  init_rvalue.append(lvalue.extract(initSyncSignals, &rvalue));
399  lvalue.remove2(initSyncSignals, &rvalue);
400  }
401  log_assert(lvalue.size() == rvalue.size());
402 
403  int offset = 0;
404  for (auto &lvalue_c : lvalue.chunks()) {
405  RTLIL::SigSpec lhs = lvalue_c;
406  RTLIL::SigSpec rhs = rvalue.extract(offset, lvalue_c.width);
407  if (inSyncRule && lvalue_c.wire && lvalue_c.wire->get_bool_attribute("\\nosync"))
408  rhs = RTLIL::SigSpec(RTLIL::State::Sx, rhs.size());
409  remove_unwanted_lvalue_bits(lhs, rhs);
410  actions.push_back(RTLIL::SigSig(lhs, rhs));
411  offset += lhs.size();
412  }
413  }
AST_INTERNAL::ProcessGenerator::init_lvalue
RTLIL::SigSpec init_lvalue
Definition: genrtlil.cc:200
RTLIL::SigSpec::size
int size() const
Definition: rtlil.h:1019
AST_INTERNAL::ProcessGenerator::remove_unwanted_lvalue_bits
void remove_unwanted_lvalue_bits(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs)
Definition: genrtlil.cc:288
log_assert
#define log_assert(_assert_expr_)
Definition: log.h:85
RTLIL::SigSpec::remove2
void remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
Definition: rtlil.cc:2353
AST_INTERNAL::ProcessGenerator::init_rvalue
RTLIL::SigSpec init_rvalue
Definition: genrtlil.cc:200
RTLIL::SigSpec::extract
RTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other=NULL) const
Definition: rtlil.cc:2414
RTLIL::SigSpec::append
void append(const RTLIL::SigSpec &signal)
Definition: rtlil.cc:2523
RTLIL::SigSig
std::pair< SigSpec, SigSpec > SigSig
Definition: rtlil.h:71
RTLIL::SigSpec::chunks
const std::vector< RTLIL::SigChunk > & chunks() const
Definition: rtlil.h:1016
AST_INTERNAL::ProcessGenerator::initSyncSignals
RTLIL::SigSpec initSyncSignals
Definition: genrtlil.cc:175

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void AST_INTERNAL::ProcessGenerator::collect_lvalues ( RTLIL::SigSpec &  reg,
AstNode *  ast,
bool  type_eq,
bool  type_le,
bool  run_sort_and_unify = true 
)
inline

Definition at line 334 of file genrtlil.cc.

335  {
336  switch (ast->type)
337  {
338  case AST_CASE:
339  for (auto child : ast->children)
340  if (child != ast->children[0]) {
341  log_assert(child->type == AST_COND);
342  collect_lvalues(reg, child, type_eq, type_le, false);
343  }
344  break;
345 
346  case AST_COND:
347  case AST_ALWAYS:
348  case AST_INITIAL:
349  for (auto child : ast->children)
350  if (child->type == AST_BLOCK)
351  collect_lvalues(reg, child, type_eq, type_le, false);
352  break;
353 
354  case AST_BLOCK:
355  for (auto child : ast->children) {
356  if (child->type == AST_ASSIGN_EQ && type_eq)
357  reg.append(child->children[0]->genRTLIL());
358  if (child->type == AST_ASSIGN_LE && type_le)
359  reg.append(child->children[0]->genRTLIL());
360  if (child->type == AST_CASE || child->type == AST_BLOCK)
361  collect_lvalues(reg, child, type_eq, type_le, false);
362  }
363  break;
364 
365  default:
366  log_abort();
367  }
368 
369  if (run_sort_and_unify) {
370  std::set<RTLIL::SigBit> sorted_reg;
371  for (auto bit : reg)
372  if (bit.wire)
373  sorted_reg.insert(bit);
374  reg = RTLIL::SigSpec(sorted_reg);
375  }
376  }
log_abort
#define log_abort()
Definition: log.h:84
AST_INTERNAL::ProcessGenerator::collect_lvalues
void collect_lvalues(RTLIL::SigSpec &reg, AstNode *ast, bool type_eq, bool type_le, bool run_sort_and_unify=true)
Definition: genrtlil.cc:334
log_assert
#define log_assert(_assert_expr_)
Definition: log.h:85
AST::AstNode::type
AstNodeType type
Definition: ast.h:146
RTLIL::SigSpec::append
void append(const RTLIL::SigSpec &signal)
Definition: rtlil.cc:2523
AST::AstNode::children
std::vector< AstNode * > children
Definition: ast.h:149

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RTLIL::SigSpec AST_INTERNAL::ProcessGenerator::new_temp_signal ( RTLIL::SigSpec  sig)
inline

Definition at line 305 of file genrtlil.cc.

306  {
307  std::vector<RTLIL::SigChunk> chunks = sig.chunks();
308 
309  for (int i = 0; i < GetSize(chunks); i++)
310  {
311  RTLIL::SigChunk &chunk = chunks[i];
312  if (chunk.wire == NULL)
313  continue;
314 
315  std::string wire_name;
316  do {
317  wire_name = stringf("$%d%s[%d:%d]", new_temp_count[chunk.wire]++,
318  chunk.wire->name.c_str(), chunk.width+chunk.offset-1, chunk.offset);;
319  if (chunk.wire->name.str().find('$') != std::string::npos)
320  wire_name += stringf("$%d", autoidx++);
321  } while (current_module->wires_.count(wire_name) > 0);
322 
323  RTLIL::Wire *wire = current_module->addWire(wire_name, chunk.width);
324  wire->attributes["\\src"] = stringf("%s:%d", always->filename.c_str(), always->linenum);
325 
326  chunk.wire = wire;
327  chunk.offset = 0;
328  }
329 
330  return chunks;
331  }
RTLIL::IdString::c_str
const char * c_str() const
Definition: rtlil.h:178
RTLIL::IdString::str
std::string str() const
Definition: rtlil.h:182
stringf
std::string stringf(const char *fmt,...)
Definition: yosys.cc:58
RTLIL::Module::wires_
std::map< RTLIL::IdString, RTLIL::Wire * > wires_
Definition: rtlil.h:595
AST_INTERNAL::ProcessGenerator::new_temp_count
std::map< RTLIL::Wire *, int > new_temp_count
Definition: genrtlil.cc:197
AST_INTERNAL::ProcessGenerator::always
AstNode * always
Definition: genrtlil.cc:174
RTLIL::SigChunk::wire
RTLIL::Wire * wire
Definition: rtlil.h:885
GetSize
int GetSize(RTLIL::Wire *wire)
Definition: yosys.cc:334
RTLIL::Module::addWire
RTLIL::Wire * addWire(RTLIL::IdString name, int width=1)
Definition: rtlil.cc:1331
RTLIL::Wire::name
RTLIL::IdString name
Definition: rtlil.h:825
NULL
#define NULL
Definition: NumberlikeArray.hh:6
AST::AstNode::filename
std::string filename
Definition: ast.h:175
AST::AstNode::linenum
int linenum
Definition: ast.h:176
AST_INTERNAL::current_module
AstModule * current_module
Definition: ast.cc:62
autoidx
YOSYS_NAMESPACE_BEGIN int autoidx
Definition: yosys.cc:51
RTLIL::SigSpec::chunks
const std::vector< RTLIL::SigChunk > & chunks() const
Definition: rtlil.h:1016

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void AST_INTERNAL::ProcessGenerator::processAst ( AstNode *  ast)
inline

Definition at line 416 of file genrtlil.cc.

417  {
418  switch (ast->type)
419  {
420  case AST_BLOCK:
421  for (auto child : ast->children)
422  processAst(child);
423  break;
424 
425  case AST_ASSIGN_EQ:
426  case AST_ASSIGN_LE:
427  {
428  RTLIL::SigSpec unmapped_lvalue = ast->children[0]->genRTLIL(), lvalue = unmapped_lvalue;
429  RTLIL::SigSpec rvalue = ast->children[1]->genWidthRTLIL(lvalue.size(), &subst_rvalue_map.stdmap());
430  lvalue.replace(subst_lvalue_map.stdmap());
431 
432  if (ast->type == AST_ASSIGN_EQ) {
433  for (int i = 0; i < GetSize(unmapped_lvalue); i++)
434  subst_rvalue_map.set(unmapped_lvalue[i], rvalue[i]);
435  }
436 
437  removeSignalFromCaseTree(lvalue.to_sigbit_set(), current_case);
438  remove_unwanted_lvalue_bits(lvalue, rvalue);
439  current_case->actions.push_back(RTLIL::SigSig(lvalue, rvalue));
440  }
441  break;
442 
443  case AST_CASE:
444  {
445  RTLIL::SwitchRule *sw = new RTLIL::SwitchRule;
446  sw->signal = ast->children[0]->genWidthRTLIL(-1, &subst_rvalue_map.stdmap());
447  current_case->switches.push_back(sw);
448 
449  for (auto &attr : ast->attributes) {
450  if (attr.second->type != AST_CONSTANT)
451  log_error("Attribute `%s' with non-constant value at %s:%d!\n",
452  attr.first.c_str(), ast->filename.c_str(), ast->linenum);
453  sw->attributes[attr.first] = attr.second->asAttrConst();
454  }
455 
456  RTLIL::SigSpec this_case_eq_lvalue;
457  collect_lvalues(this_case_eq_lvalue, ast, true, false);
458 
459  RTLIL::SigSpec this_case_eq_ltemp = new_temp_signal(this_case_eq_lvalue);
460 
461  RTLIL::SigSpec this_case_eq_rvalue = this_case_eq_lvalue;
462  this_case_eq_rvalue.replace(subst_rvalue_map.stdmap());
463 
464  RTLIL::CaseRule *default_case = NULL;
465  RTLIL::CaseRule *last_generated_case = NULL;
466  for (auto child : ast->children)
467  {
468  if (child == ast->children[0])
469  continue;
470  log_assert(child->type == AST_COND);
471 
472  subst_lvalue_map.save();
473  subst_rvalue_map.save();
474 
475  for (int i = 0; i < GetSize(this_case_eq_lvalue); i++)
476  subst_lvalue_map.set(this_case_eq_lvalue[i], this_case_eq_ltemp[i]);
477 
478  RTLIL::CaseRule *backup_case = current_case;
479  current_case = new RTLIL::CaseRule;
480  last_generated_case = current_case;
481  addChunkActions(current_case->actions, this_case_eq_ltemp, this_case_eq_rvalue);
482  for (auto node : child->children) {
483  if (node->type == AST_DEFAULT)
484  default_case = current_case;
485  else if (node->type == AST_BLOCK)
486  processAst(node);
487  else
488  current_case->compare.push_back(node->genWidthRTLIL(sw->signal.size(), &subst_rvalue_map.stdmap()));
489  }
490  if (default_case != current_case)
491  sw->cases.push_back(current_case);
492  else
493  log_assert(current_case->compare.size() == 0);
494  current_case = backup_case;
495 
496  subst_lvalue_map.restore();
497  subst_rvalue_map.restore();
498  }
499 
500  if (last_generated_case != NULL && ast->get_bool_attribute("\\full_case") && default_case == NULL) {
501  last_generated_case->compare.clear();
502  } else {
503  if (default_case == NULL) {
504  default_case = new RTLIL::CaseRule;
505  addChunkActions(default_case->actions, this_case_eq_ltemp, this_case_eq_rvalue);
506  }
507  sw->cases.push_back(default_case);
508  }
509 
510  for (int i = 0; i < GetSize(this_case_eq_lvalue); i++)
511  subst_rvalue_map.set(this_case_eq_lvalue[i], this_case_eq_ltemp[i]);
512 
513  this_case_eq_lvalue.replace(subst_lvalue_map.stdmap());
514  removeSignalFromCaseTree(this_case_eq_lvalue.to_sigbit_set(), current_case);
515  addChunkActions(current_case->actions, this_case_eq_lvalue, this_case_eq_ltemp);
516  }
517  break;
518 
519  case AST_WIRE:
520  log_error("Found wire declaration in block without label at at %s:%d!\n", ast->filename.c_str(), ast->linenum);
521  break;
522 
523  case AST_TCALL:
524  case AST_FOR:
525  break;
526 
527  default:
528  log_abort();
529  }
530  }
AST_INTERNAL::ProcessGenerator::subst_lvalue_map
stackmap< RTLIL::SigBit, RTLIL::SigBit > subst_lvalue_map
Definition: genrtlil.cc:193
AST_INTERNAL::ProcessGenerator::addChunkActions
void addChunkActions(std::vector< RTLIL::SigSig > &actions, RTLIL::SigSpec lvalue, RTLIL::SigSpec rvalue, bool inSyncRule=false)
Definition: genrtlil.cc:394
RTLIL::SigSpec::to_sigbit_set
std::set< RTLIL::SigBit > to_sigbit_set() const
Definition: rtlil.cc:2909
RTLIL::SwitchRule::cases
RTLIL_ATTRIBUTE_MEMBERS std::vector< RTLIL::CaseRule * > cases
Definition: rtlil.h:1134
AST::AstNode::attributes
std::map< RTLIL::IdString, AstNode * > attributes
Definition: ast.h:152
log_error
void log_error(const char *format,...)
Definition: log.cc:204
RTLIL::SigSpec::size
int size() const
Definition: rtlil.h:1019
log_abort
#define log_abort()
Definition: log.h:84
RTLIL::CaseRule::compare
std::vector< RTLIL::SigSpec > compare
Definition: rtlil.h:1119
AST_INTERNAL::ProcessGenerator::remove_unwanted_lvalue_bits
void remove_unwanted_lvalue_bits(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs)
Definition: genrtlil.cc:288
AST::AstNode::get_bool_attribute
bool get_bool_attribute(RTLIL::IdString id)
Definition: ast.cc:166
AST_INTERNAL::ProcessGenerator::collect_lvalues
void collect_lvalues(RTLIL::SigSpec &reg, AstNode *ast, bool type_eq, bool type_le, bool run_sort_and_unify=true)
Definition: genrtlil.cc:334
AST_INTERNAL::ProcessGenerator::current_case
RTLIL::CaseRule * current_case
Definition: genrtlil.cc:180
stackmap::set
void set(const Key &k, const T &v)
Definition: utils.h:63
RTLIL::SwitchRule::signal
RTLIL::SigSpec signal
Definition: rtlil.h:1132
GetSize
int GetSize(RTLIL::Wire *wire)
Definition: yosys.cc:334
log_assert
#define log_assert(_assert_expr_)
Definition: log.h:85
stackmap::restore
void restore()
Definition: utils.h:107
AST_INTERNAL::ProcessGenerator::processAst
void processAst(AstNode *ast)
Definition: genrtlil.cc:416
AST::AstNode::type
AstNodeType type
Definition: ast.h:146
AST_INTERNAL::ProcessGenerator::new_temp_signal
RTLIL::SigSpec new_temp_signal(RTLIL::SigSpec sig)
Definition: genrtlil.cc:305
RTLIL::SigSpec::replace
void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
Definition: rtlil.cc:2297
AST_INTERNAL::ProcessGenerator::subst_rvalue_map
stackmap< RTLIL::SigBit, RTLIL::SigBit > subst_rvalue_map
Definition: genrtlil.cc:187
NULL
#define NULL
Definition: NumberlikeArray.hh:6
AST::AstNode::filename
std::string filename
Definition: ast.h:175
stackmap::save
void save()
Definition: utils.h:102
AST::AstNode::children
std::vector< AstNode * > children
Definition: ast.h:149
AST_INTERNAL::ProcessGenerator::removeSignalFromCaseTree
void removeSignalFromCaseTree(const std::set< RTLIL::SigBit > &pattern, RTLIL::CaseRule *cs)
Definition: genrtlil.cc:382
RTLIL::CaseRule::actions
std::vector< RTLIL::SigSig > actions
Definition: rtlil.h:1120
AST::AstNode::linenum
int linenum
Definition: ast.h:176
RTLIL::CaseRule::switches
std::vector< RTLIL::SwitchRule * > switches
Definition: rtlil.h:1121
RTLIL::SigSig
std::pair< SigSpec, SigSpec > SigSig
Definition: rtlil.h:71
stackmap::stdmap
const std::map< Key, T, Compare > & stdmap()
Definition: utils.h:97

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void AST_INTERNAL::ProcessGenerator::remove_unwanted_lvalue_bits ( RTLIL::SigSpec &  lhs,
RTLIL::SigSpec &  rhs 
)
inline

Definition at line 288 of file genrtlil.cc.

289  {
290  RTLIL::SigSpec new_lhs, new_rhs;
291 
292  log_assert(GetSize(lhs) == GetSize(rhs));
293  for (int i = 0; i < GetSize(lhs); i++) {
294  if (lhs[i].wire == nullptr)
295  continue;
296  new_lhs.append(lhs[i]);
297  new_rhs.append(rhs[i]);
298  }
299 
300  lhs = new_lhs;
301  rhs = new_rhs;
302  }
GetSize
int GetSize(RTLIL::Wire *wire)
Definition: yosys.cc:334
log_assert
#define log_assert(_assert_expr_)
Definition: log.h:85
RTLIL::SigSpec::append
void append(const RTLIL::SigSpec &signal)
Definition: rtlil.cc:2523

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void AST_INTERNAL::ProcessGenerator::removeSignalFromCaseTree ( const std::set< RTLIL::SigBit > &  pattern,
RTLIL::CaseRule *  cs 
)
inline

Definition at line 382 of file genrtlil.cc.

383  {
384  for (auto it = cs->actions.begin(); it != cs->actions.end(); it++)
385  it->first.remove2(pattern, &it->second);
386 
387  for (auto it = cs->switches.begin(); it != cs->switches.end(); it++)
388  for (auto it2 = (*it)->cases.begin(); it2 != (*it)->cases.end(); it2++)
389  removeSignalFromCaseTree(pattern, *it2);
390  }
AST_INTERNAL::ProcessGenerator::removeSignalFromCaseTree
void removeSignalFromCaseTree(const std::set< RTLIL::SigBit > &pattern, RTLIL::CaseRule *cs)
Definition: genrtlil.cc:382
RTLIL::CaseRule::actions
std::vector< RTLIL::SigSig > actions
Definition: rtlil.h:1120
RTLIL::CaseRule::switches
std::vector< RTLIL::SwitchRule * > switches
Definition: rtlil.h:1121

Field Documentation

AstNode* AST_INTERNAL::ProcessGenerator::always

Definition at line 174 of file genrtlil.cc.

RTLIL::CaseRule* AST_INTERNAL::ProcessGenerator::current_case

Definition at line 180 of file genrtlil.cc.

RTLIL::SigSpec AST_INTERNAL::ProcessGenerator::init_lvalue

Definition at line 200 of file genrtlil.cc.

RTLIL::SigSpec AST_INTERNAL::ProcessGenerator::init_rvalue

Definition at line 200 of file genrtlil.cc.

RTLIL::SigSpec AST_INTERNAL::ProcessGenerator::initSyncSignals

Definition at line 175 of file genrtlil.cc.

std::map<RTLIL::Wire*, int> AST_INTERNAL::ProcessGenerator::new_temp_count

Definition at line 197 of file genrtlil.cc.

RTLIL::SigSpec AST_INTERNAL::ProcessGenerator::outputSignals

Definition at line 177 of file genrtlil.cc.

RTLIL::Process* AST_INTERNAL::ProcessGenerator::proc

Definition at line 176 of file genrtlil.cc.

stackmap<RTLIL::SigBit, RTLIL::SigBit> AST_INTERNAL::ProcessGenerator::subst_lvalue_map

Definition at line 193 of file genrtlil.cc.

stackmap<RTLIL::SigBit, RTLIL::SigBit> AST_INTERNAL::ProcessGenerator::subst_rvalue_map

Definition at line 187 of file genrtlil.cc.

The documentation for this struct was generated from the following file: