SplitnetsWorker Struct Reference

Public Member Functions
void	append_wire (RTLIL::Module *module, RTLIL::Wire *wire, int offset, int width, std::string format)
void	operator() (RTLIL::SigSpec &sig)

Data Fields
std::map< RTLIL::Wire *, std::vector< RTLIL::SigBit > >	splitmap

Detailed Description

Definition at line 28 of file splitnets.cc.

Member Function Documentation

void SplitnetsWorker::append_wire ( RTLIL::Module *  module, RTLIL::Wire *  wire, int  offset, int  width, std::string  format  )

inline

Definition at line 32 of file splitnets.cc.

    {
        std::string new_wire_name = wire->name.str();

        if (format.size() > 0)
            new_wire_name += format.substr(0, 1);

        if (width > 1) {
            new_wire_name += stringf("%d", offset+width-1);
            if (format.size() > 2)
                new_wire_name += format.substr(2, 1);
            else
                new_wire_name += ":";
        }

        new_wire_name += stringf("%d", offset);

        if (format.size() > 1)
            new_wire_name += format.substr(1, 1);

        RTLIL::Wire *new_wire = module->addWire(module->uniquify(new_wire_name), width);
        new_wire->port_id = wire->port_id;
        new_wire->port_input = wire->port_input;
        new_wire->port_output = wire->port_output;

        std::vector<RTLIL::SigBit> sigvec = RTLIL::SigSpec(new_wire).to_sigbit_vector();
        splitmap[wire].insert(splitmap[wire].end(), sigvec.begin(), sigvec.end());
    }

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void SplitnetsWorker::operator() ( RTLIL::SigSpec &  sig )

inline

Definition at line 61 of file splitnets.cc.

    {
        for (auto &bit : sig)
            if (splitmap.count(bit.wire) > 0)
                bit = splitmap.at(bit.wire).at(bit.offset);
    }

Field Documentation

std::map<RTLIL::Wire*, std::vector<RTLIL::SigBit> > SplitnetsWorker::splitmap

Definition at line 30 of file splitnets.cc.

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The documentation for this struct was generated from the following file:

• splitnets.cc