166 log_header(
"Executing OPT_RMDFF pass (remove dff with constant values).\n");
170 for (
auto &mod_it : design->
modules_)
172 if (!design->
selected(mod_it.second))
177 for (
auto &it : mod_it.second->wires_)
178 if (it.second->attributes.count(
"\\init") != 0)
182 std::vector<RTLIL::IdString> dff_list;
183 for (
auto &it : mod_it.second->cells_) {
184 if (it.second->type ==
"$mux" || it.second->type ==
"$pmux") {
185 if (it.second->getPort(
"\\A").size() == it.second->getPort(
"\\B").size())
189 if (!design->
selected(mod_it.second, it.second))
191 if (it.second->type ==
"$_DFF_N_") dff_list.push_back(it.first);
192 if (it.second->type ==
"$_DFF_P_") dff_list.push_back(it.first);
193 if (it.second->type ==
"$_DFF_NN0_") dff_list.push_back(it.first);
194 if (it.second->type ==
"$_DFF_NN1_") dff_list.push_back(it.first);
195 if (it.second->type ==
"$_DFF_NP0_") dff_list.push_back(it.first);
196 if (it.second->type ==
"$_DFF_NP1_") dff_list.push_back(it.first);
197 if (it.second->type ==
"$_DFF_PN0_") dff_list.push_back(it.first);
198 if (it.second->type ==
"$_DFF_PN1_") dff_list.push_back(it.first);
199 if (it.second->type ==
"$_DFF_PP0_") dff_list.push_back(it.first);
200 if (it.second->type ==
"$_DFF_PP1_") dff_list.push_back(it.first);
201 if (it.second->type ==
"$dff") dff_list.push_back(it.first);
202 if (it.second->type ==
"$adff") dff_list.push_back(it.first);
205 for (
auto &
id : dff_list) {
206 if (mod_it.second->cells_.count(
id) > 0 &&
207 handle_dff(mod_it.second, mod_it.second->cells_[
id]))
217 log(
"Replaced %d DFF cells.\n", total_count);
bool selected(T1 *module) const
void log_header(const char *format,...)
void set(RTLIL::Module *module)
USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN SigMap dff_init_map
std::map< RTLIL::IdString, RTLIL::Module * > modules_
bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
SigSet< RTLIL::Cell * > mux_drivers
void log(const char *format,...)
void scratchpad_set_bool(std::string varname, bool value)
void add(RTLIL::SigSpec from, RTLIL::SigSpec to)
void extra_args(std::vector< std::string > args, size_t argidx, RTLIL::Design *design, bool select=true)
void insert(RTLIL::SigSpec sig, T data)
USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN SigMap assign_map