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Public Member Functions | Data Fields
statdata_t Struct Reference

Public Member Functions

statdata_t operator+ (const statdata_t &other) const
 
statdata_t operator* (int other) const
 
 statdata_t ()
 
 statdata_t (RTLIL::Design *design, RTLIL::Module *mod, bool width_mode)
 
void log_data ()
 

Data Fields

STAT_INT_MEMBERS std::map
< RTLIL::IdString, int,
RTLIL::sort_by_id_str > 		num_cells_by_type
 

Detailed Description

Definition at line 27 of file stat.cc.

Constructor & Destructor Documentation

statdata_t::statdata_t ( )
inline

Definition at line 60 of file stat.cc.

61  {
62  #define X(_name) _name = 0;
63  STAT_INT_MEMBERS
64  #undef X
65  }
STAT_INT_MEMBERS
#define STAT_INT_MEMBERS
Definition: stat.cc:29
statdata_t::statdata_t ( RTLIL::Design *  design,
RTLIL::Module *  mod,
bool  width_mode 
)
inline

Definition at line 67 of file stat.cc.

68  {
69  #define X(_name) _name = 0;
70  STAT_INT_MEMBERS
71  #undef X
72 
73  for (auto &it : mod->wires_)
74  {
75  if (!design->selected(mod, it.second))
76  continue;
77 
78  if (it.first[0] == '\\') {
79  num_pub_wires++;
80  num_pub_wire_bits += it.second->width;
81  }
82 
83  num_wires++;
84  num_wire_bits += it.second->width;
85  }
86 
87  for (auto &it : mod->memories) {
88  if (!design->selected(mod, it.second))
89  continue;
90  num_memories++;
91  num_memory_bits += it.second->width * it.second->size;
92  }
93 
94  for (auto &it : mod->cells_)
95  {
96  if (!design->selected(mod, it.second))
97  continue;
98 
99  RTLIL::IdString cell_type = it.second->type;
100 
101  if (width_mode)
102  {
103  if (cell_type.in("$not", "$pos", "$neg",
104  "$logic_not", "$logic_and", "$logic_or",
105  "$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool",
106  "$lut", "$and", "$or", "$xor", "$xnor",
107  "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx",
108  "$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt",
109  "$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
110  int width_a = it.second->hasPort("\\A") ? GetSize(it.second->getPort("\\A")) : 0;
111  int width_b = it.second->hasPort("\\B") ? GetSize(it.second->getPort("\\B")) : 0;
112  int width_y = it.second->hasPort("\\Y") ? GetSize(it.second->getPort("\\Y")) : 0;
113  cell_type = stringf("%s_%d", cell_type.c_str(), std::max<int>({width_a, width_b, width_y}));
114  }
115  else if (cell_type.in("$mux", "$pmux"))
116  cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(it.second->getPort("\\Y")));
117  else if (cell_type.in("$sr", "$dff", "$dffsr", "$adff", "$dlatch", "$dlatchsr"))
118  cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(it.second->getPort("\\Q")));
119  }
120 
121  num_cells++;
122  num_cells_by_type[cell_type]++;
123  }
124 
125  for (auto &it : mod->processes) {
126  if (!design->selected(mod, it.second))
127  continue;
128  num_processes++;
129  }
130  }
RTLIL::IdString::c_str
const char * c_str() const
Definition: rtlil.h:178
RTLIL::Design::selected
bool selected(T1 *module) const
Definition: rtlil.h:551
stringf
std::string stringf(const char *fmt,...)
Definition: yosys.cc:58
RTLIL::Module::wires_
std::map< RTLIL::IdString, RTLIL::Wire * > wires_
Definition: rtlil.h:595
RTLIL::Module::memories
std::map< RTLIL::IdString, RTLIL::Memory * > memories
Definition: rtlil.h:601
RTLIL::IdString::in
bool in(T first, Args...rest)
Definition: rtlil.h:241
GetSize
int GetSize(RTLIL::Wire *wire)
Definition: yosys.cc:334
statdata_t::num_cells_by_type
STAT_INT_MEMBERS std::map< RTLIL::IdString, int, RTLIL::sort_by_id_str > num_cells_by_type
Definition: stat.cc:36
RTLIL::Module::processes
std::map< RTLIL::IdString, RTLIL::Process * > processes
Definition: rtlil.h:602
RTLIL::Module::cells_
std::map< RTLIL::IdString, RTLIL::Cell * > cells_
Definition: rtlil.h:596
STAT_INT_MEMBERS
#define STAT_INT_MEMBERS
Definition: stat.cc:29

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Member Function Documentation

void statdata_t::log_data ( )
inline

Definition at line 132 of file stat.cc.

133  {
134  log(" Number of wires: %6d\n", num_wires);
135  log(" Number of wire bits: %6d\n", num_wire_bits);
136  log(" Number of public wires: %6d\n", num_pub_wires);
137  log(" Number of public wire bits: %6d\n", num_pub_wire_bits);
138  log(" Number of memories: %6d\n", num_memories);
139  log(" Number of memory bits: %6d\n", num_memory_bits);
140  log(" Number of processes: %6d\n", num_processes);
141  log(" Number of cells: %6d\n", num_cells);
142  for (auto &it : num_cells_by_type)
143  log(" %-26s %6d\n", RTLIL::id2cstr(it.first), it.second);
144  }
statdata_t::num_cells_by_type
STAT_INT_MEMBERS std::map< RTLIL::IdString, int, RTLIL::sort_by_id_str > num_cells_by_type
Definition: stat.cc:36
RTLIL::id2cstr
static const char * id2cstr(const RTLIL::IdString &str)
Definition: rtlil.h:267
log
void log(const char *format,...)
Definition: log.cc:180

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statdata_t statdata_t::operator* ( int  other) const
inline

Definition at line 49 of file stat.cc.

50  {
51  statdata_t sum = *this;
52  #define X(_name) sum._name *= other;
53  STAT_INT_MEMBERS
54  #undef X
55  for (auto &it : sum.num_cells_by_type)
56  it.second *= other;
57  return sum;
58  }
statdata_t
Definition: stat.cc:27
statdata_t::num_cells_by_type
STAT_INT_MEMBERS std::map< RTLIL::IdString, int, RTLIL::sort_by_id_str > num_cells_by_type
Definition: stat.cc:36
STAT_INT_MEMBERS
#define STAT_INT_MEMBERS
Definition: stat.cc:29
statdata_t statdata_t::operator+ ( const statdata_t &  other) const
inline

Definition at line 38 of file stat.cc.

39  {
40  statdata_t sum = other;
41  #define X(_name) sum._name += _name;
42  STAT_INT_MEMBERS
43  #undef X
44  for (auto &it : num_cells_by_type)
45  sum.num_cells_by_type[it.first] += it.second;
46  return sum;
47  }
statdata_t
Definition: stat.cc:27
statdata_t::num_cells_by_type
STAT_INT_MEMBERS std::map< RTLIL::IdString, int, RTLIL::sort_by_id_str > num_cells_by_type
Definition: stat.cc:36
STAT_INT_MEMBERS
#define STAT_INT_MEMBERS
Definition: stat.cc:29

Field Documentation

STAT_INT_MEMBERS std::map<RTLIL::IdString, int, RTLIL::sort_by_id_str> statdata_t::num_cells_by_type

Definition at line 36 of file stat.cc.

The documentation for this struct was generated from the following file: