Collaboration diagram for OptShareWorker:

Data Structures
struct	CompareCells

Public Member Functions
std::string	int_to_hash_string (unsigned int v)

std::string	hash_cell_parameters_and_connections (const RTLIL::Cell *cell)

bool	compare_cell_parameters_and_connections (const RTLIL::Cell cell1, const RTLIL::Cell cell2, bool &lt)

bool	compare_cells (const RTLIL::Cell cell1, const RTLIL::Cell cell2)

	OptShareWorker (RTLIL::Design design, RTLIL::Module module, bool mode_nomux)

Data Fields
RTLIL::Design *	design

RTLIL::Module *	module

SigMap	assign_map

SigMap	dff_init_map

CellTypes	ct

int	total_count

std::map< const RTLIL::Cell *, std::string >	cell_hash_cache

Detailed Description

Definition at line 34 of file opt_share.cc.

Constructor & Destructor Documentation

OptShareWorker::OptShareWorker	(	RTLIL::Design *	design,
		RTLIL::Module *	module,
		bool	mode_nomux
	)

inline

Definition at line 217 of file opt_share.cc.

                                                                               :
         design(design), module(module), assign_map(module)
     {
         total_count = 0;
         ct.setup_internals();
         ct.setup_internals_mem();
         ct.setup_stdcells();
         ct.setup_stdcells_mem();
 
         if (mode_nomux) {
             ct.cell_types.erase("$mux");
             ct.cell_types.erase("$pmux");
         }
 
         log("Finding identical cells in module `%s'.\n", module->name.c_str());
         assign_map.set(module);
 
         dff_init_map.set(module);
         for (auto &it : module->wires_)
             if (it.second->attributes.count("\\init") != 0)
                 dff_init_map.add(it.second, it.second->attributes.at("\\init"));
 
         bool did_something = true;
         while (did_something)
         {
 #ifdef USE_CELL_HASH_CACHE
             cell_hash_cache.clear();
 #endif
             std::vector<RTLIL::Cell*> cells;
             cells.reserve(module->cells_.size());
             for (auto &it : module->cells_) {
                 if (ct.cell_known(it.second->type) && design->selected(module, it.second))
                     cells.push_back(it.second);
             }
 
             did_something = false;
             std::map<RTLIL::Cell*, RTLIL::Cell*, CompareCells> sharemap(CompareCells(this));
             for (auto cell : cells)
             {
                 if (sharemap.count(cell) > 0) {
                     did_something = true;
                     log("  Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), sharemap[cell]->name.c_str());
                     for (auto &it : cell->connections()) {
                         if (ct.cell_output(cell->type, it.first)) {
                             RTLIL::SigSpec other_sig = sharemap[cell]->getPort(it.first);
                             log("    Redirecting output %s: %s = %s\n", it.first.c_str(),
                                     log_signal(it.second), log_signal(other_sig));
                             module->connect(RTLIL::SigSig(it.second, other_sig));
                             assign_map.add(it.second, other_sig);
                         }
                     }
                     log("    Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str());
                     module->remove(cell);
                     total_count++;
                 } else {
                     sharemap[cell] = cell;
                 }
             }
         }
     }

Here is the call graph for this function:

Member Function Documentation

bool OptShareWorker::compare_cell_parameters_and_connections	(	const RTLIL::Cell *	cell1,
		const RTLIL::Cell *	cell2,
		bool &	lt
	)

inline

Definition at line 117 of file opt_share.cc.

     {
 #ifdef USE_CELL_HASH_CACHE
         std::string hash1 = hash_cell_parameters_and_connections(cell1);
         std::string hash2 = hash_cell_parameters_and_connections(cell2);
 
         if (hash1 != hash2) {
             lt = hash1 < hash2;
             return true;
         }
 #endif
 
         if (cell1->parameters != cell2->parameters) {
             lt = cell1->parameters < cell2->parameters;
             return true;
         }
 
         std::map<RTLIL::IdString, RTLIL::SigSpec> conn1 = cell1->connections();
         std::map<RTLIL::IdString, RTLIL::SigSpec> conn2 = cell2->connections();
 
         for (auto &it : conn1) {
             if (ct.cell_output(cell1->type, it.first))
                 it.second = RTLIL::SigSpec();
             else
                 assign_map.apply(it.second);
         }
 
         for (auto &it : conn2) {
             if (ct.cell_output(cell2->type, it.first))
                 it.second = RTLIL::SigSpec();
             else
                 assign_map.apply(it.second);
         }
 
         if (cell1->type == "$and" || cell1->type == "$or" || cell1->type == "$xor" || cell1->type == "$xnor" || cell1->type == "$add" || cell1->type == "$mul" ||
                 cell1->type == "$logic_and" || cell1->type == "$logic_or" || cell1->type == "$_AND_" || cell1->type == "$_OR_" || cell1->type == "$_XOR_") {
             if (conn1.at("\\A") < conn1.at("\\B")) {
                 RTLIL::SigSpec tmp = conn1["\\A"];
                 conn1["\\A"] = conn1["\\B"];
                 conn1["\\B"] = tmp;
             }
             if (conn2.at("\\A") < conn2.at("\\B")) {
                 RTLIL::SigSpec tmp = conn2["\\A"];
                 conn2["\\A"] = conn2["\\B"];
                 conn2["\\B"] = tmp;
             }
         } else
         if (cell1->type == "$reduce_xor" || cell1->type == "$reduce_xnor") {
             conn1["\\A"].sort();
             conn2["\\A"].sort();
         } else
         if (cell1->type == "$reduce_and" || cell1->type == "$reduce_or" || cell1->type == "$reduce_bool") {
             conn1["\\A"].sort_and_unify();
             conn2["\\A"].sort_and_unify();
         }
 
         if (conn1 != conn2) {
             lt = conn1 < conn2;
             return true;
         }
 
         if (cell1->type.substr(0, 1) == "$" && conn1.count("\\Q") != 0) {
             std::vector<RTLIL::SigBit> q1 = dff_init_map(cell1->getPort("\\Q")).to_sigbit_vector();
             std::vector<RTLIL::SigBit> q2 = dff_init_map(cell2->getPort("\\Q")).to_sigbit_vector();
             for (size_t i = 0; i < q1.size(); i++)
                 if ((q1.at(i).wire == NULL || q2.at(i).wire == NULL) && q1.at(i) != q2.at(i)) {
                     lt = q1.at(i) < q2.at(i);
                     return true;
                 }
         }
 
         return false;
     }

Here is the call graph for this function:

Here is the caller graph for this function:

bool OptShareWorker::compare_cells	(	const RTLIL::Cell *	cell1,
		const RTLIL::Cell *	cell2
	)

inline

Definition at line 191 of file opt_share.cc.

     {
         if (cell1->type != cell2->type)
             return cell1->type < cell2->type;
 
         if (!ct.cell_known(cell1->type))
             return cell1 < cell2;
 
         if (cell1->has_keep_attr() || cell2->has_keep_attr())
             return cell1 < cell2;
 
         bool lt;
         if (compare_cell_parameters_and_connections(cell1, cell2, lt))
             return lt;
 
         return false;
     }

Here is the call graph for this function:

Here is the caller graph for this function:

std::string OptShareWorker::hash_cell_parameters_and_connections ( const RTLIL::Cell * cell )

inline

Definition at line 60 of file opt_share.cc.

     {
         if (cell_hash_cache.count(cell) > 0)
             return cell_hash_cache[cell];
 
         std::string hash_string = cell->type.str() + "\n";
 
         for (auto &it : cell->parameters)
             hash_string += "P " + it.first.str() + "=" + it.second.as_string() + "\n";
 
         const std::map<RTLIL::IdString, RTLIL::SigSpec> *conn = &cell->connections();
         std::map<RTLIL::IdString, RTLIL::SigSpec> alt_conn;
 
         if (cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor" || cell->type == "$add" || cell->type == "$mul" ||
                 cell->type == "$logic_and" || cell->type == "$logic_or" || cell->type == "$_AND_" || cell->type == "$_OR_" || cell->type == "$_XOR_") {
             alt_conn = *conn;
             if (assign_map(alt_conn.at("\\A")) < assign_map(alt_conn.at("\\B"))) {
                 alt_conn["\\A"] = conn->at("\\B");
                 alt_conn["\\B"] = conn->at("\\A");
             }
             conn = &alt_conn;
         } else
         if (cell->type == "$reduce_xor" || cell->type == "$reduce_xnor") {
             alt_conn = *conn;
             assign_map.apply(alt_conn.at("\\A"));
             alt_conn.at("\\A").sort();
             conn = &alt_conn;
         } else
         if (cell->type == "$reduce_and" || cell->type == "$reduce_or" || cell->type == "$reduce_bool") {
             alt_conn = *conn;
             assign_map.apply(alt_conn.at("\\A"));
             alt_conn.at("\\A").sort_and_unify();
             conn = &alt_conn;
         }
 
         for (auto &it : *conn) {
             if (ct.cell_output(cell->type, it.first))
                 continue;
             RTLIL::SigSpec sig = it.second;
             assign_map.apply(sig);
             hash_string += "C " + it.first.str() + "=";
             for (auto &chunk : sig.chunks()) {
                 if (chunk.wire)
                     hash_string += "{" + chunk.wire->name.str() + " " +
                             int_to_hash_string(chunk.offset) + " " +
                             int_to_hash_string(chunk.width) + "}";
                 else
                     hash_string += RTLIL::Const(chunk.data).as_string();
             }
             hash_string += "\n";
         }
 
         cell_hash_cache[cell] = sha1(hash_string);
         return cell_hash_cache[cell];
     }

Here is the call graph for this function:

Here is the caller graph for this function:

std::string OptShareWorker::int_to_hash_string ( unsigned int v )

inline

Definition at line 48 of file opt_share.cc.

     {
         if (v == 0)
             return "0";
         std::string str = "";
         while (v > 0) {
             str += 'a' + (v & 15);
             v = v >> 4;
         }
         return str;
     }

Here is the caller graph for this function:

Field Documentation

SigMap OptShareWorker::assign_map

Definition at line 38 of file opt_share.cc.

std::map<const RTLIL::Cell*, std::string> OptShareWorker::cell_hash_cache

Definition at line 44 of file opt_share.cc.

CellTypes OptShareWorker::ct

Definition at line 41 of file opt_share.cc.

RTLIL::Design* OptShareWorker::design

Definition at line 36 of file opt_share.cc.

SigMap OptShareWorker::dff_init_map

Definition at line 39 of file opt_share.cc.

RTLIL::Module* OptShareWorker::module

Definition at line 37 of file opt_share.cc.

int OptShareWorker::total_count

Definition at line 42 of file opt_share.cc.

The documentation for this struct was generated from the following file:

opt_share.cc

Data Structures

Public Member Functions

Data Fields

Detailed Description

Constructor & Destructor Documentation

Member Function Documentation

Field Documentation