Here is a list of all struct and union fields with links to the structures/unions they belong to:

- r -

• ra : Minisat::ClauseAllocator
• random_seed : Minisat::Solver
• random_var_freq : Minisat::Solver
• range : Minisat::DoubleOption , Minisat::Int64Option , Minisat::IntOption
• range_left : AST::AstNode
• range_right : AST::AstNode
• range_swapped : AST::AstNode
• range_valid : AST::AstNode
• read() : SHA1
• readmem() : AST::AstNode
• realAsConst() : AST::AstNode
• realvalue : AST::AstNode
• reason() : Minisat::Solver , Minisat::Solver::VarData
• rebuildOrderHeap() : Minisat::Solver
• recursion_state : ShareWorker
• recursive_mode : TechmapWorker
• ReduceAnd() : RTLIL::Module
• ReduceBool() : RTLIL::Module
• reduceDB() : Minisat::Solver
• reduceDB_lt() : reduceDB_lt
• ReduceOr() : RTLIL::Module
• ReduceXnor() : RTLIL::Module
• ReduceXor() : RTLIL::Module
• Ref : Minisat::RegionAllocator< T >
• Ref_Undef : Minisat::RegionAllocator< T >
• refcount_cells_ : RTLIL::Module
• refcount_modules_ : RTLIL::Design
• refcount_p : RTLIL::ObjIterator< T > , RTLIL::ObjRange< T >
• refcount_wires_ : RTLIL::Module
• RegionAllocator() : Minisat::RegionAllocator< T >
• register_bit() : SigMap
• register_cone() : FindReducedInputs
• register_cone_worker() : FindReducedInputs , PerformReduction
• register_pi_bit() : FindReducedInputs
• rehash() : Minisat::Map< K, D, H, E >
• rel : Minisat::Clause
• released_vars : Minisat::Solver
• releaseVar() : Minisat::SimpSolver , Minisat::Solver
• reload_module() : ModIndex
• reloc() : Minisat::ClauseAllocator
• relocAll() : Minisat::SimpSolver , Minisat::Solver
• relocate() : Minisat::Clause
• relocation() : Minisat::Clause
• reloced : Minisat::Clause
• remove() : Minisat::CMap< T > , Minisat::Heap< K, Comp, MkIndex > , Minisat::Map< K, D, H, E > , RTLIL::Design , RTLIL::Module , RTLIL::SigSpec , SigPool
• remove2() : RTLIL::SigSpec
• remove_const() : RTLIL::SigSpec
• remove_satisfied : Minisat::Solver
• remove_unwanted_lvalue_bits() : AST_INTERNAL::ProcessGenerator
• removeClause() : Minisat::SimpSolver , Minisat::Solver
• removed_count : OptMuxtreeWorker
• removeMin() : Minisat::Heap< K, Comp, MkIndex >
• removeSatisfied() : Minisat::Solver
• removeSignalFromCaseTree() : AST_INTERNAL::ProcessGenerator
• rename() : RTLIL::Module
• RenamePass() : RenamePass
• repeat() : RTLIL::SigSpec
• replace() : RTLIL::SigSpec
• replace_alu() : AlumaccWorker
• replace_ids() : AST::AstNode
• replace_macc() : AlumaccWorker
• replace_variables() : AST::AstNode
• reserve() : Minisat::IntMap< K, V, MkIndex >
• reset() : PerformanceTimer , SHA1 , stackmap< Key, T, Compare >
• reset_state : FsmData
• restart_first : Minisat::Solver
• restart_inc : Minisat::Solver
• restore() : stackmap< Key, T, Compare >
• rewrite_sigspecs() : RTLIL::CaseRule , RTLIL::Cell , RTLIL::Module , RTLIL::Process , RTLIL::SwitchRule , RTLIL::SyncRule
• right() : Minisat::Heap< K, Comp, MkIndex >
• rnd_decisions : Minisat::Solver
• rnd_init_act : Minisat::Solver
• rnd_pol : Minisat::Solver
• root_case : RTLIL::Process
• rotate_x() : blockgeom_t
• rotate_y() : blockgeom_t
• rotate_z() : blockgeom_t
• RTLIL::Module : RTLIL::Cell , RTLIL::Wire
• run() : AlumaccWorker , Dff2dffeWorker , FreduceWorker , SccWorker , SpliceWorker , VlogHammerReporter , WreduceWorker
• run_cell() : WreduceWorker
• run_cell_mux() : WreduceWorker
• run_checker() : BruteForceEquivChecker
• run_reduce_inport() : WreduceWorker
• run_register() : Backend , Frontend , Pass
• runtime_ns : Pass