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Dff2dffeWorker Struct Reference
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Public Types

typedef std::pair< RTLIL::Cell
*, int > 		cell_int_t
 
typedef std::map
< RTLIL::SigBit, bool > 		pattern_t
 
typedef std::set< pattern_t > patterns_t
 

Public Member Functions

 Dff2dffeWorker (RTLIL::Module *module)
 
patterns_t find_muxtree_feedback_patterns (RTLIL::SigBit d, RTLIL::SigBit q, pattern_t path)
 
void simplify_patterns (patterns_t &)
 
RTLIL::SigSpec make_patterns_logic (patterns_t patterns)
 
void handle_dff_cell (RTLIL::Cell *dff_cell)
 
void run ()
 

Data Fields

RTLIL::Module * module
 
SigMap sigmap
 
CellTypes ct
 
std::map< RTLIL::SigBit,
cell_int_t > 		bit2mux
 
std::vector< RTLIL::Cell * > dff_cells
 
std::map< RTLIL::SigBit, int > bitusers
 

Detailed Description

Definition at line 27 of file dff2dffe.cc.

Member Typedef Documentation

typedef std::pair<RTLIL::Cell*, int> Dff2dffeWorker::cell_int_t

Definition at line 33 of file dff2dffe.cc.

typedef std::map<RTLIL::SigBit, bool> Dff2dffeWorker::pattern_t

Definition at line 38 of file dff2dffe.cc.

typedef std::set<pattern_t> Dff2dffeWorker::patterns_t

Definition at line 39 of file dff2dffe.cc.

Constructor & Destructor Documentation

Dff2dffeWorker::Dff2dffeWorker ( RTLIL::Module *  module)
inline

Definition at line 41 of file dff2dffe.cc.

41  : module(module), sigmap(module), ct(module->design)
42  {
43  for (auto wire : module->wires()) {
44  if (wire->port_output)
45  for (auto bit : sigmap(wire))
46  bitusers[bit]++;
47  }
48 
49  for (auto cell : module->cells()) {
50  if (cell->type == "$mux" || cell->type == "$pmux") {
51  RTLIL::SigSpec sig_y = sigmap(cell->getPort("\\Y"));
52  for (int i = 0; i < GetSize(sig_y); i++)
53  bit2mux[sig_y[i]] = cell_int_t(cell, i);
54  }
55  if (cell->type == "$dff")
56  dff_cells.push_back(cell);
57  for (auto conn : cell->connections()) {
58  if (ct.cell_output(cell->type, conn.first))
59  continue;
60  for (auto bit : sigmap(conn.second))
61  bitusers[bit]++;
62  }
63  }
64  }
Dff2dffeWorker::bitusers
std::map< RTLIL::SigBit, int > bitusers
Definition: dff2dffe.cc:36
Dff2dffeWorker::ct
CellTypes ct
Definition: dff2dffe.cc:31
RTLIL::Module::wires
RTLIL::ObjRange< RTLIL::Wire * > wires()
Definition: rtlil.h:640
Dff2dffeWorker::dff_cells
std::vector< RTLIL::Cell * > dff_cells
Definition: dff2dffe.cc:35
CellTypes::cell_output
bool cell_output(RTLIL::IdString type, RTLIL::IdString port)
Definition: celltypes.h:193
GetSize
int GetSize(RTLIL::Wire *wire)
Definition: yosys.cc:334
Dff2dffeWorker::bit2mux
std::map< RTLIL::SigBit, cell_int_t > bit2mux
Definition: dff2dffe.cc:34
RTLIL::Module::cells
RTLIL::ObjRange< RTLIL::Cell * > cells()
Definition: rtlil.h:641
Dff2dffeWorker::cell_int_t
std::pair< RTLIL::Cell *, int > cell_int_t
Definition: dff2dffe.cc:33
Dff2dffeWorker::sigmap
SigMap sigmap
Definition: dff2dffe.cc:30
Dff2dffeWorker::module
RTLIL::Module * module
Definition: dff2dffe.cc:29
RTLIL::Module::design
RTLIL::Design * design
Definition: rtlil.h:589

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Member Function Documentation

patterns_t Dff2dffeWorker::find_muxtree_feedback_patterns ( RTLIL::SigBit  d,
RTLIL::SigBit  q,
pattern_t  path 
)
inline

Definition at line 66 of file dff2dffe.cc.

67  {
68  patterns_t ret;
69 
70  if (d == q) {
71  ret.insert(path);
72  return ret;
73  }
74 
75  if (bit2mux.count(d) == 0 || bitusers[d] > 1)
76  return ret;
77 
78  cell_int_t mux_cell_int = bit2mux.at(d);
79  RTLIL::SigSpec sig_a = sigmap(mux_cell_int.first->getPort("\\A"));
80  RTLIL::SigSpec sig_b = sigmap(mux_cell_int.first->getPort("\\B"));
81  RTLIL::SigSpec sig_s = sigmap(mux_cell_int.first->getPort("\\S"));
82  int width = GetSize(sig_a), index = mux_cell_int.second;
83 
84  for (int i = 0; i < GetSize(sig_s); i++)
85  if (path.count(sig_s[i]) && path.at(sig_s[i]))
86  {
87  ret = find_muxtree_feedback_patterns(sig_b[i*width + index], q, path);
88 
89  if (sig_b[i*width + index] == q) {
90  RTLIL::SigSpec s = mux_cell_int.first->getPort("\\B");
91  s[i*width + index] = RTLIL::Sx;
92  mux_cell_int.first->setPort("\\B", s);
93  }
94 
95  return ret;
96  }
97 
98  pattern_t path_else = path;
99 
100  for (int i = 0; i < GetSize(sig_s); i++)
101  {
102  if (path.count(sig_s[i]))
103  continue;
104 
105  pattern_t path_this = path;
106  path_else[sig_s[i]] = false;
107  path_this[sig_s[i]] = true;
108 
109  for (auto &pat : find_muxtree_feedback_patterns(sig_b[i*width + index], q, path_this))
110  ret.insert(pat);
111 
112  if (sig_b[i*width + index] == q) {
113  RTLIL::SigSpec s = mux_cell_int.first->getPort("\\B");
114  s[i*width + index] = RTLIL::Sx;
115  mux_cell_int.first->setPort("\\B", s);
116  }
117  }
118 
119  for (auto &pat : find_muxtree_feedback_patterns(sig_a[index], q, path_else))
120  ret.insert(pat);
121 
122  if (sig_a[index] == q) {
123  RTLIL::SigSpec s = mux_cell_int.first->getPort("\\A");
124  s[index] = RTLIL::Sx;
125  mux_cell_int.first->setPort("\\A", s);
126  }
127 
128  return ret;
129  }
Dff2dffeWorker::bitusers
std::map< RTLIL::SigBit, int > bitusers
Definition: dff2dffe.cc:36
Dff2dffeWorker::pattern_t
std::map< RTLIL::SigBit, bool > pattern_t
Definition: dff2dffe.cc:38
Dff2dffeWorker::patterns_t
std::set< pattern_t > patterns_t
Definition: dff2dffe.cc:39
GetSize
int GetSize(RTLIL::Wire *wire)
Definition: yosys.cc:334
Dff2dffeWorker::find_muxtree_feedback_patterns
patterns_t find_muxtree_feedback_patterns(RTLIL::SigBit d, RTLIL::SigBit q, pattern_t path)
Definition: dff2dffe.cc:66
Dff2dffeWorker::bit2mux
std::map< RTLIL::SigBit, cell_int_t > bit2mux
Definition: dff2dffe.cc:34
Dff2dffeWorker::cell_int_t
std::pair< RTLIL::Cell *, int > cell_int_t
Definition: dff2dffe.cc:33
Dff2dffeWorker::sigmap
SigMap sigmap
Definition: dff2dffe.cc:30

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void Dff2dffeWorker::handle_dff_cell ( RTLIL::Cell *  dff_cell)
inline

Definition at line 154 of file dff2dffe.cc.

155  {
156  RTLIL::SigSpec sig_d = sigmap(dff_cell->getPort("\\D"));
157  RTLIL::SigSpec sig_q = sigmap(dff_cell->getPort("\\Q"));
158 
159  std::map<patterns_t, std::set<int>> grouped_patterns;
160  std::set<int> remaining_indices;
161 
162  for (int i = 0 ; i < GetSize(sig_d); i++) {
163  patterns_t patterns = find_muxtree_feedback_patterns(sig_d[i], sig_q[i], pattern_t());
164  if (!patterns.empty()) {
165  simplify_patterns(patterns);
166  grouped_patterns[patterns].insert(i);
167  } else
168  remaining_indices.insert(i);
169  }
170 
171  for (auto &it : grouped_patterns) {
172  RTLIL::SigSpec new_sig_d, new_sig_q;
173  for (int i : it.second) {
174  new_sig_d.append(sig_d[i]);
175  new_sig_q.append(sig_q[i]);
176  }
177  RTLIL::Cell *new_cell = module->addDffe(NEW_ID, dff_cell->getPort("\\CLK"), make_patterns_logic(it.first),
178  new_sig_d, new_sig_q, dff_cell->getParam("\\CLK_POLARITY").as_bool(), true);
179  log(" created $dffe cell %s for %s -> %s.\n", log_id(new_cell), log_signal(new_sig_d), log_signal(new_sig_q));
180  }
181 
182  if (remaining_indices.empty()) {
183  log(" removing now obsolete cell %s.\n", log_id(dff_cell));
184  module->remove(dff_cell);
185  } else if (GetSize(remaining_indices) != GetSize(sig_d)) {
186  log(" removing %d now obsolete bits from cell %s.\n", GetSize(sig_d) - GetSize(remaining_indices), log_id(dff_cell));
187  RTLIL::SigSpec new_sig_d, new_sig_q;
188  for (int i : remaining_indices) {
189  new_sig_d.append(sig_d[i]);
190  new_sig_q.append(sig_q[i]);
191  }
192  dff_cell->setPort("\\D", new_sig_d);
193  dff_cell->setPort("\\Q", new_sig_q);
194  dff_cell->setParam("\\WIDTH", GetSize(remaining_indices));
195  }
196  }
RTLIL::Const::as_bool
bool as_bool() const
Definition: rtlil.cc:96
RTLIL::Cell::setParam
void setParam(RTLIL::IdString paramname, RTLIL::Const value)
Definition: rtlil.cc:1829
Dff2dffeWorker::simplify_patterns
void simplify_patterns(patterns_t &)
Definition: dff2dffe.cc:131
log_signal
const char * log_signal(const RTLIL::SigSpec &sig, bool autoint)
Definition: log.cc:269
RTLIL::Cell::setPort
void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
Definition: rtlil.cc:1789
Dff2dffeWorker::pattern_t
std::map< RTLIL::SigBit, bool > pattern_t
Definition: dff2dffe.cc:38
Dff2dffeWorker::patterns_t
std::set< pattern_t > patterns_t
Definition: dff2dffe.cc:39
RTLIL::Cell::getPort
const RTLIL::SigSpec & getPort(RTLIL::IdString portname) const
Definition: rtlil.cc:1809
GetSize
int GetSize(RTLIL::Wire *wire)
Definition: yosys.cc:334
Dff2dffeWorker::find_muxtree_feedback_patterns
patterns_t find_muxtree_feedback_patterns(RTLIL::SigBit d, RTLIL::SigBit q, pattern_t path)
Definition: dff2dffe.cc:66
NEW_ID
#define NEW_ID
Definition: yosys.h:166
RTLIL::Module::remove
void remove(const std::set< RTLIL::Wire * > &wires)
Definition: rtlil.cc:1158
Dff2dffeWorker::sigmap
SigMap sigmap
Definition: dff2dffe.cc:30
log
void log(const char *format,...)
Definition: log.cc:180
RTLIL::Cell::getParam
const RTLIL::Const & getParam(RTLIL::IdString paramname) const
Definition: rtlil.cc:1834
RTLIL::SigSpec::append
void append(const RTLIL::SigSpec &signal)
Definition: rtlil.cc:2523
Dff2dffeWorker::make_patterns_logic
RTLIL::SigSpec make_patterns_logic(patterns_t patterns)
Definition: dff2dffe.cc:136
Dff2dffeWorker::module
RTLIL::Module * module
Definition: dff2dffe.cc:29
RTLIL::Module::addDffe
RTLIL::Cell * addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity=true, bool en_polarity=true)
Definition: rtlil.cc:1610
log_id
const char * log_id(RTLIL::IdString str)
Definition: log.cc:283

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RTLIL::SigSpec Dff2dffeWorker::make_patterns_logic ( patterns_t  patterns)
inline

Definition at line 136 of file dff2dffe.cc.

137  {
138  RTLIL::SigSpec or_input;
139  for (auto pat : patterns) {
140  RTLIL::SigSpec s1, s2;
141  for (auto it : pat) {
142  s1.append(it.first);
143  s2.append(it.second);
144  }
145  or_input.append(module->Ne(NEW_ID, s1, s2));
146  }
147  if (GetSize(or_input) == 0)
148  return RTLIL::S1;
149  if (GetSize(or_input) == 1)
150  return or_input;
151  return module->ReduceOr(NEW_ID, or_input);
152  }
RTLIL::Module::Ne
RTLIL::SigSpec Ne(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed=false)
GetSize
int GetSize(RTLIL::Wire *wire)
Definition: yosys.cc:334
NEW_ID
#define NEW_ID
Definition: yosys.h:166
RTLIL::Module::ReduceOr
RTLIL::SigSpec ReduceOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed=false)
RTLIL::SigSpec::append
void append(const RTLIL::SigSpec &signal)
Definition: rtlil.cc:2523
Dff2dffeWorker::module
RTLIL::Module * module
Definition: dff2dffe.cc:29

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void Dff2dffeWorker::run ( )
inline

Definition at line 198 of file dff2dffe.cc.

199  {
200  log("Transforming $dff to $dffe cells in module %s:\n", log_id(module));
201  for (auto dff_cell : dff_cells)
202  handle_dff_cell(dff_cell);
203  }
Dff2dffeWorker::dff_cells
std::vector< RTLIL::Cell * > dff_cells
Definition: dff2dffe.cc:35
Dff2dffeWorker::handle_dff_cell
void handle_dff_cell(RTLIL::Cell *dff_cell)
Definition: dff2dffe.cc:154
log
void log(const char *format,...)
Definition: log.cc:180
Dff2dffeWorker::module
RTLIL::Module * module
Definition: dff2dffe.cc:29
log_id
const char * log_id(RTLIL::IdString str)
Definition: log.cc:283

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void Dff2dffeWorker::simplify_patterns ( patterns_t &  )
inline

Definition at line 131 of file dff2dffe.cc.

132  {
133  // TBD
134  }

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Field Documentation

std::map<RTLIL::SigBit, cell_int_t> Dff2dffeWorker::bit2mux

Definition at line 34 of file dff2dffe.cc.

std::map<RTLIL::SigBit, int> Dff2dffeWorker::bitusers

Definition at line 36 of file dff2dffe.cc.

CellTypes Dff2dffeWorker::ct

Definition at line 31 of file dff2dffe.cc.

std::vector<RTLIL::Cell*> Dff2dffeWorker::dff_cells

Definition at line 35 of file dff2dffe.cc.

RTLIL::Module* Dff2dffeWorker::module

Definition at line 29 of file dff2dffe.cc.

SigMap Dff2dffeWorker::sigmap

Definition at line 30 of file dff2dffe.cc.

The documentation for this struct was generated from the following file: