FreduceWorker Struct Reference

Collaboration diagram for FreduceWorker:

Public Member Functions
	FreduceWorker (RTLIL::Design *design, RTLIL::Module *module)
bool	find_bit_in_cone (std::set< RTLIL::Cell * > &celldone, RTLIL::SigBit needle, RTLIL::SigBit haystack)
bool	find_bit_in_cone (RTLIL::SigBit needle, RTLIL::SigBit haystack)
void	dump ()
int	run ()

Data Fields
RTLIL::Design *	design
RTLIL::Module *	module
SigMap	sigmap
drivers_t	drivers
std::set< std::pair < RTLIL::SigBit, RTLIL::SigBit > >	inv_pairs

Detailed Description

Definition at line 551 of file freduce.cc.

Constructor & Destructor Documentation

FreduceWorker::FreduceWorker ( RTLIL::Design *  design, RTLIL::Module *  module  )

inline

Definition at line 560 of file freduce.cc.

                                                            : design(design), module(module), sigmap(module)
    {
    }

Member Function Documentation

void FreduceWorker::dump ( )

inline

Definition at line 589 of file freduce.cc.

    {
        std::string filename = stringf("%s_%s_%05d.il", dump_prefix.c_str(), RTLIL::id2cstr(module->name), reduce_counter);
        log("%s    Writing dump file `%s'.\n", reduce_counter ? "  " : "", filename.c_str());
        Pass::call(design, stringf("dump -outfile %s %s", filename.c_str(), design->selected_active_module.empty() ? module->name.c_str() : ""));
    }

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bool FreduceWorker::find_bit_in_cone ( std::set< RTLIL::Cell * > &  celldone, RTLIL::SigBit  needle, RTLIL::SigBit  haystack  )

inline

Definition at line 564 of file freduce.cc.

    {
        if (needle == haystack)
            return true;
        if (haystack.wire == NULL || needle.wire == NULL || drivers.count(haystack) == 0)
            return false;

        std::pair<RTLIL::Cell*, std::set<RTLIL::SigBit>> &drv = drivers.at(haystack);

        if (celldone.count(drv.first))
            return false;
        celldone.insert(drv.first);

        for (auto &bit : drv.second)
            if (find_bit_in_cone(celldone, needle, bit))
                return true;
        return false;
    }

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bool FreduceWorker::find_bit_in_cone ( RTLIL::SigBit  needle, RTLIL::SigBit  haystack  )

inline

Definition at line 583 of file freduce.cc.

    {
        std::set<RTLIL::Cell*> celldone;
        return find_bit_in_cone(celldone, needle, haystack);
    }

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int FreduceWorker::run ( )

inline

Definition at line 596 of file freduce.cc.

    {
        log("Running functional reduction on module %s:\n", RTLIL::id2cstr(module->name));

        CellTypes ct;
        ct.setup_internals();
        ct.setup_stdcells();

        int bits_full_total = 0;
        std::vector<std::set<RTLIL::SigBit>> batches;
        for (auto &it : module->wires_)
            if (it.second->port_input) {
                batches.push_back(sigmap(it.second).to_sigbit_set());
                bits_full_total += it.second->width;
            }
        for (auto &it : module->cells_) {
            if (ct.cell_known(it.second->type)) {
                std::set<RTLIL::SigBit> inputs, outputs;
                for (auto &port : it.second->connections()) {
                    std::vector<RTLIL::SigBit> bits = sigmap(port.second).to_sigbit_vector();
                    if (ct.cell_output(it.second->type, port.first))
                        outputs.insert(bits.begin(), bits.end());
                    else
                        inputs.insert(bits.begin(), bits.end());
                }
                std::pair<RTLIL::Cell*, std::set<RTLIL::SigBit>> drv(it.second, inputs);
                for (auto &bit : outputs)
                    drivers[bit] = drv;
                batches.push_back(outputs);
                bits_full_total += outputs.size();
            }
            if (inv_mode && it.second->type == "$_NOT_")
                inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(it.second->getPort("\\A")), sigmap(it.second->getPort("\\Y"))));
        }

        int bits_count = 0;
        int bits_full_count = 0;
        std::map<std::vector<RTLIL::SigBit>, std::vector<RTLIL::SigBit>> buckets;
        for (auto &batch : batches)
        {
            for (auto &bit : batch)
                if (bit.wire != NULL && design->selected(module, bit.wire))
                    goto found_selected_wire;
            bits_full_count += batch.size();
            continue;

        found_selected_wire:
            log("  Finding reduced input cone for signal batch %s%c\n",
                    log_signal(batch), verbose_level ? ':' : '.');

            FindReducedInputs infinder(sigmap, drivers);
            for (auto &bit : batch) {
                std::vector<RTLIL::SigBit> inputs;
                infinder.analyze(inputs, bit, 100 * bits_full_count / bits_full_total);
                buckets[inputs].push_back(bit);
                bits_full_count++;
                bits_count++;
            }
        }
        log("  Sorted %d signal bits into %d buckets.\n", bits_count, int(buckets.size()));

        int bucket_count = 0;
        std::vector<std::vector<equiv_bit_t>> equiv;
        for (auto &bucket : buckets)
        {
            bucket_count++;

            if (bucket.second.size() == 1)
                continue;

            if (bucket.first.size() == 0) {
                log("  Finding const values for bucket %s%c\n", log_signal(bucket.second), verbose_level ? ':' : '.');
                PerformReduction worker(sigmap, drivers, inv_pairs, bucket.second, bucket.first.size());
                for (size_t idx = 0; idx < bucket.second.size(); idx++)
                    worker.analyze_const(equiv, idx);
            } else {
                log("  Trying to shatter bucket %s%c\n", log_signal(bucket.second), verbose_level ? ':' : '.');
                PerformReduction worker(sigmap, drivers, inv_pairs, bucket.second, bucket.first.size());
                worker.analyze(equiv, 100 * bucket_count / (buckets.size() + 1));
            }
        }

        std::map<RTLIL::SigBit, int> bitusage;
        module->rewrite_sigspecs(CountBitUsage(sigmap, bitusage));

        if (!dump_prefix.empty())
            dump();

        log("  Rewiring %d equivialent groups:\n", int(equiv.size()));
        int rewired_sigbits = 0;
        for (auto &grp : equiv)
        {
            log("    [%05d] Using as master for group: %s\n", ++reduce_counter, log_signal(grp.front().bit));

            RTLIL::SigSpec inv_sig;
            for (size_t i = 1; i < grp.size(); i++)
            {
                if (!design->selected(module, grp[i].bit.wire)) {
                    log("      Skipping not-selected slave: %s\n", log_signal(grp[i].bit));
                    continue;
                }

                if (grp[i].bit.wire->port_id == 0 && bitusage[grp[i].bit] <= 1) {
                    log("      Skipping unused slave: %s\n", log_signal(grp[i].bit));
                    continue;
                }

                if (find_bit_in_cone(grp[i].bit, grp.front().bit)) {
                    log("      Skipping dependency of master: %s\n", log_signal(grp[i].bit));
                    continue;
                }

                log("      Connect slave%s: %s\n", grp[i].inverted ? " using inverter" : "", log_signal(grp[i].bit));

                RTLIL::Cell *drv = drivers.at(grp[i].bit).first;
                RTLIL::Wire *dummy_wire = module->addWire(NEW_ID);
                for (auto &port : drv->connections_)
                    if (ct.cell_output(drv->type, port.first))
                        sigmap(port.second).replace(grp[i].bit, dummy_wire, &port.second);

                if (grp[i].inverted)
                {
                    if (inv_sig.size() == 0)
                    {
                        inv_sig = module->addWire(NEW_ID);

                        RTLIL::Cell *inv_cell = module->addCell(NEW_ID, "$_NOT_");
                        inv_cell->setPort("\\A", grp[0].bit);
                        inv_cell->setPort("\\Y", inv_sig);
                    }

                    module->connect(RTLIL::SigSig(grp[i].bit, inv_sig));
                }
                else
                    module->connect(RTLIL::SigSig(grp[i].bit, grp[0].bit));

                rewired_sigbits++;
            }

            if (!dump_prefix.empty())
                dump();

            if (reduce_counter == reduce_stop_at) {
                log("    Reached limit passed using -stop option. Skipping all further reductions.\n");
                break;
            }
        }

        log("  Rewired a total of %d signal bits in module %s.\n", rewired_sigbits, RTLIL::id2cstr(module->name));
        return rewired_sigbits;
    }

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Field Documentation

RTLIL::Design* FreduceWorker::design

Definition at line 553 of file freduce.cc.

drivers_t FreduceWorker::drivers

Definition at line 557 of file freduce.cc.

std::set<std::pair<RTLIL::SigBit, RTLIL::SigBit> > FreduceWorker::inv_pairs

Definition at line 558 of file freduce.cc.

RTLIL::Module* FreduceWorker::module

Definition at line 554 of file freduce.cc.

SigMap FreduceWorker::sigmap

Definition at line 556 of file freduce.cc.

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The documentation for this struct was generated from the following file:

• freduce.cc