yosys-master
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Friends Macros
Data Structures | Functions | Variables
techmap.cc File Reference
#include "kernel/yosys.h"
#include "kernel/utils.h"
#include "kernel/sigtools.h"
#include "libs/sha1/sha1.h"
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include "passes/techmap/techmap.inc"
+ Include dependency graph for techmap.cc:

Go to the source code of this file.

Data Structures

struct  TechmapWorker
 
struct  TechmapWorker::TechmapWireData
 
struct  TechmapPass
 
struct  FlattenPass
 

Functions

YOSYS_NAMESPACE_BEGIN void simplemap_get_mappers (std::map< RTLIL::IdString, void(*)(RTLIL::Module *, RTLIL::Cell *)> &mappers)
 
void maccmap (RTLIL::Module *module, RTLIL::Cell *cell, bool unmap=false)
 
YOSYS_NAMESPACE_END
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN void 		apply_prefix (std::string prefix, std::string &id)
 
void apply_prefix (std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module *module)
 

Variables

TechmapPass TechmapPass
 
FlattenPass FlattenPass
 

Function Documentation

YOSYS_NAMESPACE_END USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN void apply_prefix ( std::string  prefix,
std::string &  id 
)

Definition at line 44 of file techmap.cc.

45 {
46  if (id[0] == '\\')
47  id = prefix + "." + id.substr(1);
48  else
49  id = "$techmap" + prefix + "." + id;
50 }
id
std::string id(RTLIL::IdString internal_id, bool may_rename=true)
Definition: verilog_backend.cc:96

+ Here is the call graph for this function:

+ Here is the caller graph for this function:

void apply_prefix ( std::string  prefix,
RTLIL::SigSpec &  sig,
RTLIL::Module *  module 
)

Definition at line 52 of file techmap.cc.

53 {
54  std::vector<RTLIL::SigChunk> chunks = sig;
55  for (auto &chunk : chunks)
56  if (chunk.wire != NULL) {
57  std::string wire_name = chunk.wire->name.str();
58  apply_prefix(prefix, wire_name);
59  log_assert(module->wires_.count(wire_name) > 0);
60  chunk.wire = module->wires_[wire_name];
61  }
62  sig = chunks;
63 }
apply_prefix
YOSYS_NAMESPACE_END USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN void apply_prefix(std::string prefix, std::string &id)
Definition: techmap.cc:44
RTLIL::Module::wires_
std::map< RTLIL::IdString, RTLIL::Wire * > wires_
Definition: rtlil.h:595
log_assert
#define log_assert(_assert_expr_)
Definition: log.h:85
NULL
#define NULL
Definition: NumberlikeArray.hh:6

+ Here is the call graph for this function:

void maccmap ( RTLIL::Module *  module,
RTLIL::Cell *  cell,
bool  unmap = false 
)

Definition at line 265 of file maccmap.cc.

266 {
267  int width = GetSize(cell->getPort("\\Y"));
268 
269  Macc macc;
270  macc.from_cell(cell);
271 
272  RTLIL::SigSpec all_input_bits;
273  all_input_bits.append(cell->getPort("\\A"));
274  all_input_bits.append(cell->getPort("\\B"));
275 
276  if (all_input_bits.to_sigbit_set().count(RTLIL::Sx)) {
277  module->connect(cell->getPort("\\Y"), RTLIL::SigSpec(RTLIL::Sx, width));
278  return;
279  }
280 
281  for (auto &port : macc.ports)
282  if (GetSize(port.in_b) == 0)
283  log(" %s %s (%d bits, %s)\n", port.do_subtract ? "sub" : "add", log_signal(port.in_a),
284  GetSize(port.in_a), port.is_signed ? "signed" : "unsigned");
285  else
286  log(" %s %s * %s (%dx%d bits, %s)\n", port.do_subtract ? "sub" : "add", log_signal(port.in_a), log_signal(port.in_b),
287  GetSize(port.in_a), GetSize(port.in_b), port.is_signed ? "signed" : "unsigned");
288 
289  if (GetSize(macc.bit_ports) != 0)
290  log(" add bits %s (%d bits)\n", log_signal(macc.bit_ports), GetSize(macc.bit_ports));
291 
292  if (unmap)
293  {
294  typedef std::pair<RTLIL::SigSpec, bool> summand_t;
295  std::vector<summand_t> summands;
296 
297  for (auto &port : macc.ports) {
298  summand_t this_summand;
299  if (GetSize(port.in_b)) {
300  this_summand.first = module->addWire(NEW_ID, width);
301  module->addMul(NEW_ID, port.in_a, port.in_b, this_summand.first, port.is_signed);
302  } else if (GetSize(port.in_a) != width) {
303  this_summand.first = module->addWire(NEW_ID, width);
304  module->addPos(NEW_ID, port.in_a, this_summand.first, port.is_signed);
305  } else {
306  this_summand.first = port.in_a;
307  }
308  this_summand.second = port.do_subtract;
309  summands.push_back(this_summand);
310  }
311 
312  for (auto &bit : macc.bit_ports)
313  summands.push_back(summand_t(bit, false));
314 
315  if (GetSize(summands) == 0)
316  summands.push_back(summand_t(RTLIL::SigSpec(0, width), false));
317 
318  while (GetSize(summands) > 1)
319  {
320  std::vector<summand_t> new_summands;
321  for (int i = 0; i < GetSize(summands); i += 2) {
322  if (i+1 < GetSize(summands)) {
323  summand_t this_summand;
324  this_summand.first = module->addWire(NEW_ID, width);
325  this_summand.second = summands[i].second && summands[i+1].second;
326  if (summands[i].second == summands[i+1].second)
327  module->addAdd(NEW_ID, summands[i].first, summands[i+1].first, this_summand.first);
328  else if (summands[i].second)
329  module->addSub(NEW_ID, summands[i+1].first, summands[i].first, this_summand.first);
330  else if (summands[i+1].second)
331  module->addSub(NEW_ID, summands[i].first, summands[i+1].first, this_summand.first);
332  else
333  log_abort();
334  new_summands.push_back(this_summand);
335  } else
336  new_summands.push_back(summands[i]);
337  }
338  summands.swap(new_summands);
339  }
340 
341  if (summands.front().second)
342  module->addNeg(NEW_ID, summands.front().first, cell->getPort("\\Y"));
343  else
344  module->connect(cell->getPort("\\Y"), summands.front().first);
345  }
346  else
347  {
348  MaccmapWorker worker(module, width);
349 
350  for (auto &port : macc.ports)
351  if (GetSize(port.in_b) == 0)
352  worker.add(port.in_a, port.is_signed, port.do_subtract);
353  else
354  worker.add(port.in_a, port.in_b, port.is_signed, port.do_subtract);
355 
356  for (auto &bit : macc.bit_ports)
357  worker.add(bit, 0);
358 
359  module->connect(cell->getPort("\\Y"), worker.synth());
360  }
361 }
Macc
Definition: macc.h:27
RTLIL::SigSpec::to_sigbit_set
std::set< RTLIL::SigBit > to_sigbit_set() const
Definition: rtlil.cc:2909
log_signal
const char * log_signal(const RTLIL::SigSpec &sig, bool autoint)
Definition: log.cc:269
RTLIL::Module::addAdd
RTLIL::Cell * addAdd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed=false)
log_abort
#define log_abort()
Definition: log.h:84
RTLIL::Module::addNeg
RTLIL::Cell * addNeg(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed=false)
RTLIL::Module::connect
void connect(const RTLIL::SigSig &conn)
Definition: rtlil.cc:1278
RTLIL::Cell::getPort
const RTLIL::SigSpec & getPort(RTLIL::IdString portname) const
Definition: rtlil.cc:1809
GetSize
int GetSize(RTLIL::Wire *wire)
Definition: yosys.cc:334
RTLIL::Module::addWire
RTLIL::Wire * addWire(RTLIL::IdString name, int width=1)
Definition: rtlil.cc:1331
NEW_ID
#define NEW_ID
Definition: yosys.h:166
RTLIL::Module::addMul
RTLIL::Cell * addMul(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed=false)
Macc::from_cell
void from_cell(RTLIL::Cell *cell)
Definition: macc.h:100
RTLIL::Module::addSub
RTLIL::Cell * addSub(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed=false)
log
void log(const char *format,...)
Definition: log.cc:180
RTLIL::SigSpec::append
void append(const RTLIL::SigSpec &signal)
Definition: rtlil.cc:2523
RTLIL::Module::addPos
RTLIL::Cell * addPos(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed=false)

+ Here is the call graph for this function:

+ Here is the caller graph for this function:

YOSYS_NAMESPACE_BEGIN void simplemap_get_mappers ( std::map< RTLIL::IdString, void(*)(RTLIL::Module *, RTLIL::Cell *)> &  mappers)

Definition at line 403 of file simplemap.cc.

404 {
405  mappers["$not"] = simplemap_not;
406  mappers["$pos"] = simplemap_pos;
407  mappers["$and"] = simplemap_bitop;
408  mappers["$or"] = simplemap_bitop;
409  mappers["$xor"] = simplemap_bitop;
410  mappers["$xnor"] = simplemap_bitop;
411  mappers["$reduce_and"] = simplemap_reduce;
412  mappers["$reduce_or"] = simplemap_reduce;
413  mappers["$reduce_xor"] = simplemap_reduce;
414  mappers["$reduce_xnor"] = simplemap_reduce;
415  mappers["$reduce_bool"] = simplemap_reduce;
416  mappers["$logic_not"] = simplemap_lognot;
417  mappers["$logic_and"] = simplemap_logbin;
418  mappers["$logic_or"] = simplemap_logbin;
419  mappers["$mux"] = simplemap_mux;
420  mappers["$slice"] = simplemap_slice;
421  mappers["$concat"] = simplemap_concat;
422  mappers["$sr"] = simplemap_sr;
423  mappers["$dff"] = simplemap_dff;
424  mappers["$dffe"] = simplemap_dffe;
425  mappers["$dffsr"] = simplemap_dffsr;
426  mappers["$adff"] = simplemap_adff;
427  mappers["$dlatch"] = simplemap_dlatch;
428 }
simplemap_bitop
static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
Definition: simplemap.cc:54
simplemap_lognot
static void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell)
Definition: simplemap.cc:186
simplemap_pos
static void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell)
Definition: simplemap.cc:44
simplemap_dffsr
static void simplemap_dffsr(RTLIL::Module *module, RTLIL::Cell *cell)
Definition: simplemap.cc:327
simplemap_dff
static void simplemap_dff(RTLIL::Module *module, RTLIL::Cell *cell)
Definition: simplemap.cc:286
simplemap_mux
static void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell)
Definition: simplemap.cc:235
simplemap_dffe
static void simplemap_dffe(RTLIL::Module *module, RTLIL::Cell *cell)
Definition: simplemap.cc:305
simplemap_concat
static void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell)
Definition: simplemap.cc:258
simplemap_sr
static void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell)
Definition: simplemap.cc:266
simplemap_slice
static void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell)
Definition: simplemap.cc:250
simplemap_adff
static void simplemap_adff(RTLIL::Module *module, RTLIL::Cell *cell)
Definition: simplemap.cc:352
simplemap_reduce
static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
Definition: simplemap.cc:91
simplemap_dlatch
static void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell)
Definition: simplemap.cc:379
simplemap_not
USING_YOSYS_NAMESPACE static PRIVATE_NAMESPACE_BEGIN void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
Definition: simplemap.cc:30
simplemap_logbin
static void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
Definition: simplemap.cc:206

+ Here is the call graph for this function:

+ Here is the caller graph for this function:

Variable Documentation

FlattenPass FlattenPass
TechmapPass TechmapPass