1042 log_header(
"Executing FLATTEN pass (flatten design).\n");
1050 std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> celltypeMap;
1052 celltypeMap[it.first].insert(it.first);
1056 for (
auto mod : design->
modules())
1057 if (mod->get_bool_attribute(
"\\top"))
1061 std::set<RTLIL::Cell*> handled_cells;
1062 while (did_something) {
1063 did_something =
false;
1064 if (top_mod !=
NULL) {
1065 if (worker.
techmap_module(design, top_mod, design, handled_cells, celltypeMap,
false))
1066 did_something =
true;
1068 for (
auto mod : design->
modules())
1069 if (worker.
techmap_module(design, mod, design, handled_cells, celltypeMap,
false))
1070 did_something =
true;
1074 log(
"No more expansions possible.\n");
1076 if (top_mod !=
NULL) {
1077 std::map<RTLIL::IdString, RTLIL::Module*> new_modules;
1078 for (
auto mod : design->
modules())
1079 if (mod == top_mod || mod->get_bool_attribute(
"\\blackbox")) {
1080 new_modules[mod->name] = mod;
1082 log(
"Deleting now unused module %s.\n",
log_id(mod));
1085 design->
modules_.swap(new_modules);
void log_header(const char *format,...)
USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN bool did_something
bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set< RTLIL::Cell * > &handled_cells, const std::map< RTLIL::IdString, std::set< RTLIL::IdString, RTLIL::sort_by_id_str >> &celltypeMap, bool in_recursion)
bool full_selection() const
RTLIL::ObjRange< RTLIL::Module * > modules()
std::map< RTLIL::IdString, RTLIL::Module * > modules_
void log(const char *format,...)
void extra_args(std::vector< std::string > args, size_t argidx, RTLIL::Design *design, bool select=true)
const char * log_id(RTLIL::IdString str)