MaccmapWorker Struct Reference

Collaboration diagram for MaccmapWorker:

Public Member Functions
	MaccmapWorker (RTLIL::Module *module, int width)
void	add (RTLIL::SigBit bit, int position)
void	add (RTLIL::SigSpec a, bool is_signed, bool do_subtract)
void	add (RTLIL::SigSpec a, RTLIL::SigSpec b, bool is_signed, bool do_subtract)
void	fulladd (RTLIL::SigSpec &in1, RTLIL::SigSpec &in2, RTLIL::SigSpec &in3, RTLIL::SigSpec &out1, RTLIL::SigSpec &out2)
int	tree_bit_slots (int n)
RTLIL::SigSpec	synth ()

Data Fields
std::vector< std::set < RTLIL::SigBit > >	bits
RTLIL::Module *	module
int	width

Detailed Description

Definition at line 26 of file maccmap.cc.

Constructor & Destructor Documentation

MaccmapWorker::MaccmapWorker ( RTLIL::Module *  module, int  width  )

inline

Definition at line 32 of file maccmap.cc.

                                                  : module(module), width(width)
    {
        bits.resize(width);
    }

Member Function Documentation

void MaccmapWorker::add ( RTLIL::SigBit  bit, int  position  )

inline

Definition at line 37 of file maccmap.cc.

    {
        if (position >= width || bit == RTLIL::S0)
            return;

        if (bits.at(position).count(bit)) {
            bits.at(position).erase(bit);
            add(bit, position+1);
        } else {
            bits.at(position).insert(bit);
        }
    }

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void MaccmapWorker::add ( RTLIL::SigSpec  a, bool  is_signed, bool  do_subtract  )

inline

Definition at line 50 of file maccmap.cc.

    {
        a.extend(width, is_signed);

        if (do_subtract) {
            a = module->Not(NEW_ID, a);
            add(RTLIL::S1, 0);
        }

        for (int i = 0; i < width; i++)
            add(a[i], i);
    }

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void MaccmapWorker::add ( RTLIL::SigSpec  a, RTLIL::SigSpec  b, bool  is_signed, bool  do_subtract  )

inline

Definition at line 63 of file maccmap.cc.

    {
        if (GetSize(a) < GetSize(b))
            std::swap(a, b);

        a.extend(width, is_signed);

        if (GetSize(b) > width)
            b.extend(width, is_signed);

        for (int i = 0; i < GetSize(b); i++)
            if (is_signed && i+1 == GetSize(b))
            {
                a = {module->Not(NEW_ID, a.extract(i, width-i)), RTLIL::SigSpec(0, i)};
                add(module->And(NEW_ID, a, RTLIL::SigSpec(b[i], width)), false, do_subtract);
                add({b[i], RTLIL::SigSpec(0, i)}, false, do_subtract);
            }
            else
            {
                add(module->And(NEW_ID, a, RTLIL::SigSpec(b[i], width)), false, do_subtract);
                a = {a.extract(0, width-1), RTLIL::S0};
            }
    }

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void MaccmapWorker::fulladd ( RTLIL::SigSpec &  in1, RTLIL::SigSpec &  in2, RTLIL::SigSpec &  in3, RTLIL::SigSpec &  out1, RTLIL::SigSpec &  out2  )

inline

Definition at line 87 of file maccmap.cc.

    {
        int start_index = 0, stop_index = GetSize(in1);

        while (start_index < stop_index && in1[start_index] == RTLIL::S0 && in2[start_index] == RTLIL::S0 && in3[start_index] == RTLIL::S0)
            start_index++;

        while (start_index < stop_index && in1[stop_index-1] == RTLIL::S0 && in2[stop_index-1] == RTLIL::S0 && in3[stop_index-1] == RTLIL::S0)
            stop_index--;

        if (start_index == stop_index)
        {
            out1 = RTLIL::SigSpec(0, GetSize(in1));
            out2 = RTLIL::SigSpec(0, GetSize(in1));
        }
        else
        {
            RTLIL::SigSpec out_zeros_lsb(0, start_index), out_zeros_msb(0, GetSize(in1)-stop_index);

            in1 = in1.extract(start_index, stop_index-start_index);
            in2 = in2.extract(start_index, stop_index-start_index);
            in3 = in3.extract(start_index, stop_index-start_index);

            int width = GetSize(in1);
            RTLIL::Wire *w1 = module->addWire(NEW_ID, width);
            RTLIL::Wire *w2 = module->addWire(NEW_ID, width);

            RTLIL::Cell *cell = module->addCell(NEW_ID, "$fa");
            cell->setParam("\\WIDTH", width);
            cell->setPort("\\A", in1);
            cell->setPort("\\B", in2);
            cell->setPort("\\C", in3);
            cell->setPort("\\Y", w1);
            cell->setPort("\\X", w2);

            out1 = {out_zeros_msb, w1, out_zeros_lsb};
            out2 = {out_zeros_msb, w2, out_zeros_lsb};
        }
    }

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RTLIL::SigSpec MaccmapWorker::synth ( )

inline

Definition at line 141 of file maccmap.cc.

    {
        std::vector<RTLIL::SigSpec> summands;
        std::vector<RTLIL::SigBit> tree_sum_bits;
        int unique_tree_bits = 0;
        int count_tree_words = 0;

        while (1)
        {
            RTLIL::SigSpec summand(0, width);
            bool got_data_bits = false;

            for (int i = 0; i < width; i++)
                if (!bits.at(i).empty()) {
                    auto it = bits.at(i).begin();
                    summand[i] = *it;
                    bits.at(i).erase(it);
                    got_data_bits = true;
                }

            if (!got_data_bits)
                break;

            summands.push_back(summand);

            while (1)
            {
                int free_bit_slots = tree_bit_slots(GetSize(summands)) - GetSize(tree_sum_bits);

                int max_depth = 0, max_position = 0;
                for (int i = 0; i < width; i++)
                    if (max_depth <= GetSize(bits.at(i))) {
                        max_depth = GetSize(bits.at(i));
                        max_position = i;
                    }

                if (max_depth == 0 || max_position > 4)
                    break;

                int required_bits = 0;
                for (int i = 0; i <= max_position; i++)
                    if (GetSize(bits.at(i)) == max_depth)
                        required_bits += 1 << i;

                if (required_bits > free_bit_slots)
                    break;

                for (int i = 0; i <= max_position; i++)
                    if (GetSize(bits.at(i)) == max_depth) {
                        auto it = bits.at(i).begin();
                        RTLIL::SigBit bit = *it;
                        for (int k = 0; k < (1 << i); k++, free_bit_slots--)
                            tree_sum_bits.push_back(bit);
                        bits.at(i).erase(it);
                        unique_tree_bits++;
                    }

                count_tree_words++;
            }
        }

        if (!tree_sum_bits.empty())
            log("  packed %d (%d) bits / %d words into adder tree\n", GetSize(tree_sum_bits), unique_tree_bits, count_tree_words);

        if (GetSize(summands) == 0) {
            log_assert(tree_sum_bits.empty());
            return RTLIL::SigSpec(0, width);
        }

        if (GetSize(summands) == 1) {
            log_assert(tree_sum_bits.empty());
            return summands.front();
        }

        while (GetSize(summands) > 2)
        {
            std::vector<RTLIL::SigSpec> new_summands;
            for (int i = 0; i < GetSize(summands); i += 3)
                if (i+2 < GetSize(summands)) {
                    RTLIL::SigSpec in1 = summands[i];
                    RTLIL::SigSpec in2 = summands[i+1];
                    RTLIL::SigSpec in3 = summands[i+2];
                    RTLIL::SigSpec out1, out2;
                    fulladd(in1, in2, in3, out1, out2);
                    RTLIL::SigBit extra_bit = RTLIL::S0;
                    if (!tree_sum_bits.empty()) {
                        extra_bit = tree_sum_bits.back();
                        tree_sum_bits.pop_back();
                    }
                    new_summands.push_back(out1);
                    new_summands.push_back({out2.extract(0, width-1), extra_bit});
                } else {
                    new_summands.push_back(summands[i]);
                    i -= 2;
                }
            summands.swap(new_summands);
        }


        RTLIL::Cell *c = module->addCell(NEW_ID, "$alu");
        c->setPort("\\A", summands.front());
        c->setPort("\\B", summands.back());
        c->setPort("\\CI", RTLIL::S0);
        c->setPort("\\BI", RTLIL::S0);
        c->setPort("\\Y", module->addWire(NEW_ID, width));
        c->setPort("\\X", module->addWire(NEW_ID, width));
        c->setPort("\\CO", module->addWire(NEW_ID, width));
        c->fixup_parameters();

        if (!tree_sum_bits.empty()) {
            c->setPort("\\CI", tree_sum_bits.back());
            tree_sum_bits.pop_back();
        }
        log_assert(tree_sum_bits.empty());

        return c->getPort("\\Y");
    }

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int MaccmapWorker::tree_bit_slots ( int  n )

inline

Definition at line 127 of file maccmap.cc.

    {
    #if 0
        int retval = 1;
        while (n > 2) {
            retval += n / 3;
            n = 2*(n / 3) + (n % 3);
        }
        return retval;
    #else
        return std::max(n - 1, 0);
    #endif
    }

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Field Documentation

std::vector<std::set<RTLIL::SigBit> > MaccmapWorker::bits

Definition at line 28 of file maccmap.cc.

RTLIL::Module* MaccmapWorker::module

Definition at line 29 of file maccmap.cc.

int MaccmapWorker::width

Definition at line 30 of file maccmap.cc.

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The documentation for this struct was generated from the following file:

• maccmap.cc