Inheritance diagram for TechmapPass:

Collaboration diagram for TechmapPass:

Public Member Functions
	TechmapPass ()

virtual void	help ()

virtual void	execute (std::vector< std::string > args, RTLIL::Design *design)

pre_post_exec_state_t	pre_execute ()

void	post_execute (pre_post_exec_state_t state)

void	cmd_log_args (const std::vector< std::string > &args)

void	cmd_error (const std::vector< std::string > &args, size_t argidx, std::string msg)

void	extra_args (std::vector< std::string > args, size_t argidx, RTLIL::Design *design, bool select=true)

virtual void	run_register ()

Static Public Member Functions
static void	call (RTLIL::Design *design, std::string command)

static void	call (RTLIL::Design *design, std::vector< std::string > args)

static void	call_on_selection (RTLIL::Design *design, const RTLIL::Selection &selection, std::string command)

static void	call_on_selection (RTLIL::Design *design, const RTLIL::Selection &selection, std::vector< std::string > args)

static void	call_on_module (RTLIL::Design design, RTLIL::Module module, std::string command)

static void	call_on_module (RTLIL::Design design, RTLIL::Module module, std::vector< std::string > args)

static void	init_register ()

static void	done_register ()

Data Fields
std::string	pass_name

std::string	short_help

int	call_counter

int64_t	runtime_ns

Pass *	next_queued_pass

Detailed Description

Definition at line 763 of file techmap.cc.

Constructor & Destructor Documentation

TechmapPass::TechmapPass ( )

inline

Definition at line 764 of file techmap.cc.

764 : Pass("techmap", "generic technology mapper") { }

Pass::Pass

Pass(std::string name, std::string short_help="** document me **")

Definition: register.cc:40

Member Function Documentation

void Pass::call	(	RTLIL::Design *	design,
		std::string	command
	)

staticinherited

Definition at line 146 of file register.cc.

 {
     std::vector<std::string> args;
 
     std::string cmd_buf = command;
     std::string tok = next_token(cmd_buf, " \t\r\n");
 
     if (tok.empty() || tok[0] == '#')
         return;
 
     if (tok[0] == '!') {
         cmd_buf = command.substr(command.find('!') + 1);
         while (!cmd_buf.empty() && (cmd_buf.back() == ' ' || cmd_buf.back() == '\t' ||
                 cmd_buf.back() == '\r' || cmd_buf.back() == '\n'))
             cmd_buf.resize(cmd_buf.size()-1);
         log_header("Shell command: %s\n", cmd_buf.c_str());
         int retCode = run_command(cmd_buf);
         if (retCode != 0)
             log_cmd_error("Shell command returned error code %d.\n", retCode);
         return;
     }
 
     while (!tok.empty()) {
         if (tok == "#")
             break;
         if (tok.back() == ';') {
             int num_semikolon = 0;
             while (!tok.empty() && tok.back() == ';')
                 tok.resize(tok.size()-1), num_semikolon++;
             if (!tok.empty())
                 args.push_back(tok);
             call(design, args);
             args.clear();
             if (num_semikolon == 2)
                 call(design, "clean");
             if (num_semikolon == 3)
                 call(design, "clean -purge");
         } else
             args.push_back(tok);
         tok = next_token(cmd_buf, " \t\r\n");
     }
 
     call(design, args);
 }

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void Pass::call	(	RTLIL::Design *	design,
		std::vector< std::string >	args
	)

staticinherited

Definition at line 191 of file register.cc.

 {
     if (args.size() == 0 || args[0][0] == '#')
         return;
 
     if (echo_mode) {
         log("%s", create_prompt(design, 0));
         for (size_t i = 0; i < args.size(); i++)
             log("%s%s", i ? " " : "", args[i].c_str());
         log("\n");
     }
 
     if (pass_register.count(args[0]) == 0)
         log_cmd_error("No such command: %s (type 'help' for a command overview)\n", args[0].c_str());
 
     size_t orig_sel_stack_pos = design->selection_stack.size();
     auto state = pass_register[args[0]]->pre_execute();
     pass_register[args[0]]->execute(args, design);
     pass_register[args[0]]->post_execute(state);
     while (design->selection_stack.size() > orig_sel_stack_pos)
         design->selection_stack.pop_back();
 
     design->check();
 }

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void Pass::call_on_module	(	RTLIL::Design *	design,
		RTLIL::Module *	module,
		std::string	command
	)

staticinherited

Definition at line 240 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module = module->name.str();
     design->selection_stack.push_back(RTLIL::Selection(false));
     design->selection_stack.back().select(module);
 
     Pass::call(design, command);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

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void Pass::call_on_module	(	RTLIL::Design *	design,
		RTLIL::Module *	module,
		std::vector< std::string >	args
	)

staticinherited

Definition at line 253 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module = module->name.str();
     design->selection_stack.push_back(RTLIL::Selection(false));
     design->selection_stack.back().select(module);
 
     Pass::call(design, args);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

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void Pass::call_on_selection	(	RTLIL::Design *	design,
		const RTLIL::Selection &	selection,
		std::string	command
	)

staticinherited

Definition at line 216 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module.clear();
     design->selection_stack.push_back(selection);
 
     Pass::call(design, command);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

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void Pass::call_on_selection	(	RTLIL::Design *	design,
		const RTLIL::Selection &	selection,
		std::vector< std::string >	args
	)

staticinherited

Definition at line 228 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module.clear();
     design->selection_stack.push_back(selection);
 
     Pass::call(design, args);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

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void Pass::cmd_error	(	const std::vector< std::string > &	args,
		size_t	argidx,
		std::string	msg
	)

inherited

Definition at line 110 of file register.cc.

 {
     std::string command_text;
     int error_pos = 0;
 
     for (size_t i = 0; i < args.size(); i++) {
         if (i < argidx)
             error_pos += args[i].size() + 1;
         command_text = command_text + (command_text.empty() ? "" : " ") + args[i];
     }
 
     log("\nSyntax error in command `%s':\n", command_text.c_str());
     help();
 
     log_cmd_error("Command syntax error: %s\n> %s\n> %*s^\n",
             msg.c_str(), command_text.c_str(), error_pos, "");
 }

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void Pass::cmd_log_args ( const std::vector< std::string > & args )

inherited

Definition at line 100 of file register.cc.

 {
     if (args.size() <= 1)
         return;
     log("Full command line:");
     for (size_t i = 0; i < args.size(); i++)
         log(" %s", args[i].c_str());
     log("\n");
 }

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void Pass::done_register ( )

staticinherited

Definition at line 62 of file register.cc.

 {
     frontend_register.clear();
     pass_register.clear();
     backend_register.clear();
     log_assert(first_queued_pass == NULL);
 }

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virtual void TechmapPass::execute	(	std::vector< std::string >	args,
		RTLIL::Design *	design
	)

inlinevirtual

Implements Pass.

Definition at line 901 of file techmap.cc.

     {
         log_header("Executing TECHMAP pass (map to technology primitives).\n");
         log_push();
 
         TechmapWorker worker;
         simplemap_get_mappers(worker.simplemap_mappers);
 
         std::vector<std::string> map_files;
         std::string verilog_frontend = "verilog -ignore_redef";
         int max_iter = -1;
 
         size_t argidx;
         for (argidx = 1; argidx < args.size(); argidx++) {
             if (args[argidx] == "-map" && argidx+1 < args.size()) {
                 if (args[argidx+1].substr(0, 2) == "+/")
                     map_files.push_back(proc_share_dirname() + args[++argidx].substr(2));
                 else
                     map_files.push_back(args[++argidx]);
                 continue;
             }
             if (args[argidx] == "-share_map" && argidx+1 < args.size()) {
                 map_files.push_back(proc_share_dirname() + args[++argidx]);
                 continue;
             }
             if (args[argidx] == "-max_iter" && argidx+1 < args.size()) {
                 max_iter = atoi(args[++argidx].c_str());
                 continue;
             }
             if (args[argidx] == "-D" && argidx+1 < args.size()) {
                 verilog_frontend += " -D " + args[++argidx];
                 continue;
             }
             if (args[argidx] == "-I" && argidx+1 < args.size()) {
                 verilog_frontend += " -I " + args[++argidx];
                 continue;
             }
             if (args[argidx] == "-assert") {
                 worker.assert_mode = true;
                 continue;
             }
             if (args[argidx] == "-extern") {
                 worker.extern_mode = true;
                 continue;
             }
             if (args[argidx] == "-recursive") {
                 worker.recursive_mode = true;
                 continue;
             }
             if (args[argidx] == "-autoproc") {
                 worker.autoproc_mode = true;
                 continue;
             }
             break;
         }
         extra_args(args, argidx, design);
 
         RTLIL::Design *map = new RTLIL::Design;
         if (map_files.empty()) {
             std::istringstream f(stdcells_code);
             Frontend::frontend_call(map, &f, "<techmap.v>", verilog_frontend);
         } else
             for (auto &fn : map_files)
                 if (fn.substr(0, 1) == "%") {
                     if (!saved_designs.count(fn.substr(1))) {
                         delete map;
                         log_cmd_error("Can't saved design `%s'.\n", fn.c_str()+1);
                     }
                     for (auto mod : saved_designs.at(fn.substr(1))->modules())
                         if (!map->has(mod->name))
                             map->add(mod->clone());
                 } else {
                     std::ifstream f;
                     f.open(fn.c_str());
                     if (f.fail())
                         log_cmd_error("Can't open map file `%s'\n", fn.c_str());
                     Frontend::frontend_call(map, &f, fn, (fn.size() > 3 && fn.substr(fn.size()-3) == ".il") ? "ilang" : verilog_frontend);
                 }
 
         std::map<RTLIL::IdString, RTLIL::Module*> modules_new;
         for (auto &it : map->modules_) {
             if (it.first.substr(0, 2) == "\\$")
                 it.second->name = it.first.substr(1);
             modules_new[it.second->name] = it.second;
         }
         map->modules_.swap(modules_new);
 
         std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> celltypeMap;
         for (auto &it : map->modules_) {
             if (it.second->attributes.count("\\techmap_celltype") && !it.second->attributes.at("\\techmap_celltype").bits.empty()) {
                 char *p = strdup(it.second->attributes.at("\\techmap_celltype").decode_string().c_str());
                 for (char *q = strtok(p, " \t\r\n"); q; q = strtok(NULL, " \t\r\n"))
                     celltypeMap[RTLIL::escape_id(q)].insert(it.first);
                 free(p);
             } else
                 celltypeMap[it.first].insert(it.first);
         }
 
         for (auto module : design->modules())
             worker.module_queue.insert(module);
 
         while (!worker.module_queue.empty())
         {
             RTLIL::Module *module = *worker.module_queue.begin();
             worker.module_queue.erase(module);
 
             bool did_something = true;
             std::set<RTLIL::Cell*> handled_cells;
             while (did_something) {
                 did_something = false;
                     if (worker.techmap_module(design, module, map, handled_cells, celltypeMap, false))
                         did_something = true;
                 if (did_something)
                     module->check();
                 if (max_iter > 0 && --max_iter == 0)
                     break;
             }
         }
 
         log("No more expansions possible.\n");
         delete map;
 
         log_pop();
     }

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void Pass::extra_args	(	std::vector< std::string >	args,
		size_t	argidx,
		RTLIL::Design *	design,
		bool	select = `true`
	)

inherited

Definition at line 128 of file register.cc.

 {
     for (; argidx < args.size(); argidx++)
     {
         std::string arg = args[argidx];
 
         if (arg.substr(0, 1) == "-")
             cmd_error(args, argidx, "Unknown option or option in arguments.");
 
         if (!select)
             cmd_error(args, argidx, "Extra argument.");
 
         handle_extra_select_args(this, args, argidx, args.size(), design);
         break;
     }
     // cmd_log_args(args);
 }

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virtual void TechmapPass::help ( )

inlinevirtual

Reimplemented from Pass.

Definition at line 765 of file techmap.cc.

     {
         //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
         log("\n");
         log("    techmap [-map filename] [selection]\n");
         log("\n");
         log("This pass implements a very simple technology mapper that replaces cells in\n");
         log("the design with implementations given in form of a verilog or ilang source\n");
         log("file.\n");
         log("\n");
         log("    -map filename\n");
         log("        the library of cell implementations to be used.\n");
         log("        without this parameter a builtin library is used that\n");
         log("        transforms the internal RTL cells to the internal gate\n");
         log("        library.\n");
         log("\n");
         log("    -map %%<design-name>\n");
         log("        like -map above, but with an in-memory design instead of a file.\n");
         log("\n");
         log("    -share_map filename\n");
         log("        like -map, but look for the file in the share directory (where the\n");
         log("        yosys data files are). this is mainly used internally when techmap\n");
         log("        is called from other commands.\n");
         log("\n");
         log("    -extern\n");
         log("        load the cell implementations as separate modules into the design\n");
         log("        instead of inlining them.\n");
         log("\n");
         log("    -max_iter <number>\n");
         log("        only run the specified number of iterations.\n");
         log("\n");
         log("    -recursive\n");
         log("        instead of the iterative breadth-first algorithm use a recursive\n");
         log("        depth-first algorithm. both methods should yield equivialent results,\n");
         log("        but may differ in performance.\n");
         log("\n");
         log("    -autoproc\n");
         log("        Automatically call \"proc\" on implementations that contain processes.\n");
         log("\n");
         log("    -assert\n");
         log("        this option will cause techmap to exit with an error if it can't map\n");
         log("        a selected cell. only cell types that end on an underscore are accepted\n");
         log("        as final cell types by this mode.\n");
         log("\n");
         log("    -D <define>, -I <incdir>\n");
         log("        this options are passed as-is to the verilog frontend for loading the\n");
         log("        map file. Note that the verilog frontend is also called with the\n");
         log("        '-ignore_redef' option set.\n");
         log("\n");
         log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n");
         log("match cells with a type that match the text value of this attribute. Otherwise\n");
         log("the module name will be used to match the cell.\n");
         log("\n");
         log("When a module in the map file has the 'techmap_simplemap' attribute set, techmap\n");
         log("will use 'simplemap' (see 'help simplemap') to map cells matching the module.\n");
         log("\n");
         log("When a module in the map file has the 'techmap_maccmap' attribute set, techmap\n");
         log("will use 'maccmap' (see 'help maccmap') to map cells matching the module.\n");
         log("\n");
         log("When a module in the map file has the 'techmap_wrap' attribute set, techmap\n");
         log("will create a wrapper for the cell and then run the command string that the\n");
         log("attribute is set to on the wrapper module.\n");
         log("\n");
         log("All wires in the modules from the map file matching the pattern _TECHMAP_*\n");
         log("or *._TECHMAP_* are special wires that are used to pass instructions from\n");
         log("the mapping module to the techmap command. At the moment the following special\n");
         log("wires are supported:\n");
         log("\n");
         log("    _TECHMAP_FAIL_\n");
         log("        When this wire is set to a non-zero constant value, techmap will not\n");
         log("        use this module and instead try the next module with a matching\n");
         log("        'techmap_celltype' attribute.\n");
         log("\n");
         log("        When such a wire exists but does not have a constant value after all\n");
         log("        _TECHMAP_DO_* commands have been executed, an error is generated.\n");
         log("\n");
         log("    _TECHMAP_DO_*\n");
         log("        This wires are evaluated in alphabetical order. The constant text value\n");
         log("        of this wire is a yosys command (or sequence of commands) that is run\n");
         log("        by techmap on the module. A common use case is to run 'proc' on modules\n");
         log("        that are written using always-statements.\n");
         log("\n");
         log("        When such a wire has a non-constant value at the time it is to be\n");
         log("        evaluated, an error is produced. That means it is possible for such a\n");
         log("        wire to start out as non-constant and evaluate to a constant value\n");
         log("        during processing of other _TECHMAP_DO_* commands.\n");
         log("\n");
         log("        A _TECHMAP_DO_* command may start with the special token 'CONSTMAP; '.\n");
         log("        in this case techmap will create a copy for each distinct configuration\n");
         log("        of constant inputs and shorted inputs at this point and import the\n");
         log("        constant and connected bits into the map module. All further commands\n");
         log("        are executed in this copy. This is a very convenient way of creating\n");
         log("        optimizied specializations of techmap modules without using the special\n");
         log("        parameters described below.\n");
         log("\n");
         log("        A _TECHMAP_DO_* command may start with the special token 'RECURSION; '.\n");
         log("        then techmap will recursively replace the cells in the module with their\n");
         log("        implementation. This is not affected by the -max_iter option.\n");
         log("\n");
         log("        It is possible to combine both prefixes to 'RECURSION; CONSTMAP; '.\n");
         log("\n");
         log("In addition to this special wires, techmap also supports special parameters in\n");
         log("modules in the map file:\n");
         log("\n");
         log("    _TECHMAP_CELLTYPE_\n");
         log("        When a parameter with this name exists, it will be set to the type name\n");
         log("        of the cell that matches the module.\n");
         log("\n");
         log("    _TECHMAP_CONSTMSK_<port-name>_\n");
         log("    _TECHMAP_CONSTVAL_<port-name>_\n");
         log("        When this pair of parameters is available in a module for a port, then\n");
         log("        former has a 1-bit for each constant input bit and the latter has the\n");
         log("        value for this bit. The unused bits of the latter are set to undef (x).\n");
         log("\n");
         log("    _TECHMAP_BITS_CONNMAP_\n");
         log("    _TECHMAP_CONNMAP_<port-name>_\n");
         log("        For an N-bit port, the _TECHMAP_CONNMAP_<port-name>_ parameter, if it\n");
         log("        exists, will be set to an N*_TECHMAP_BITS_CONNMAP_ bit vector containing\n");
         log("        N words (of _TECHMAP_BITS_CONNMAP_ bits each) that assign each single\n");
         log("        bit driver a unique id. The values 0-3 are reserved for 0, 1, x, and z.\n");
         log("        This can be used to detect shorted inputs.\n");
         log("\n");
         log("When a module in the map file has a parameter where the according cell in the\n");
         log("design has a port, the module from the map file is only used if the port in\n");
         log("the design is connected to a constant value. The parameter is then set to the\n");
         log("constant value.\n");
         log("\n");
         log("A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name\n");
         log("of the cell that is beeing replaced.\n");
         log("\n");
         log("See 'help extract' for a pass that does the opposite thing.\n");
         log("\n");
         log("See 'help flatten' for a pass that does flatten the design (which is\n");
         log("esentially techmap but using the design itself as map library).\n");
         log("\n");
     }

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void Pass::init_register ( )

staticinherited

Definition at line 54 of file register.cc.

 {
     while (first_queued_pass) {
         first_queued_pass->run_register();
         first_queued_pass = first_queued_pass->next_queued_pass;
     }
 }

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void Pass::post_execute ( Pass::pre_post_exec_state_t state )

inherited

Definition at line 84 of file register.cc.

 {
     int64_t time_ns = PerformanceTimer::query() - state.begin_ns;
     runtime_ns += time_ns;
     current_pass = state.parent_pass;
     if (current_pass)
         current_pass->runtime_ns -= time_ns;
 }

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Pass::pre_post_exec_state_t Pass::pre_execute ( )

inherited

Definition at line 74 of file register.cc.

 {
     pre_post_exec_state_t state;
     call_counter++;
     state.begin_ns = PerformanceTimer::query();
     state.parent_pass = current_pass;
     current_pass = this;
     return state;
 }

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void Pass::run_register ( )

virtualinherited

Reimplemented in Backend, and Frontend.

Definition at line 48 of file register.cc.

 {
     log_assert(pass_register.count(pass_name) == 0);
     pass_register[pass_name] = this;
 }

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Field Documentation

int Pass::call_counter

inherited

Definition at line 36 of file register.h.

Pass* Pass::next_queued_pass

inherited

Definition at line 60 of file register.h.

std::string Pass::pass_name

inherited

Definition at line 29 of file register.h.

int64_t Pass::runtime_ns

inherited

Definition at line 37 of file register.h.

std::string Pass::short_help

inherited

Definition at line 29 of file register.h.

The documentation for this struct was generated from the following file:

techmap.cc

Public Member Functions

Static Public Member Functions

Data Fields

Detailed Description

Constructor & Destructor Documentation

Member Function Documentation

Field Documentation