#include "kernel/yosys.h"
#include "kernel/celltypes.h"
#include "kernel/sigtools.h"
#include <string.h>
#include <errno.h>

Include dependency graph for select.cc:

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Data Structures
struct	SelectPass

struct	CdPass

struct	LsPass

Macros
#define	LOG_OBJECT(...) { if (list_mode) log(__VA_ARGS__); if (f != NULL) fprintf(f, __VA_ARGS__); total_count++; }

Functions
static bool	match_ids (RTLIL::IdString id, std::string pattern)

static bool	match_attr_val (const RTLIL::Const &value, std::string pattern, char match_op)

static bool	match_attr (const std::map< RTLIL::IdString, RTLIL::Const > &attributes, std::string name_pat, std::string value_pat, char match_op)

static bool	match_attr (const std::map< RTLIL::IdString, RTLIL::Const > &attributes, std::string match_expr)

static void	select_op_neg (RTLIL::Design *design, RTLIL::Selection &lhs)

static void	select_op_submod (RTLIL::Design *design, RTLIL::Selection &lhs)

static void	select_op_fullmod (RTLIL::Design *design, RTLIL::Selection &lhs)

static void	select_op_alias (RTLIL::Design *design, RTLIL::Selection &lhs)

static void	select_op_union (RTLIL::Design *, RTLIL::Selection &lhs, const RTLIL::Selection &rhs)

static void	select_op_diff (RTLIL::Design *design, RTLIL::Selection &lhs, const RTLIL::Selection &rhs)

static void	select_op_intersect (RTLIL::Design *design, RTLIL::Selection &lhs, const RTLIL::Selection &rhs)

static int	parse_comma_list (std::set< RTLIL::IdString > &tokens, std::string str, size_t pos, std::string stopchar)

static int	select_op_expand (RTLIL::Design *design, RTLIL::Selection &lhs, std::vector< expand_rule_t > &rules, std::set< RTLIL::IdString > &limits, int max_objects, char mode, CellTypes &ct)

static void	select_op_expand (RTLIL::Design *design, std::string arg, char mode)

static void	select_filter_active_mod (RTLIL::Design *design, RTLIL::Selection &sel)

static void	select_stmt (RTLIL::Design *design, std::string arg)

PRIVATE_NAMESPACE_END YOSYS_NAMESPACE_BEGIN void	handle_extra_select_args (Pass pass, std::vector< std::string > args, size_t argidx, size_t args_size, RTLIL::Design design)

template<typename T >
static int	log_matches (const char *title, std::string pattern, T list)

Variables
static std::vector < RTLIL::Selection >	work_stack

SelectPass	SelectPass

CdPass	CdPass

LsPass	LsPass

Macro Definition Documentation

#define LOG_OBJECT ( ... ) { if (list_mode) log(__VA_ARGS__); if (f != NULL) fprintf(f, __VA_ARGS__); total_count++; }

Function Documentation

PRIVATE_NAMESPACE_END YOSYS_NAMESPACE_BEGIN void handle_extra_select_args	(	Pass *	pass,
		std::vector< std::string >	args,
		size_t	argidx,
		size_t	args_size,
		RTLIL::Design *	design
	)

Definition at line 803 of file select.cc.

 {
     work_stack.clear();
     for (; argidx < args_size; argidx++) {
         if (args[argidx].substr(0, 1) == "-") {
             if (pass != NULL)
                 pass->cmd_error(args, argidx, "Unexpected option in selection arguments.");
             else
                 log_cmd_error("Unexpected option in selection arguments.");
         }
         select_stmt(design, args[argidx]);
     }
     while (work_stack.size() > 1) {
         select_op_union(design, work_stack.front(), work_stack.back());
         work_stack.pop_back();
     }
     if (work_stack.size() > 0)
         design->selection_stack.push_back(work_stack.back());
     else
         design->selection_stack.push_back(RTLIL::Selection(false));
 }

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template<typename T >

static int log_matches	(	const char *	title,
		std::string	pattern,
		T	list
	)

static

Definition at line 1330 of file select.cc.

 {
     std::vector<RTLIL::IdString> matches;
 
     for (auto &it : list)
         if (pattern.empty() || match_ids(it.first, pattern))
             matches.push_back(it.first);
 
     if (matches.empty())
         return 0;
 
     log("\n%d %s:\n", int(matches.size()), title);
     for (auto &id : matches)
         log("  %s\n", RTLIL::id2cstr(id));
     return matches.size();
 }

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static bool match_attr	(	const std::map< RTLIL::IdString, RTLIL::Const > &	attributes,
		std::string	name_pat,
		std::string	value_pat,
		char	match_op
	)

static

Definition at line 104 of file select.cc.

 {
     if (name_pat.find('*') != std::string::npos || name_pat.find('?') != std::string::npos || name_pat.find('[') != std::string::npos) {
         for (auto &it : attributes) {
             if (patmatch(name_pat.c_str(), it.first.c_str()) && match_attr_val(it.second, value_pat, match_op))
                 return true;
             if (it.first.size() > 0 && it.first[0] == '\\' && patmatch(name_pat.c_str(), it.first.substr(1).c_str()) && match_attr_val(it.second, value_pat, match_op))
                 return true;
         }
     } else {
         if (name_pat.size() > 0 && (name_pat[0] == '\\' || name_pat[0] == '$') && attributes.count(name_pat) && match_attr_val(attributes.at(name_pat), value_pat, match_op))
             return true;
         if (attributes.count("\\" + name_pat) && match_attr_val(attributes.at("\\" + name_pat), value_pat, match_op))
             return true;
     }
     return false;
 }

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static bool match_attr	(	const std::map< RTLIL::IdString, RTLIL::Const > &	attributes,
		std::string	match_expr
	)

static

Definition at line 122 of file select.cc.

 {
     size_t pos = match_expr.find_first_of("<!=>");
 
     if (pos != std::string::npos) {
         if (match_expr.substr(pos, 2) == "!=")
             return match_attr(attributes, match_expr.substr(0, pos), match_expr.substr(pos+2), '!');
         if (match_expr.substr(pos, 2) == "<=")
             return match_attr(attributes, match_expr.substr(0, pos), match_expr.substr(pos+2), '[');
         if (match_expr.substr(pos, 2) == ">=")
             return match_attr(attributes, match_expr.substr(0, pos), match_expr.substr(pos+2), ']');
         return match_attr(attributes, match_expr.substr(0, pos), match_expr.substr(pos+1), match_expr[pos]);
     }
 
     return match_attr(attributes, match_expr, std::string(), 0);
 }

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static bool match_attr_val	(	const RTLIL::Const &	value,
		std::string	pattern,
		char	match_op
	)

static

Definition at line 52 of file select.cc.

 {
     if (match_op == 0)
         return true;
 
     if ((value.flags & RTLIL::CONST_FLAG_STRING) == 0)
     {
         RTLIL::SigSpec sig_value;
 
         if (!RTLIL::SigSpec::parse(sig_value, NULL, pattern))
             return false;
 
         RTLIL::Const pattern_value = sig_value.as_const();
 
         if (match_op == '=')
             return value == pattern_value;
         if (match_op == '!')
             return value != pattern_value;
         if (match_op == '<')
             return value.as_int() < pattern_value.as_int();
         if (match_op == '>')
             return value.as_int() > pattern_value.as_int();
         if (match_op == '[')
             return value.as_int() <= pattern_value.as_int();
         if (match_op == ']')
             return value.as_int() >= pattern_value.as_int();
     }
     else
     {
         std::string value_str = value.decode_string();
 
         if (match_op == '=')
             if (patmatch(pattern.c_str(), value.decode_string().c_str()))
                 return true;
 
         if (match_op == '=')
             return value_str == pattern;
         if (match_op == '!')
             return value_str != pattern;
         if (match_op == '<')
             return value_str < pattern;
         if (match_op == '>')
             return value_str > pattern;
         if (match_op == '[')
             return value_str <= pattern;
         if (match_op == ']')
             return value_str >= pattern;
     }
 
     log_abort();
 }

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static bool match_ids	(	RTLIL::IdString	id,
		std::string	pattern
	)

static

Definition at line 33 of file select.cc.

 {
     if (id == pattern)
         return true;
     if (id.size() > 0 && id[0] == '\\' && id.substr(1) == pattern)
         return true;
     if (patmatch(pattern.c_str(), id.c_str()))
         return true;
     if (id.size() > 0 && id[0] == '\\' && patmatch(pattern.c_str(), id.substr(1).c_str()))
         return true;
     if (id.size() > 0 && id[0] == '$' && pattern.size() > 0 && pattern[0] == '$') {
         const char *p = id.c_str();
         const char *q = strrchr(p, '$');
         if (pattern == q)
             return true;
     }
     return false;
 }

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static int parse_comma_list	(	std::set< RTLIL::IdString > &	tokens,
		std::string	str,
		size_t	pos,
		std::string	stopchar
	)

static

Definition at line 352 of file select.cc.

 {
     stopchar += ',';
     while (1) {
         size_t endpos = str.find_first_of(stopchar, pos);
         if (endpos == std::string::npos)
             endpos = str.size();
         if (endpos != pos)
             tokens.insert(RTLIL::escape_id(str.substr(pos, endpos-pos)));
         pos = endpos;
         if (pos == str.size() || str[pos] != ',')
             return pos;
         pos++;
     }
 }

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static void select_filter_active_mod	(	RTLIL::Design *	design,
		RTLIL::Selection &	sel
	)

static

Definition at line 538 of file select.cc.

 {
     if (design->selected_active_module.empty())
         return;
     
     if (sel.full_selection) {
         sel.full_selection = false;
         sel.selected_modules.clear();
         sel.selected_members.clear();
         sel.selected_modules.insert(design->selected_active_module);
         return;
     }
 
     std::vector<RTLIL::IdString> del_list;
     for (auto mod_name : sel.selected_modules)
         if (mod_name != design->selected_active_module)
             del_list.push_back(mod_name);
     for (auto &it : sel.selected_members)
         if (it.first != design->selected_active_module)
             del_list.push_back(it.first);
     for (auto mod_name : del_list) {
         sel.selected_modules.erase(mod_name);
         sel.selected_members.erase(mod_name);
     }
 }

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static void select_op_alias	(	RTLIL::Design *	design,
		RTLIL::Selection &	lhs
	)

static

Definition at line 207 of file select.cc.

 {
     for (auto &mod_it : design->modules_)
     {
         if (lhs.selected_whole_module(mod_it.first))
             continue;
         if (!lhs.selected_module(mod_it.first))
             continue;
 
         SigMap sigmap(mod_it.second);
         SigPool selected_bits;
 
         for (auto &it : mod_it.second->wires_)
             if (lhs.selected_member(mod_it.first, it.first))
                 selected_bits.add(sigmap(it.second));
 
         for (auto &it : mod_it.second->wires_)
             if (!lhs.selected_member(mod_it.first, it.first) && selected_bits.check_any(sigmap(it.second)))
                 lhs.selected_members[mod_it.first].insert(it.first);
     }
 }

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static void select_op_diff	(	RTLIL::Design *	design,
		RTLIL::Selection &	lhs,
		const RTLIL::Selection &	rhs
	)

static

Definition at line 251 of file select.cc.

 {
     if (rhs.full_selection) {
         lhs.full_selection = false;
         lhs.selected_modules.clear();
         lhs.selected_members.clear();
         return;
     }
 
     if (lhs.full_selection) {
         if (!rhs.full_selection && rhs.selected_modules.size() == 0 && rhs.selected_members.size() == 0)
             return;
         lhs.full_selection = false;
         for (auto &it : design->modules_)
             lhs.selected_modules.insert(it.first);
     }
 
     for (auto &it : rhs.selected_modules) {
         lhs.selected_modules.erase(it);
         lhs.selected_members.erase(it);
     }
 
     for (auto &it : rhs.selected_members)
     {
         if (design->modules_.count(it.first) == 0)
             continue;
 
         RTLIL::Module *mod = design->modules_[it.first];
 
         if (lhs.selected_modules.count(mod->name) > 0)
         {
             for (auto &it : mod->wires_)
                 lhs.selected_members[mod->name].insert(it.first);
             for (auto &it : mod->memories)
                 lhs.selected_members[mod->name].insert(it.first);
             for (auto &it : mod->cells_)
                 lhs.selected_members[mod->name].insert(it.first);
             for (auto &it : mod->processes)
                 lhs.selected_members[mod->name].insert(it.first);
             lhs.selected_modules.erase(mod->name);
         }
 
         if (lhs.selected_members.count(mod->name) == 0)
             continue;
 
         for (auto &it2 : it.second)
             lhs.selected_members[mod->name].erase(it2);
     }
 }

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static int select_op_expand	(	RTLIL::Design *	design,
		RTLIL::Selection &	lhs,
		std::vector< expand_rule_t > &	rules,
		std::set< RTLIL::IdString > &	limits,
		int	max_objects,
		char	mode,
		CellTypes &	ct
	)

static

Definition at line 368 of file select.cc.

 {
     int sel_objects = 0;
     bool is_input, is_output;
     for (auto &mod_it : design->modules_)
     {
         if (lhs.selected_whole_module(mod_it.first) || !lhs.selected_module(mod_it.first))
             continue;
 
         RTLIL::Module *mod = mod_it.second;
         std::set<RTLIL::Wire*> selected_wires;
 
         for (auto &it : mod->wires_)
             if (lhs.selected_member(mod_it.first, it.first) && limits.count(it.first) == 0)
                 selected_wires.insert(it.second);
 
         for (auto &conn : mod->connections())
         {
             std::vector<RTLIL::SigBit> conn_lhs = conn.first.to_sigbit_vector();
             std::vector<RTLIL::SigBit> conn_rhs = conn.second.to_sigbit_vector();
 
             for (size_t i = 0; i < conn_lhs.size(); i++) {
                 if (conn_lhs[i].wire == NULL || conn_rhs[i].wire == NULL)
                     continue;
                 if (mode != 'i' && selected_wires.count(conn_rhs[i].wire) && lhs.selected_members[mod->name].count(conn_lhs[i].wire->name) == 0)
                     lhs.selected_members[mod->name].insert(conn_lhs[i].wire->name), sel_objects++, max_objects--;
                 if (mode != 'o' && selected_wires.count(conn_lhs[i].wire) && lhs.selected_members[mod->name].count(conn_rhs[i].wire->name) == 0)
                     lhs.selected_members[mod->name].insert(conn_rhs[i].wire->name), sel_objects++, max_objects--;
             }
         }
 
         for (auto &cell : mod->cells_)
         for (auto &conn : cell.second->connections())
         {
             char last_mode = '-';
             for (auto &rule : rules) {
                 last_mode = rule.mode;
                 if (rule.cell_types.size() > 0 && rule.cell_types.count(cell.second->type) == 0)
                     continue;
                 if (rule.port_names.size() > 0 && rule.port_names.count(conn.first) == 0)
                     continue;
                 if (rule.mode == '+')
                     goto include_match;
                 else
                     goto exclude_match;
             }
             if (last_mode == '+')
                 goto exclude_match;
         include_match:
             is_input = mode == 'x' || ct.cell_input(cell.second->type, conn.first);
             is_output = mode == 'x' || ct.cell_output(cell.second->type, conn.first);
             for (auto &chunk : conn.second.chunks())
                 if (chunk.wire != NULL) {
                     if (max_objects != 0 && selected_wires.count(chunk.wire) > 0 && lhs.selected_members[mod->name].count(cell.first) == 0)
                         if (mode == 'x' || (mode == 'i' && is_output) || (mode == 'o' && is_input))
                             lhs.selected_members[mod->name].insert(cell.first), sel_objects++, max_objects--;
                     if (max_objects != 0 && lhs.selected_members[mod->name].count(cell.first) > 0 && limits.count(cell.first) == 0 && lhs.selected_members[mod->name].count(chunk.wire->name) == 0)
                         if (mode == 'x' || (mode == 'i' && is_input) || (mode == 'o' && is_output))
                             lhs.selected_members[mod->name].insert(chunk.wire->name), sel_objects++, max_objects--;
                 }
         exclude_match:;
         }
     }
 
     return sel_objects;
 }

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static void select_op_expand	(	RTLIL::Design *	design,
		std::string	arg,
		char	mode
	)

static

Definition at line 435 of file select.cc.

 {
     int pos = mode == 'x' ? 2 : 3, levels = 1, rem_objects = -1;
     std::vector<expand_rule_t> rules;
     std::set<RTLIL::IdString> limits;
 
     CellTypes ct;
 
     if (mode != 'x')
         ct.setup(design);
 
     if (pos < int(arg.size()) && arg[pos] == '*') {
         levels = 1000000;
         pos++;
     } else
     if (pos < int(arg.size()) && '0' <= arg[pos] && arg[pos] <= '9') {
         size_t endpos = arg.find_first_not_of("0123456789", pos);
         if (endpos == std::string::npos)
             endpos = arg.size();
         levels = atoi(arg.substr(pos, endpos-pos).c_str());
         pos = endpos;
     }
 
     if (pos < int(arg.size()) && arg[pos] == '.') {
         size_t endpos = arg.find_first_not_of("0123456789", ++pos);
         if (endpos == std::string::npos)
             endpos = arg.size();
         if (int(endpos) > pos)
             rem_objects = atoi(arg.substr(pos, endpos-pos).c_str());
         pos = endpos;
     }
 
     while (pos < int(arg.size())) {
         if (arg[pos] != ':' || pos+1 == int(arg.size()))
             log_cmd_error("Syntax error in expand operator '%s'.\n", arg.c_str());
         pos++;
         if (arg[pos] == '+' || arg[pos] == '-') {
             expand_rule_t rule;
             rule.mode = arg[pos++];
             pos = parse_comma_list(rule.cell_types, arg, pos, "[:");
             if (pos < int(arg.size()) && arg[pos] == '[') {
                 pos = parse_comma_list(rule.port_names, arg, pos+1, "]:");
                 if (pos < int(arg.size()) && arg[pos] == ']')
                     pos++;
             }
             rules.push_back(rule);
         } else {
             size_t endpos = arg.find(':', pos);
             if (endpos == std::string::npos)
                 endpos = arg.size();
             if (int(endpos) > pos) {
                 std::string str = arg.substr(pos, endpos-pos);
                 if (str[0] == '@') {
                     str = RTLIL::escape_id(str.substr(1));
                     if (design->selection_vars.count(str) > 0) {
                         for (auto i1 : design->selection_vars.at(str).selected_members)
                         for (auto i2 : i1.second)
                             limits.insert(i2);
                     } else
                         log_cmd_error("Selection %s is not defined!\n", RTLIL::unescape_id(str).c_str());
                 } else
                     limits.insert(RTLIL::escape_id(str));
             }
             pos = endpos;
         }
     }
 
 #if 0
     log("expand by %d levels (max. %d objects):\n", levels, rem_objects);
     for (auto &rule : rules) {
         log("  rule (%c):\n", rule.mode);
         if (rule.cell_types.size() > 0) {
             log("    cell types:");
             for (auto &it : rule.cell_types)
                 log(" %s", it.c_str());
             log("\n");
         }
         if (rule.port_names.size() > 0) {
             log("    port names:");
             for (auto &it : rule.port_names)
                 log(" %s", it.c_str());
             log("\n");
         }
     }
     if (limits.size() > 0) {
         log("  limits:");
         for (auto &it : limits)
             log(" %s", it.c_str());
         log("\n");
     }
 #endif
 
     while (levels-- > 0 && rem_objects != 0) {
         int num_objects = select_op_expand(design, work_stack.back(), rules, limits, rem_objects, mode, ct);
         if (num_objects == 0)
             break;
         rem_objects -= num_objects;
     }
 
     if (rem_objects == 0)
         log_warning("reached configured limit at `%s'.\n", arg.c_str());
 }

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static void select_op_fullmod	(	RTLIL::Design *	design,
		RTLIL::Selection &	lhs
	)

static

Definition at line 199 of file select.cc.

 {
     lhs.optimize(design);
     for (auto &it : lhs.selected_members)
         lhs.selected_modules.insert(it.first);
     lhs.selected_members.clear();
 }

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static void select_op_intersect	(	RTLIL::Design *	design,
		RTLIL::Selection &	lhs,
		const RTLIL::Selection &	rhs
	)

static

Definition at line 301 of file select.cc.

 {
     if (rhs.full_selection)
         return;
 
     if (lhs.full_selection) {
         lhs.full_selection = false;
         for (auto &it : design->modules_)
             lhs.selected_modules.insert(it.first);
     }
 
     std::vector<RTLIL::IdString> del_list;
 
     for (auto &it : lhs.selected_modules)
         if (rhs.selected_modules.count(it) == 0) {
             if (rhs.selected_members.count(it) > 0)
                 for (auto &it2 : rhs.selected_members.at(it))
                     lhs.selected_members[it].insert(it2);
             del_list.push_back(it);
         }
     for (auto &it : del_list)
         lhs.selected_modules.erase(it);
 
     del_list.clear();
     for (auto &it : lhs.selected_members) {
         if (rhs.selected_modules.count(it.first) > 0)
             continue;
         if (rhs.selected_members.count(it.first) == 0) {
             del_list.push_back(it.first);
             continue;
         }
         std::vector<RTLIL::IdString> del_list2;
         for (auto &it2 : it.second)
             if (rhs.selected_members.at(it.first).count(it2) == 0)
                 del_list2.push_back(it2);
         for (auto &it2 : del_list2)
             it.second.erase(it2);
         if (it.second.size() == 0)
             del_list.push_back(it.first);
     }
     for (auto &it : del_list)
         lhs.selected_members.erase(it);
 }

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static void select_op_neg	(	RTLIL::Design *	design,
		RTLIL::Selection &	lhs
	)

static

Definition at line 139 of file select.cc.

 {
     if (lhs.full_selection) {
         lhs.full_selection = false;
         lhs.selected_modules.clear();
         lhs.selected_members.clear();
         return;
     }
 
     if (lhs.selected_modules.size() == 0 && lhs.selected_members.size() == 0) {
         lhs.full_selection = true;
         return;
     }
 
     RTLIL::Selection new_sel(false);
 
     for (auto &mod_it : design->modules_)
     {
         if (lhs.selected_whole_module(mod_it.first))
             continue;
         if (!lhs.selected_module(mod_it.first)) {
             new_sel.selected_modules.insert(mod_it.first);
             continue;
         }
 
         RTLIL::Module *mod = mod_it.second;
         for (auto &it : mod->wires_)
             if (!lhs.selected_member(mod_it.first, it.first))
                 new_sel.selected_members[mod->name].insert(it.first);
         for (auto &it : mod->memories)
             if (!lhs.selected_member(mod_it.first, it.first))
                 new_sel.selected_members[mod->name].insert(it.first);
         for (auto &it : mod->cells_)
             if (!lhs.selected_member(mod_it.first, it.first))
                 new_sel.selected_members[mod->name].insert(it.first);
         for (auto &it : mod->processes)
             if (!lhs.selected_member(mod_it.first, it.first))
                 new_sel.selected_members[mod->name].insert(it.first);
     }
 
     lhs.selected_modules.swap(new_sel.selected_modules);
     lhs.selected_members.swap(new_sel.selected_members);
 }

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static void select_op_submod	(	RTLIL::Design *	design,
		RTLIL::Selection &	lhs
	)

static

Definition at line 183 of file select.cc.

 {
     for (auto &mod_it : design->modules_)
     {
         if (lhs.selected_whole_module(mod_it.first))
         {
             for (auto &cell_it : mod_it.second->cells_)
             {
                 if (design->modules_.count(cell_it.second->type) == 0)
                     continue;
                 lhs.selected_modules.insert(cell_it.second->type);
             }
         }
     }
 }

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static void select_op_union	(	RTLIL::Design *	,
		RTLIL::Selection &	lhs,
		const RTLIL::Selection &	rhs
	)

static

Definition at line 229 of file select.cc.

 {
     if (rhs.full_selection) {
         lhs.full_selection = true;
         lhs.selected_modules.clear();
         lhs.selected_members.clear();
         return;
     }
 
     if (lhs.full_selection)
         return;
 
     for (auto &it : rhs.selected_members)
         for (auto &it2 : it.second)
             lhs.selected_members[it.first].insert(it2);
 
     for (auto &it : rhs.selected_modules) {
         lhs.selected_modules.insert(it);
         lhs.selected_members.erase(it);
     }
 }

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static void select_stmt	(	RTLIL::Design *	design,
		std::string	arg
	)

static

Definition at line 564 of file select.cc.

 {
     std::string arg_mod, arg_memb;
 
     if (arg.size() == 0)
         return;
 
     if (arg[0] == '%') {
         if (arg == "%") {
             if (design->selection_stack.size() > 0)
                 work_stack.push_back(design->selection_stack.back());
         } else
         if (arg == "%%") {
             while (work_stack.size() > 1) {
                 select_op_union(design, work_stack.front(), work_stack.back());
                 work_stack.pop_back();
             }
         } else
         if (arg == "%n") {
             if (work_stack.size() < 1)
                 log_cmd_error("Must have at least one element on the stack for operator %%n.\n");
             select_op_neg(design, work_stack[work_stack.size()-1]);
         } else
         if (arg == "%u") {
             if (work_stack.size() < 2)
                 log_cmd_error("Must have at least two elements on the stack for operator %%u.\n");
             select_op_union(design, work_stack[work_stack.size()-2], work_stack[work_stack.size()-1]);
             work_stack.pop_back();
         } else
         if (arg == "%d") {
             if (work_stack.size() < 2)
                 log_cmd_error("Must have at least two elements on the stack for operator %%d.\n");
             select_op_diff(design, work_stack[work_stack.size()-2], work_stack[work_stack.size()-1]);
             work_stack.pop_back();
         } else
         if (arg == "%D") {
             if (work_stack.size() < 2)
                 log_cmd_error("Must have at least two elements on the stack for operator %%d.\n");
             select_op_diff(design, work_stack[work_stack.size()-1], work_stack[work_stack.size()-2]);
             work_stack[work_stack.size()-2] = work_stack[work_stack.size()-1];
             work_stack.pop_back();
         } else
         if (arg == "%i") {
             if (work_stack.size() < 2)
                 log_cmd_error("Must have at least two elements on the stack for operator %%i.\n");
             select_op_intersect(design, work_stack[work_stack.size()-2], work_stack[work_stack.size()-1]);
             work_stack.pop_back();
         } else
         if (arg == "%s") {
             if (work_stack.size() < 1)
                 log_cmd_error("Must have at least one element on the stack for operator %%s.\n");
             select_op_submod(design, work_stack[work_stack.size()-1]);
         } else
         if (arg == "%c") {
             if (work_stack.size() < 1)
                 log_cmd_error("Must have at least one element on the stack for operator %%c.\n");
             work_stack.push_back(work_stack.back());
         } else
         if (arg == "%m") {
             if (work_stack.size() < 1)
                 log_cmd_error("Must have at least one element on the stack for operator %%m.\n");
             select_op_fullmod(design, work_stack[work_stack.size()-1]);
         } else
         if (arg == "%a") {
             if (work_stack.size() < 1)
                 log_cmd_error("Must have at least one element on the stack for operator %%a.\n");
             select_op_alias(design, work_stack[work_stack.size()-1]);
         } else
         if (arg == "%x" || (arg.size() > 2 && arg.substr(0, 2) == "%x" && (arg[2] == ':' || arg[2] == '*' || arg[2] == '.' || ('0' <= arg[2] && arg[2] <= '9')))) {
             if (work_stack.size() < 1)
                 log_cmd_error("Must have at least one element on the stack for operator %%x.\n");
             select_op_expand(design, arg, 'x');
         } else
         if (arg == "%ci" || (arg.size() > 3 && arg.substr(0, 3) == "%ci" && (arg[3] == ':' || arg[3] == '*' || arg[3] == '.' || ('0' <= arg[3] && arg[3] <= '9')))) {
             if (work_stack.size() < 1)
                 log_cmd_error("Must have at least one element on the stack for operator %%ci.\n");
             select_op_expand(design, arg, 'i');
         } else
         if (arg == "%co" || (arg.size() > 3 && arg.substr(0, 3) == "%co" && (arg[3] == ':' || arg[3] == '*' || arg[3] == '.' || ('0' <= arg[3] && arg[3] <= '9')))) {
             if (work_stack.size() < 1)
                 log_cmd_error("Must have at least one element on the stack for operator %%co.\n");
             select_op_expand(design, arg, 'o');
         } else
             log_cmd_error("Unknown selection operator '%s'.\n", arg.c_str());
         if (work_stack.size() >= 1)
             select_filter_active_mod(design, work_stack.back());
         return;
     }
 
     if (arg[0] == '@') {
         std::string set_name = RTLIL::escape_id(arg.substr(1));
         if (design->selection_vars.count(set_name) > 0)
             work_stack.push_back(design->selection_vars[set_name]);
         else
             log_cmd_error("Selection @%s is not defined!\n", RTLIL::unescape_id(set_name).c_str());
         select_filter_active_mod(design, work_stack.back());
         return;
     }
 
     if (!design->selected_active_module.empty()) {
         arg_mod = design->selected_active_module;
         arg_memb = arg;
     } else {
         size_t pos = arg.find('/');
         if (pos == std::string::npos) {
             if (arg.find(':') == std::string::npos || arg.substr(0, 1) == "A")
                 arg_mod = arg;
             else
                 arg_mod = "*", arg_memb = arg;
         } else {
             arg_mod = arg.substr(0, pos);
             arg_memb = arg.substr(pos+1);
         }
     }
 
     work_stack.push_back(RTLIL::Selection());
     RTLIL::Selection &sel = work_stack.back();
 
     if (arg == "*" && arg_mod == "*") {
         select_filter_active_mod(design, work_stack.back());
         return;
     }
     
     sel.full_selection = false;
     for (auto &mod_it : design->modules_)
     {
         if (arg_mod.substr(0, 2) == "A:") {
             if (!match_attr(mod_it.second->attributes, arg_mod.substr(2)))
                 continue;
         } else
         if (!match_ids(mod_it.first, arg_mod))
             continue;
 
         if (arg_memb == "") {
             sel.selected_modules.insert(mod_it.first);
             continue;
         }
 
         RTLIL::Module *mod = mod_it.second;
         if (arg_memb.substr(0, 2) == "w:") {
             for (auto &it : mod->wires_)
                 if (match_ids(it.first, arg_memb.substr(2)))
                     sel.selected_members[mod->name].insert(it.first);
         } else
         if (arg_memb.substr(0, 2) == "i:") {
             for (auto &it : mod->wires_)
                 if (it.second->port_input && match_ids(it.first, arg_memb.substr(2)))
                     sel.selected_members[mod->name].insert(it.first);
         } else
         if (arg_memb.substr(0, 2) == "o:") {
             for (auto &it : mod->wires_)
                 if (it.second->port_output && match_ids(it.first, arg_memb.substr(2)))
                     sel.selected_members[mod->name].insert(it.first);
         } else
         if (arg_memb.substr(0, 2) == "x:") {
             for (auto &it : mod->wires_)
                 if ((it.second->port_input || it.second->port_output) && match_ids(it.first, arg_memb.substr(2)))
                     sel.selected_members[mod->name].insert(it.first);
         } else
         if (arg_memb.substr(0, 2) == "s:") {
             size_t delim = arg_memb.substr(2).find(':');
             if (delim == std::string::npos) {
                 int width = atoi(arg_memb.substr(2).c_str());
                 for (auto &it : mod->wires_)
                     if (it.second->width == width)
                         sel.selected_members[mod->name].insert(it.first);
             } else {
                 std::string min_str = arg_memb.substr(2, delim);
                 std::string max_str = arg_memb.substr(2+delim+1);
                 int min_width = min_str.empty() ? 0 : atoi(min_str.c_str());
                 int max_width = max_str.empty() ? -1 : atoi(max_str.c_str());
                 for (auto &it : mod->wires_)
                     if (min_width <= it.second->width && (it.second->width <= max_width || max_width == -1))
                         sel.selected_members[mod->name].insert(it.first);
             }
         } else
         if (arg_memb.substr(0, 2) == "m:") {
             for (auto &it : mod->memories)
                 if (match_ids(it.first, arg_memb.substr(2)))
                     sel.selected_members[mod->name].insert(it.first);
         } else
         if (arg_memb.substr(0, 2) == "c:") {
             for (auto &it : mod->cells_)
                 if (match_ids(it.first, arg_memb.substr(2)))
                     sel.selected_members[mod->name].insert(it.first);
         } else
         if (arg_memb.substr(0, 2) == "t:") {
             for (auto &it : mod->cells_)
                 if (match_ids(it.second->type, arg_memb.substr(2)))
                     sel.selected_members[mod->name].insert(it.first);
         } else
         if (arg_memb.substr(0, 2) == "p:") {
             for (auto &it : mod->processes)
                 if (match_ids(it.first, arg_memb.substr(2)))
                     sel.selected_members[mod->name].insert(it.first);
         } else
         if (arg_memb.substr(0, 2) == "a:") {
             for (auto &it : mod->wires_)
                 if (match_attr(it.second->attributes, arg_memb.substr(2)))
                     sel.selected_members[mod->name].insert(it.first);
             for (auto &it : mod->memories)
                 if (match_attr(it.second->attributes, arg_memb.substr(2)))
                     sel.selected_members[mod->name].insert(it.first);
             for (auto &it : mod->cells_)
                 if (match_attr(it.second->attributes, arg_memb.substr(2)))
                     sel.selected_members[mod->name].insert(it.first);
             for (auto &it : mod->processes)
                 if (match_attr(it.second->attributes, arg_memb.substr(2)))
                     sel.selected_members[mod->name].insert(it.first);
         } else
         if (arg_memb.substr(0, 2) == "r:") {
             for (auto &it : mod->cells_)
                 if (match_attr(it.second->parameters, arg_memb.substr(2)))
                     sel.selected_members[mod->name].insert(it.first);
         } else {
             if (arg_memb.substr(0, 2) == "n:")
                 arg_memb = arg_memb.substr(2);
             for (auto &it : mod->wires_)
                 if (match_ids(it.first, arg_memb))
                     sel.selected_members[mod->name].insert(it.first);
             for (auto &it : mod->memories)
                 if (match_ids(it.first, arg_memb))
                     sel.selected_members[mod->name].insert(it.first);
             for (auto &it : mod->cells_)
                 if (match_ids(it.first, arg_memb))
                     sel.selected_members[mod->name].insert(it.first);
             for (auto &it : mod->processes)
                 if (match_ids(it.first, arg_memb))
                     sel.selected_members[mod->name].insert(it.first);
         }
     }
 
     select_filter_active_mod(design, work_stack.back());
 }

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Variable Documentation

CdPass CdPass

LsPass LsPass

SelectPass SelectPass

std::vector<RTLIL::Selection> work_stack

static

Definition at line 31 of file select.cc.

Data Structures

Macros

Functions

Variables

Macro Definition Documentation

Function Documentation

Variable Documentation