435 bool flag_ignore_redef =
false;
436 bool flag_ignore_miss_func =
false;
437 bool flag_ignore_miss_dir =
false;
438 std::vector<std::string> attributes;
443 for (argidx = 1; argidx <
args.size(); argidx++) {
444 std::string arg =
args[argidx];
449 if (arg ==
"-ignore_redef") {
450 flag_ignore_redef =
true;
453 if (arg ==
"-ignore_miss_func") {
454 flag_ignore_miss_func =
true;
457 if (arg ==
"-ignore_miss_dir") {
458 flag_ignore_miss_dir =
true;
461 if (arg ==
"-setattr" && argidx+1 <
args.size()) {
472 for (
auto cell :
parser.ast->children)
474 if (cell->id !=
"cell" || cell->args.size() != 1)
479 if (design->
has(cell_name)) {
480 if (flag_ignore_redef)
488 module->
name = cell_name;
491 module->set_bool_attribute(
"\\blackbox");
493 for (
auto &attr : attributes)
494 module->attributes[attr] = 1;
496 for (
auto node : cell->children)
497 if (node->id ==
"pin" && node->args.size() == 1) {
498 LibertyAst *dir = node->find(
"direction");
499 if (!dir || (dir->value !=
"input" && dir->value !=
"output" && dir->value !=
"inout" && dir->value !=
"internal"))
501 if (!flag_ignore_miss_dir)
503 log_error(
"Missing or invalid direction for pin %s of cell %s.\n", node->args.at(0).c_str(),
log_id(module->
name));
505 log(
"Ignoring cell %s with missing or invalid direction for pin %s.\n",
log_id(module->
name), node->args.at(0).c_str());
510 if (!flag_lib || dir->value !=
"internal")
514 for (
auto node : cell->children)
517 if (node->id ==
"ff" && node->args.size() == 2)
519 if (node->id ==
"latch" && node->args.size() == 2)
523 if (node->id ==
"pin" && node->args.size() == 1)
525 LibertyAst *dir = node->find(
"direction");
527 if (flag_lib && dir->value ==
"internal")
532 if (dir && dir->value ==
"inout") {
537 if (dir && dir->value ==
"input") {
542 if (dir && dir->value ==
"output")
548 LibertyAst *func = node->find(
"function");
551 if (!flag_ignore_miss_func)
572 log(
"Imported %d cell types from liberty file.\n", cell_count);
void add(RTLIL::Module *module)
void log_header(const char *format,...)
std::map< RTLIL::IdString, RTLIL::Wire * > wires_
static std::string unescape_id(std::string str)
void log_error(const char *format,...)
static void create_latch(RTLIL::Module *module, LibertyAst *node)
static void create_ff(RTLIL::Module *module, LibertyAst *node)
static std::string escape_id(std::string str)
void connect(const RTLIL::SigSig &conn)
static RTLIL::SigSpec parse_func_expr(RTLIL::Module *module, const char *expr)
RTLIL::Wire * addWire(RTLIL::IdString name, int width=1)
bool has(RTLIL::IdString id) const
void log(const char *format,...)
std::pair< SigSpec, SigSpec > SigSig
const char * log_id(RTLIL::IdString str)
void extra_args(std::istream *&f, std::string &filename, std::vector< std::string > args, size_t argidx)