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liberty.cc File Reference
#include "passes/techmap/libparse.h"
#include "kernel/register.h"
#include "kernel/log.h"
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Data Structures

struct  token_t
 
struct  LibertyFrontend
 

Functions

static RTLIL::SigSpec parse_func_identifier (RTLIL::Module *module, const char *&expr)
 
static RTLIL::SigSpec create_inv_cell (RTLIL::Module *module, RTLIL::SigSpec A)
 
static RTLIL::SigSpec create_xor_cell (RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
 
static RTLIL::SigSpec create_and_cell (RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
 
static RTLIL::SigSpec create_or_cell (RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
 
static bool parse_func_reduce (RTLIL::Module *module, std::vector< token_t > &stack, token_t next_token)
 
static RTLIL::SigSpec parse_func_expr (RTLIL::Module *module, const char *expr)
 
static void create_ff (RTLIL::Module *module, LibertyAst *node)
 
static void create_latch (RTLIL::Module *module, LibertyAst *node)
 

Variables

LibertyFrontend LibertyFrontend
 

Function Documentation

static RTLIL::SigSpec create_and_cell ( RTLIL::Module *  module,
RTLIL::SigSpec  A,
RTLIL::SigSpec  B 
)
static

Definition at line 72 of file liberty.cc.

73 {
74  RTLIL::Cell *cell = module->addCell(NEW_ID, "$_AND_");
75  cell->setPort("\\A", A);
76  cell->setPort("\\B", B);
77  cell->setPort("\\Y", module->addWire(NEW_ID));
78  return cell->getPort("\\Y");
79 }
RTLIL::Module::addCell
RTLIL::Cell * addCell(RTLIL::IdString name, RTLIL::IdString type)
Definition: rtlil.cc:1353
RTLIL::Cell::setPort
void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
Definition: rtlil.cc:1789
RTLIL::Cell::getPort
const RTLIL::SigSpec & getPort(RTLIL::IdString portname) const
Definition: rtlil.cc:1809
RTLIL::Module::addWire
RTLIL::Wire * addWire(RTLIL::IdString name, int width=1)
Definition: rtlil.cc:1331
NEW_ID
#define NEW_ID
Definition: yosys.h:166

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static void create_ff ( RTLIL::Module *  module,
LibertyAst *  node 
)
static

Definition at line 216 of file liberty.cc.

217 {
218  RTLIL::SigSpec iq_sig(module->addWire(RTLIL::escape_id(node->args.at(0))));
219  RTLIL::SigSpec iqn_sig(module->addWire(RTLIL::escape_id(node->args.at(1))));
220 
221  RTLIL::SigSpec clk_sig, data_sig, clear_sig, preset_sig;
222  bool clk_polarity = true, clear_polarity = true, preset_polarity = true;
223 
224  for (auto child : node->children) {
225  if (child->id == "clocked_on")
226  clk_sig = parse_func_expr(module, child->value.c_str());
227  if (child->id == "next_state")
228  data_sig = parse_func_expr(module, child->value.c_str());
229  if (child->id == "clear")
230  clear_sig = parse_func_expr(module, child->value.c_str());
231  if (child->id == "preset")
232  preset_sig = parse_func_expr(module, child->value.c_str());
233  }
234 
235  if (clk_sig.size() == 0 || data_sig.size() == 0)
236  log_error("FF cell %s has no next_state and/or clocked_on attribute.\n", log_id(module->name));
237 
238  for (bool rerun_invert_rollback = true; rerun_invert_rollback;)
239  {
240  rerun_invert_rollback = false;
241 
242  for (auto &it : module->cells_) {
243  if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == clk_sig) {
244  clk_sig = it.second->getPort("\\A");
245  clk_polarity = !clk_polarity;
246  rerun_invert_rollback = true;
247  }
248  if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == clear_sig) {
249  clear_sig = it.second->getPort("\\A");
250  clear_polarity = !clear_polarity;
251  rerun_invert_rollback = true;
252  }
253  if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == preset_sig) {
254  preset_sig = it.second->getPort("\\A");
255  preset_polarity = !preset_polarity;
256  rerun_invert_rollback = true;
257  }
258  }
259  }
260 
261  RTLIL::Cell *cell = module->addCell(NEW_ID, "$_NOT_");
262  cell->setPort("\\A", iq_sig);
263  cell->setPort("\\Y", iqn_sig);
264 
265  cell = module->addCell(NEW_ID, "");
266  cell->setPort("\\D", data_sig);
267  cell->setPort("\\Q", iq_sig);
268  cell->setPort("\\C", clk_sig);
269 
270  if (clear_sig.size() == 0 && preset_sig.size() == 0) {
271  cell->type = stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N');
272  }
273 
274  if (clear_sig.size() == 1 && preset_sig.size() == 0) {
275  cell->type = stringf("$_DFF_%c%c0_", clk_polarity ? 'P' : 'N', clear_polarity ? 'P' : 'N');
276  cell->setPort("\\R", clear_sig);
277  }
278 
279  if (clear_sig.size() == 0 && preset_sig.size() == 1) {
280  cell->type = stringf("$_DFF_%c%c1_", clk_polarity ? 'P' : 'N', preset_polarity ? 'P' : 'N');
281  cell->setPort("\\R", preset_sig);
282  }
283 
284  if (clear_sig.size() == 1 && preset_sig.size() == 1) {
285  cell->type = stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', preset_polarity ? 'P' : 'N', clear_polarity ? 'P' : 'N');
286  cell->setPort("\\S", preset_sig);
287  cell->setPort("\\R", clear_sig);
288  }
289 
290  log_assert(!cell->type.empty());
291 }
stringf
std::string stringf(const char *fmt,...)
Definition: yosys.cc:58
RTLIL::Module::addCell
RTLIL::Cell * addCell(RTLIL::IdString name, RTLIL::IdString type)
Definition: rtlil.cc:1353
clk_polarity
bool clk_polarity
Definition: abc.cc:98
RTLIL::Cell::setPort
void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
Definition: rtlil.cc:1789
log_error
void log_error(const char *format,...)
Definition: log.cc:204
RTLIL::Cell::type
RTLIL::IdString type
Definition: rtlil.h:854
RTLIL::IdString::empty
bool empty() const
Definition: rtlil.h:219
RTLIL::escape_id
static std::string escape_id(std::string str)
Definition: rtlil.h:251
parse_func_expr
static RTLIL::SigSpec parse_func_expr(RTLIL::Module *module, const char *expr)
Definition: liberty.cc:178
log_assert
#define log_assert(_assert_expr_)
Definition: log.h:85
RTLIL::Module::addWire
RTLIL::Wire * addWire(RTLIL::IdString name, int width=1)
Definition: rtlil.cc:1331
RTLIL::Module::name
RTLIL::IdString name
Definition: rtlil.h:599
NEW_ID
#define NEW_ID
Definition: yosys.h:166
clk_sig
RTLIL::SigSpec clk_sig
Definition: abc.cc:99
RTLIL::Module::cells_
std::map< RTLIL::IdString, RTLIL::Cell * > cells_
Definition: rtlil.h:596
log_id
const char * log_id(RTLIL::IdString str)
Definition: log.cc:283

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static RTLIL::SigSpec create_inv_cell ( RTLIL::Module *  module,
RTLIL::SigSpec  A 
)
static

Definition at line 55 of file liberty.cc.

56 {
57  RTLIL::Cell *cell = module->addCell(NEW_ID, "$_NOT_");
58  cell->setPort("\\A", A);
59  cell->setPort("\\Y", module->addWire(NEW_ID));
60  return cell->getPort("\\Y");
61 }
RTLIL::Module::addCell
RTLIL::Cell * addCell(RTLIL::IdString name, RTLIL::IdString type)
Definition: rtlil.cc:1353
RTLIL::Cell::setPort
void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
Definition: rtlil.cc:1789
RTLIL::Cell::getPort
const RTLIL::SigSpec & getPort(RTLIL::IdString portname) const
Definition: rtlil.cc:1809
RTLIL::Module::addWire
RTLIL::Wire * addWire(RTLIL::IdString name, int width=1)
Definition: rtlil.cc:1331
NEW_ID
#define NEW_ID
Definition: yosys.h:166

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static void create_latch ( RTLIL::Module *  module,
LibertyAst *  node 
)
static

Definition at line 293 of file liberty.cc.

294 {
295  RTLIL::SigSpec iq_sig(module->addWire(RTLIL::escape_id(node->args.at(0))));
296  RTLIL::SigSpec iqn_sig(module->addWire(RTLIL::escape_id(node->args.at(1))));
297 
298  RTLIL::SigSpec enable_sig, data_sig, clear_sig, preset_sig;
299  bool enable_polarity = true, clear_polarity = true, preset_polarity = true;
300 
301  for (auto child : node->children) {
302  if (child->id == "enable")
303  enable_sig = parse_func_expr(module, child->value.c_str());
304  if (child->id == "data_in")
305  data_sig = parse_func_expr(module, child->value.c_str());
306  if (child->id == "clear")
307  clear_sig = parse_func_expr(module, child->value.c_str());
308  if (child->id == "preset")
309  preset_sig = parse_func_expr(module, child->value.c_str());
310  }
311 
312  if (enable_sig.size() == 0 || data_sig.size() == 0)
313  log_error("Latch cell %s has no data_in and/or enable attribute.\n", log_id(module->name));
314 
315  for (bool rerun_invert_rollback = true; rerun_invert_rollback;)
316  {
317  rerun_invert_rollback = false;
318 
319  for (auto &it : module->cells_) {
320  if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == enable_sig) {
321  enable_sig = it.second->getPort("\\A");
322  enable_polarity = !enable_polarity;
323  rerun_invert_rollback = true;
324  }
325  if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == clear_sig) {
326  clear_sig = it.second->getPort("\\A");
327  clear_polarity = !clear_polarity;
328  rerun_invert_rollback = true;
329  }
330  if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == preset_sig) {
331  preset_sig = it.second->getPort("\\A");
332  preset_polarity = !preset_polarity;
333  rerun_invert_rollback = true;
334  }
335  }
336  }
337 
338  RTLIL::Cell *cell = module->addCell(NEW_ID, "$_NOT_");
339  cell->setPort("\\A", iq_sig);
340  cell->setPort("\\Y", iqn_sig);
341 
342  if (clear_sig.size() == 1)
343  {
344  RTLIL::SigSpec clear_negative = clear_sig;
345  RTLIL::SigSpec clear_enable = clear_sig;
346 
347  if (clear_polarity == true || clear_polarity != enable_polarity)
348  {
349  RTLIL::Cell *inv = module->addCell(NEW_ID, "$_NOT_");
350  inv->setPort("\\A", clear_sig);
351  inv->setPort("\\Y", module->addWire(NEW_ID));
352 
353  if (clear_polarity == true)
354  clear_negative = inv->getPort("\\Y");
355  if (clear_polarity != enable_polarity)
356  clear_enable = inv->getPort("\\Y");
357  }
358 
359  RTLIL::Cell *data_gate = module->addCell(NEW_ID, "$_AND_");
360  data_gate->setPort("\\A", data_sig);
361  data_gate->setPort("\\B", clear_negative);
362  data_gate->setPort("\\Y", data_sig = module->addWire(NEW_ID));
363 
364  RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? "$_OR_" : "$_AND_");
365  enable_gate->setPort("\\A", enable_sig);
366  enable_gate->setPort("\\B", clear_enable);
367  enable_gate->setPort("\\Y", data_sig = module->addWire(NEW_ID));
368  }
369 
370  if (preset_sig.size() == 1)
371  {
372  RTLIL::SigSpec preset_positive = preset_sig;
373  RTLIL::SigSpec preset_enable = preset_sig;
374 
375  if (preset_polarity == false || preset_polarity != enable_polarity)
376  {
377  RTLIL::Cell *inv = module->addCell(NEW_ID, "$_NOT_");
378  inv->setPort("\\A", preset_sig);
379  inv->setPort("\\Y", module->addWire(NEW_ID));
380 
381  if (preset_polarity == false)
382  preset_positive = inv->getPort("\\Y");
383  if (preset_polarity != enable_polarity)
384  preset_enable = inv->getPort("\\Y");
385  }
386 
387  RTLIL::Cell *data_gate = module->addCell(NEW_ID, "$_OR_");
388  data_gate->setPort("\\A", data_sig);
389  data_gate->setPort("\\B", preset_positive);
390  data_gate->setPort("\\Y", data_sig = module->addWire(NEW_ID));
391 
392  RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? "$_OR_" : "$_AND_");
393  enable_gate->setPort("\\A", enable_sig);
394  enable_gate->setPort("\\B", preset_enable);
395  enable_gate->setPort("\\Y", data_sig = module->addWire(NEW_ID));
396  }
397 
398  cell = module->addCell(NEW_ID, stringf("$_DLATCH_%c_", enable_polarity ? 'P' : 'N'));
399  cell->setPort("\\D", data_sig);
400  cell->setPort("\\Q", iq_sig);
401  cell->setPort("\\E", enable_sig);
402 }
stringf
std::string stringf(const char *fmt,...)
Definition: yosys.cc:58
RTLIL::Module::addCell
RTLIL::Cell * addCell(RTLIL::IdString name, RTLIL::IdString type)
Definition: rtlil.cc:1353
RTLIL::Cell::setPort
void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
Definition: rtlil.cc:1789
log_error
void log_error(const char *format,...)
Definition: log.cc:204
RTLIL::escape_id
static std::string escape_id(std::string str)
Definition: rtlil.h:251
RTLIL::Cell::getPort
const RTLIL::SigSpec & getPort(RTLIL::IdString portname) const
Definition: rtlil.cc:1809
parse_func_expr
static RTLIL::SigSpec parse_func_expr(RTLIL::Module *module, const char *expr)
Definition: liberty.cc:178
RTLIL::Module::addWire
RTLIL::Wire * addWire(RTLIL::IdString name, int width=1)
Definition: rtlil.cc:1331
RTLIL::Module::name
RTLIL::IdString name
Definition: rtlil.h:599
NEW_ID
#define NEW_ID
Definition: yosys.h:166
RTLIL::Module::cells_
std::map< RTLIL::IdString, RTLIL::Cell * > cells_
Definition: rtlil.h:596
log_id
const char * log_id(RTLIL::IdString str)
Definition: log.cc:283

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static RTLIL::SigSpec create_or_cell ( RTLIL::Module *  module,
RTLIL::SigSpec  A,
RTLIL::SigSpec  B 
)
static

Definition at line 81 of file liberty.cc.

82 {
83  RTLIL::Cell *cell = module->addCell(NEW_ID, "$_OR_");
84  cell->setPort("\\A", A);
85  cell->setPort("\\B", B);
86  cell->setPort("\\Y", module->addWire(NEW_ID));
87  return cell->getPort("\\Y");
88 }
RTLIL::Module::addCell
RTLIL::Cell * addCell(RTLIL::IdString name, RTLIL::IdString type)
Definition: rtlil.cc:1353
RTLIL::Cell::setPort
void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
Definition: rtlil.cc:1789
RTLIL::Cell::getPort
const RTLIL::SigSpec & getPort(RTLIL::IdString portname) const
Definition: rtlil.cc:1809
RTLIL::Module::addWire
RTLIL::Wire * addWire(RTLIL::IdString name, int width=1)
Definition: rtlil.cc:1331
NEW_ID
#define NEW_ID
Definition: yosys.h:166

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static RTLIL::SigSpec create_xor_cell ( RTLIL::Module *  module,
RTLIL::SigSpec  A,
RTLIL::SigSpec  B 
)
static

Definition at line 63 of file liberty.cc.

64 {
65  RTLIL::Cell *cell = module->addCell(NEW_ID, "$_XOR_");
66  cell->setPort("\\A", A);
67  cell->setPort("\\B", B);
68  cell->setPort("\\Y", module->addWire(NEW_ID));
69  return cell->getPort("\\Y");
70 }
RTLIL::Module::addCell
RTLIL::Cell * addCell(RTLIL::IdString name, RTLIL::IdString type)
Definition: rtlil.cc:1353
RTLIL::Cell::setPort
void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
Definition: rtlil.cc:1789
RTLIL::Cell::getPort
const RTLIL::SigSpec & getPort(RTLIL::IdString portname) const
Definition: rtlil.cc:1809
RTLIL::Module::addWire
RTLIL::Wire * addWire(RTLIL::IdString name, int width=1)
Definition: rtlil.cc:1331
NEW_ID
#define NEW_ID
Definition: yosys.h:166

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static RTLIL::SigSpec parse_func_expr ( RTLIL::Module *  module,
const char *  expr 
)
static

Definition at line 178 of file liberty.cc.

179 {
180  const char *orig_expr = expr;
181  std::vector<token_t> stack;
182 
183  while (*expr)
184  {
185  if (*expr == ' ' || *expr == '\t' || *expr == '\r' || *expr == '\n' || *expr == '"') {
186  expr++;
187  continue;
188  }
189 
190  token_t next_token(0);
191  if (*expr == '(' || *expr == ')' || *expr == '\'' || *expr == '!' || *expr == '^' || *expr == '*' || *expr == '+' || *expr == '|')
192  next_token = token_t(*(expr++));
193  else
194  next_token = token_t(0, parse_func_identifier(module, expr));
195 
196  while (parse_func_reduce(module, stack, next_token)) {}
197  stack.push_back(next_token);
198  }
199 
200  while (parse_func_reduce(module, stack, token_t('.'))) {}
201 
202 #if 0
203  for (size_t i = 0; i < stack.size(); i++)
204  if (stack[i].type < 16)
205  log("%3d: %d %s\n", int(i), stack[i].type, log_signal(stack[i].sig));
206  else
207  log("%3d: %c\n", int(i), stack[i].type);
208 #endif
209 
210  if (stack.size() != 1 || stack.back().type != 3)
211  log_error("Parser error in function expr `%s'.\n", orig_expr);
212 
213  return stack.back().sig;
214 }
next_token
static std::string next_token(bool pass_newline=false)
Definition: preproc.cc:96
log_signal
const char * log_signal(const RTLIL::SigSpec &sig, bool autoint)
Definition: log.cc:269
parse_func_identifier
static RTLIL::SigSpec parse_func_identifier(RTLIL::Module *module, const char *&expr)
Definition: liberty.cc:33
token_t
Definition: liberty.cc:26
log_error
void log_error(const char *format,...)
Definition: log.cc:204
log
void log(const char *format,...)
Definition: log.cc:180
parse_func_reduce
static bool parse_func_reduce(RTLIL::Module *module, std::vector< token_t > &stack, token_t next_token)
Definition: liberty.cc:90

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static RTLIL::SigSpec parse_func_identifier ( RTLIL::Module *  module,
const char *&  expr 
)
static

Definition at line 33 of file liberty.cc.

34 {
35  log_assert(*expr != 0);
36 
37  int id_len = 0;
38  while (('a' <= expr[id_len] && expr[id_len] <= 'z') || ('A' <= expr[id_len] && expr[id_len] <= 'Z') ||
39  ('0' <= expr[id_len] && expr[id_len] <= '9') || expr[id_len] == '.' || expr[id_len] == '_') id_len++;
40 
41  if (id_len == 0)
42  log_error("Expected identifier at `%s'.\n", expr);
43 
44  if (id_len == 1 && (*expr == '0' || *expr == '1'))
45  return *(expr++) == '0' ? RTLIL::State::S0 : RTLIL::State::S1;
46 
47  std::string id = RTLIL::escape_id(std::string(expr, id_len));
48  if (!module->wires_.count(id))
49  log_error("Can't resolve wire name %s.\n", RTLIL::unescape_id(id).c_str());
50 
51  expr += id_len;
52  return module->wires_.at(id);
53 }
RTLIL::Module::wires_
std::map< RTLIL::IdString, RTLIL::Wire * > wires_
Definition: rtlil.h:595
RTLIL::unescape_id
static std::string unescape_id(std::string str)
Definition: rtlil.h:257
log_error
void log_error(const char *format,...)
Definition: log.cc:204
RTLIL::escape_id
static std::string escape_id(std::string str)
Definition: rtlil.h:251
log_assert
#define log_assert(_assert_expr_)
Definition: log.h:85

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static bool parse_func_reduce ( RTLIL::Module *  module,
std::vector< token_t > &  stack,
token_t  next_token 
)
static

Definition at line 90 of file liberty.cc.

91 {
92  int top = int(stack.size())-1;
93 
94  if (0 <= top-1 && stack[top].type == 0 && stack[top-1].type == '!') {
95  token_t t = token_t(0, create_inv_cell(module, stack[top].sig));
96  stack.pop_back();
97  stack.pop_back();
98  stack.push_back(t);
99  return true;
100  }
101 
102  if (0 <= top-1 && stack[top].type == '\'' && stack[top-1].type == 0) {
103  token_t t = token_t(0, create_inv_cell(module, stack[top-1].sig));
104  stack.pop_back();
105  stack.pop_back();
106  stack.push_back(t);
107  return true;
108  }
109 
110  if (0 <= top && stack[top].type == 0) {
111  if (next_token.type == '\'')
112  return false;
113  stack[top].type = 1;
114  return true;
115  }
116 
117  if (0 <= top-2 && stack[top-2].type == 1 && stack[top-1].type == '^' && stack[top].type == 1) {
118  token_t t = token_t(1, create_xor_cell(module, stack[top-2].sig, stack[top].sig));
119  stack.pop_back();
120  stack.pop_back();
121  stack.pop_back();
122  stack.push_back(t);
123  return true;
124  }
125 
126  if (0 <= top && stack[top].type == 1) {
127  if (next_token.type == '^')
128  return false;
129  stack[top].type = 2;
130  return true;
131  }
132 
133  if (0 <= top-1 && stack[top-1].type == 2 && stack[top].type == 2) {
134  token_t t = token_t(2, create_and_cell(module, stack[top-1].sig, stack[top].sig));
135  stack.pop_back();
136  stack.pop_back();
137  stack.push_back(t);
138  return true;
139  }
140 
141  if (0 <= top-2 && stack[top-2].type == 2 && (stack[top-1].type == '*' || stack[top-1].type == '&') && stack[top].type == 2) {
142  token_t t = token_t(2, create_and_cell(module, stack[top-2].sig, stack[top].sig));
143  stack.pop_back();
144  stack.pop_back();
145  stack.pop_back();
146  stack.push_back(t);
147  return true;
148  }
149 
150  if (0 <= top && stack[top].type == 2) {
151  if (next_token.type == '*' || next_token.type == '&' || next_token.type == 0 || next_token.type == '(')
152  return false;
153  stack[top].type = 3;
154  return true;
155  }
156 
157  if (0 <= top-2 && stack[top-2].type == 3 && (stack[top-1].type == '+' || stack[top-1].type == '|') && stack[top].type == 3) {
158  token_t t = token_t(3, create_or_cell(module, stack[top-2].sig, stack[top].sig));
159  stack.pop_back();
160  stack.pop_back();
161  stack.pop_back();
162  stack.push_back(t);
163  return true;
164  }
165 
166  if (0 <= top-2 && stack[top-2].type == '(' && stack[top-1].type == 3 && stack[top].type == ')') {
167  token_t t = token_t(0, stack[top-1].sig);
168  stack.pop_back();
169  stack.pop_back();
170  stack.pop_back();
171  stack.push_back(t);
172  return true;
173  }
174 
175  return false;
176 }
token_t::type
char type
Definition: liberty.cc:27
token_t
Definition: liberty.cc:26
create_and_cell
static RTLIL::SigSpec create_and_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
Definition: liberty.cc:72
create_inv_cell
static RTLIL::SigSpec create_inv_cell(RTLIL::Module *module, RTLIL::SigSpec A)
Definition: liberty.cc:55
create_or_cell
static RTLIL::SigSpec create_or_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
Definition: liberty.cc:81
create_xor_cell
static RTLIL::SigSpec create_xor_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
Definition: liberty.cc:63

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Variable Documentation

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