SpiceBackend Struct Reference

Inheritance diagram for SpiceBackend:

Collaboration diagram for SpiceBackend:

Public Member Functions
	SpiceBackend ()
virtual void	help ()
virtual void	execute (std::ostream *&f, std::string filename, std::vector< std::string > args, RTLIL::Design *design)
virtual void	run_register ()
virtual void	execute (std::vector< std::string > args, RTLIL::Design *design) YS_OVERRIDE YS_FINAL
void	extra_args (std::ostream *&f, std::string &filename, std::vector< std::string > args, size_t argidx)
void	extra_args (std::vector< std::string > args, size_t argidx, RTLIL::Design *design, bool select=true)
pre_post_exec_state_t	pre_execute ()
void	post_execute (pre_post_exec_state_t state)
void	cmd_log_args (const std::vector< std::string > &args)
void	cmd_error (const std::vector< std::string > &args, size_t argidx, std::string msg)

Static Public Member Functions
static void	backend_call (RTLIL::Design *design, std::ostream *f, std::string filename, std::string command)
static void	backend_call (RTLIL::Design *design, std::ostream *f, std::string filename, std::vector< std::string > args)
static void	call (RTLIL::Design *design, std::string command)
static void	call (RTLIL::Design *design, std::vector< std::string > args)
static void	call_on_selection (RTLIL::Design *design, const RTLIL::Selection &selection, std::string command)
static void	call_on_selection (RTLIL::Design *design, const RTLIL::Selection &selection, std::vector< std::string > args)
static void	call_on_module (RTLIL::Design *design, RTLIL::Module *module, std::string command)
static void	call_on_module (RTLIL::Design *design, RTLIL::Module *module, std::vector< std::string > args)
static void	init_register ()
static void	done_register ()

Data Fields
std::string	backend_name
std::string	pass_name
std::string	short_help
int	call_counter
int64_t	runtime_ns
Pass *	next_queued_pass

Detailed Description

Definition at line 112 of file spice.cc.

Constructor & Destructor Documentation

SpiceBackend::SpiceBackend ( )

inline

Definition at line 113 of file spice.cc.

: Backend("spice", "write design to SPICE netlist file") { }

Member Function Documentation

void Backend::backend_call ( RTLIL::Design *  design, std::ostream *  f, std::string  filename, std::string  command  )

staticinherited

Definition at line 479 of file register.cc.

{
    std::vector<std::string> args;
    char *s = strdup(command.c_str());
    for (char *p = strtok(s, " \t\r\n"); p; p = strtok(NULL, " \t\r\n"))
        args.push_back(p);
    free(s);
    backend_call(design, f, filename, args);
}

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void Backend::backend_call ( RTLIL::Design *  design, std::ostream *  f, std::string  filename, std::vector< std::string >  args  )

staticinherited

Definition at line 489 of file register.cc.

{
    if (args.size() == 0)
        return;
    if (backend_register.count(args[0]) == 0)
        log_cmd_error("No such backend: %s\n", args[0].c_str());

    size_t orig_sel_stack_pos = design->selection_stack.size();

    if (f != NULL) {
        auto state = backend_register[args[0]]->pre_execute();
        backend_register[args[0]]->execute(f, filename, args, design);
        backend_register[args[0]]->post_execute(state);
    } else if (filename == "-") {
        std::ostream *f_cout = &std::cout;
        auto state = backend_register[args[0]]->pre_execute();
        backend_register[args[0]]->execute(f_cout, "<stdout>", args, design);
        backend_register[args[0]]->post_execute(state);
    } else {
        if (!filename.empty())
            args.push_back(filename);
        backend_register[args[0]]->execute(args, design);
    }

    while (design->selection_stack.size() > orig_sel_stack_pos)
        design->selection_stack.pop_back();

    design->check();
}

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void Pass::call ( RTLIL::Design *  design, std::string  command  )

staticinherited

Definition at line 146 of file register.cc.

{
    std::vector<std::string> args;

    std::string cmd_buf = command;
    std::string tok = next_token(cmd_buf, " \t\r\n");

    if (tok.empty() || tok[0] == '#')
        return;

    if (tok[0] == '!') {
        cmd_buf = command.substr(command.find('!') + 1);
        while (!cmd_buf.empty() && (cmd_buf.back() == ' ' || cmd_buf.back() == '\t' ||
                cmd_buf.back() == '\r' || cmd_buf.back() == '\n'))
            cmd_buf.resize(cmd_buf.size()-1);
        log_header("Shell command: %s\n", cmd_buf.c_str());
        int retCode = run_command(cmd_buf);
        if (retCode != 0)
            log_cmd_error("Shell command returned error code %d.\n", retCode);
        return;
    }

    while (!tok.empty()) {
        if (tok == "#")
            break;
        if (tok.back() == ';') {
            int num_semikolon = 0;
            while (!tok.empty() && tok.back() == ';')
                tok.resize(tok.size()-1), num_semikolon++;
            if (!tok.empty())
                args.push_back(tok);
            call(design, args);
            args.clear();
            if (num_semikolon == 2)
                call(design, "clean");
            if (num_semikolon == 3)
                call(design, "clean -purge");
        } else
            args.push_back(tok);
        tok = next_token(cmd_buf, " \t\r\n");
    }

    call(design, args);
}

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void Pass::call ( RTLIL::Design *  design, std::vector< std::string >  args  )

staticinherited

Definition at line 191 of file register.cc.

{
    if (args.size() == 0 || args[0][0] == '#')
        return;

    if (echo_mode) {
        log("%s", create_prompt(design, 0));
        for (size_t i = 0; i < args.size(); i++)
            log("%s%s", i ? " " : "", args[i].c_str());
        log("\n");
    }

    if (pass_register.count(args[0]) == 0)
        log_cmd_error("No such command: %s (type 'help' for a command overview)\n", args[0].c_str());

    size_t orig_sel_stack_pos = design->selection_stack.size();
    auto state = pass_register[args[0]]->pre_execute();
    pass_register[args[0]]->execute(args, design);
    pass_register[args[0]]->post_execute(state);
    while (design->selection_stack.size() > orig_sel_stack_pos)
        design->selection_stack.pop_back();

    design->check();
}

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void Pass::call_on_module ( RTLIL::Design *  design, RTLIL::Module *  module, std::string  command  )

staticinherited

Definition at line 240 of file register.cc.

{
    std::string backup_selected_active_module = design->selected_active_module;
    design->selected_active_module = module->name.str();
    design->selection_stack.push_back(RTLIL::Selection(false));
    design->selection_stack.back().select(module);

    Pass::call(design, command);

    design->selection_stack.pop_back();
    design->selected_active_module = backup_selected_active_module;
}

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void Pass::call_on_module ( RTLIL::Design *  design, RTLIL::Module *  module, std::vector< std::string >  args  )

staticinherited

Definition at line 253 of file register.cc.

{
    std::string backup_selected_active_module = design->selected_active_module;
    design->selected_active_module = module->name.str();
    design->selection_stack.push_back(RTLIL::Selection(false));
    design->selection_stack.back().select(module);

    Pass::call(design, args);

    design->selection_stack.pop_back();
    design->selected_active_module = backup_selected_active_module;
}

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void Pass::call_on_selection ( RTLIL::Design *  design, const RTLIL::Selection &  selection, std::string  command  )

staticinherited

Definition at line 216 of file register.cc.

{
    std::string backup_selected_active_module = design->selected_active_module;
    design->selected_active_module.clear();
    design->selection_stack.push_back(selection);

    Pass::call(design, command);

    design->selection_stack.pop_back();
    design->selected_active_module = backup_selected_active_module;
}

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void Pass::call_on_selection ( RTLIL::Design *  design, const RTLIL::Selection &  selection, std::vector< std::string >  args  )

staticinherited

Definition at line 228 of file register.cc.

{
    std::string backup_selected_active_module = design->selected_active_module;
    design->selected_active_module.clear();
    design->selection_stack.push_back(selection);

    Pass::call(design, args);

    design->selection_stack.pop_back();
    design->selected_active_module = backup_selected_active_module;
}

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void Pass::cmd_error ( const std::vector< std::string > &  args, size_t  argidx, std::string  msg  )

inherited

Definition at line 110 of file register.cc.

{
    std::string command_text;
    int error_pos = 0;

    for (size_t i = 0; i < args.size(); i++) {
        if (i < argidx)
            error_pos += args[i].size() + 1;
        command_text = command_text + (command_text.empty() ? "" : " ") + args[i];
    }

    log("\nSyntax error in command `%s':\n", command_text.c_str());
    help();

    log_cmd_error("Command syntax error: %s\n> %s\n> %*s^\n",
            msg.c_str(), command_text.c_str(), error_pos, "");
}

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void Pass::cmd_log_args ( const std::vector< std::string > &  args )

inherited

Definition at line 100 of file register.cc.

{
    if (args.size() <= 1)
        return;
    log("Full command line:");
    for (size_t i = 0; i < args.size(); i++)
        log(" %s", args[i].c_str());
    log("\n");
}

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void Pass::done_register ( )

staticinherited

Definition at line 62 of file register.cc.

{
    frontend_register.clear();
    pass_register.clear();
    backend_register.clear();
    log_assert(first_queued_pass == NULL);
}

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void Backend::execute ( std::vector< std::string >  args, RTLIL::Design *  design  )

virtualinherited

Implements Pass.

Definition at line 429 of file register.cc.

{
    std::ostream *f = NULL;
    auto state = pre_execute();
    execute(f, std::string(), args, design);
    post_execute(state);
    if (f != &std::cout)
        delete f;
}

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virtual void SpiceBackend::execute ( std::ostream *&  f, std::string  filename, std::vector< std::string >  args, RTLIL::Design *  design  )

inlinevirtual

Implements Backend.

Definition at line 139 of file spice.cc.

    {
        std::string top_module_name;
        RTLIL::Module *top_module = NULL;
        bool big_endian = false;
        std::string neg = "Vss", pos = "Vdd", ncpf = "_NC";

        log_header("Executing SPICE backend.\n");

        size_t argidx;
        for (argidx = 1; argidx < args.size(); argidx++)
        {
            if (args[argidx] == "-big_endian") {
                big_endian = true;
                continue;
            }
            if (args[argidx] == "-neg" && argidx+1 < args.size()) {
                neg = args[++argidx];
                continue;
            }
            if (args[argidx] == "-pos" && argidx+1 < args.size()) {
                pos = args[++argidx];
                continue;
            }
            if (args[argidx] == "-nc_prefix" && argidx+1 < args.size()) {
                ncpf = args[++argidx];
                continue;
            }
            if (args[argidx] == "-top" && argidx+1 < args.size()) {
                top_module_name = args[++argidx];
                continue;
            }
            break;
        }
        extra_args(f, filename, args, argidx);

        if (top_module_name.empty())
            for (auto & mod_it:design->modules_)
                if (mod_it.second->get_bool_attribute("\\top"))
                    top_module_name = mod_it.first.str();

        *f << stringf("* SPICE netlist generated by %s\n", yosys_version_str);
        *f << stringf("\n");

        for (auto module_it : design->modules_)
        {
            RTLIL::Module *module = module_it.second;
            if (module->get_bool_attribute("\\blackbox"))
                continue;

            if (module->processes.size() != 0)
                log_error("Found unmapped processes in module %s: unmapped processes are not supported in SPICE backend!\n", RTLIL::id2cstr(module->name));
            if (module->memories.size() != 0)
                log_error("Found munmapped emories in module %s: unmapped memories are not supported in SPICE backend!\n", RTLIL::id2cstr(module->name));

            if (module->name == RTLIL::escape_id(top_module_name)) {
                top_module = module;
                continue;
            }

            std::vector<RTLIL::Wire*> ports;
            for (auto wire_it : module->wires_) {
                RTLIL::Wire *wire = wire_it.second;
                if (wire->port_id == 0)
                    continue;
                while (int(ports.size()) < wire->port_id)
                    ports.push_back(NULL);
                ports.at(wire->port_id-1) = wire;
            }

            *f << stringf(".SUBCKT %s", RTLIL::id2cstr(module->name));
            for (RTLIL::Wire *wire : ports) {
                log_assert(wire != NULL);
                if (wire->width > 1) {
                    for (int i = 0; i < wire->width; i++)
                        *f << stringf(" %s[%d]", RTLIL::id2cstr(wire->name), big_endian ? wire->width - 1 - i : i);
                } else
                    *f << stringf(" %s", RTLIL::id2cstr(wire->name));
            }
            *f << stringf("\n");
            print_spice_module(*f, module, design, neg, pos, ncpf, big_endian);
            *f << stringf(".ENDS %s\n\n", RTLIL::id2cstr(module->name));
        }

        if (!top_module_name.empty()) {
            if (top_module == NULL)
                log_error("Can't find top module `%s'!\n", top_module_name.c_str());
            print_spice_module(*f, top_module, design, neg, pos, ncpf, big_endian);
            *f << stringf("\n");
        }

        *f << stringf("************************\n");
        *f << stringf("* end of SPICE netlist *\n");
        *f << stringf("************************\n");
        *f << stringf("\n");
    }

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void Pass::extra_args ( std::vector< std::string >  args, size_t  argidx, RTLIL::Design *  design, bool  select = true  )

inherited

Definition at line 128 of file register.cc.

{
    for (; argidx < args.size(); argidx++)
    {
        std::string arg = args[argidx];

        if (arg.substr(0, 1) == "-")
            cmd_error(args, argidx, "Unknown option or option in arguments.");

        if (!select)
            cmd_error(args, argidx, "Extra argument.");

        handle_extra_select_args(this, args, argidx, args.size(), design);
        break;
    }
    // cmd_log_args(args);
}

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void Backend::extra_args ( std::ostream *&  f, std::string &  filename, std::vector< std::string >  args, size_t  argidx  )

inherited

Definition at line 439 of file register.cc.

{
    bool called_with_fp = f != NULL;

    for (; argidx < args.size(); argidx++)
    {
        std::string arg = args[argidx];

        if (arg.substr(0, 1) == "-" && arg != "-")
            cmd_error(args, argidx, "Unknown option or option in arguments.");
        if (f != NULL)
            cmd_error(args, argidx, "Extra filename argument in direct file mode.");

        if (arg == "-") {
            filename = "<stdout>";
            f = &std::cout;
            continue;
        }

        filename = arg;
        std::ofstream *ff = new std::ofstream;
        ff->open(filename.c_str(), std::ofstream::trunc);
        if (ff->fail()) {
            delete ff;
            log_cmd_error("Can't open output file `%s' for writing: %s\n", filename.c_str(), strerror(errno));
        }
        f = ff;
    }

    if (called_with_fp)
        args.push_back(filename);
    args[0] = pass_name;
    // cmd_log_args(args);

    if (f == NULL) {
        filename = "<stdout>";
        f = &std::cout;
    }
}

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virtual void SpiceBackend::help ( )

inlinevirtual

Reimplemented from Pass.

Definition at line 114 of file spice.cc.

    {
        //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
        log("\n");
        log("    write_spice [options] [filename]\n");
        log("\n");
        log("Write the current design to an SPICE netlist file.\n");
        log("\n");
        log("    -big_endian\n");
        log("        generate multi-bit ports in MSB first order \n");
        log("        (default is LSB first)\n");
        log("\n");
        log("    -neg net_name\n");
        log("        set the net name for constant 0 (default: Vss)\n");
        log("\n");
        log("    -pos net_name\n");
        log("        set the net name for constant 1 (default: Vdd)\n");
        log("\n");
        log("    -nc_prefix\n");
        log("        prefix for not-connected nets (default: _NC)\n");
        log("\n");
        log("    -top top_module\n");
        log("        set the specified module as design top module\n");
        log("\n");
    }

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void Pass::init_register ( )

staticinherited

Definition at line 54 of file register.cc.

{
    while (first_queued_pass) {
        first_queued_pass->run_register();
        first_queued_pass = first_queued_pass->next_queued_pass;
    }
}

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void Pass::post_execute ( Pass::pre_post_exec_state_t  state )

inherited

Definition at line 84 of file register.cc.

{
    int64_t time_ns = PerformanceTimer::query() - state.begin_ns;
    runtime_ns += time_ns;
    current_pass = state.parent_pass;
    if (current_pass)
        current_pass->runtime_ns -= time_ns;
}

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Pass::pre_post_exec_state_t Pass::pre_execute ( )

inherited

Definition at line 74 of file register.cc.

{
    pre_post_exec_state_t state;
    call_counter++;
    state.begin_ns = PerformanceTimer::query();
    state.parent_pass = current_pass;
    current_pass = this;
    return state;
}

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void Backend::run_register ( )

virtualinherited

Reimplemented from Pass.

Definition at line 416 of file register.cc.

{
    log_assert(pass_register.count(pass_name) == 0);
    pass_register[pass_name] = this;

    log_assert(backend_register.count(backend_name) == 0);
    backend_register[backend_name] = this;
}

Field Documentation

std::string Backend::backend_name

inherited

Definition at line 88 of file register.h.

int Pass::call_counter

inherited

Definition at line 36 of file register.h.

Pass* Pass::next_queued_pass

inherited

Definition at line 60 of file register.h.

std::string Pass::pass_name

inherited

Definition at line 29 of file register.h.

int64_t Pass::runtime_ns

inherited

Definition at line 37 of file register.h.

std::string Pass::short_help

inherited

Definition at line 29 of file register.h.

---

The documentation for this struct was generated from the following file:

• spice.cc