spice.cc File Reference

#include "kernel/rtlil.h"
#include "kernel/register.h"
#include "kernel/sigtools.h"
#include "kernel/celltypes.h"
#include "kernel/log.h"
#include <string>

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Data Structures
struct	SpiceBackend

Functions
USING_YOSYS_NAMESPACE static PRIVATE_NAMESPACE_BEGIN void	print_spice_net (std::ostream &f, RTLIL::SigBit s, std::string &neg, std::string &pos, std::string &ncpf, int &nc_counter)
static void	print_spice_module (std::ostream &f, RTLIL::Module *module, RTLIL::Design *design, std::string &neg, std::string &pos, std::string &ncpf, bool big_endian)

Variables
SpiceBackend	SpiceBackend

Function Documentation

static void print_spice_module ( std::ostream &  f, RTLIL::Module *  module, RTLIL::Design *  design, std::string &  neg, std::string &  pos, std::string &  ncpf, bool  big_endian  )

static

Definition at line 47 of file spice.cc.

{
    SigMap sigmap(module);
    int cell_counter = 0, conn_counter = 0, nc_counter = 0;

    for (auto &cell_it : module->cells_)
    {
        RTLIL::Cell *cell = cell_it.second;
        f << stringf("X%d", cell_counter++);

        std::vector<RTLIL::SigSpec> port_sigs;

        if (design->modules_.count(cell->type) == 0)
        {
            log_warning("no (blackbox) module for cell type `%s' (%s.%s) found! Guessing order of ports.\n",
                    RTLIL::id2cstr(cell->type), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name));
            for (auto &conn : cell->connections()) {
                RTLIL::SigSpec sig = sigmap(conn.second);
                port_sigs.push_back(sig);
            }
        }
        else
        {
            RTLIL::Module *mod = design->modules_.at(cell->type);

            std::vector<RTLIL::Wire*> ports;
            for (auto wire_it : mod->wires_) {
                RTLIL::Wire *wire = wire_it.second;
                if (wire->port_id == 0)
                    continue;
                while (int(ports.size()) < wire->port_id)
                    ports.push_back(NULL);
                ports.at(wire->port_id-1) = wire;
            }

            for (RTLIL::Wire *wire : ports) {
                log_assert(wire != NULL);
                RTLIL::SigSpec sig(RTLIL::State::Sz, wire->width);
                if (cell->hasPort(wire->name)) {
                    sig = sigmap(cell->getPort(wire->name));
                    sig.extend(wire->width, false);
                }
                port_sigs.push_back(sig);
            }
        }

        for (auto &sig : port_sigs) {
            for (int i = 0; i < sig.size(); i++) {
                RTLIL::SigSpec s = sig.extract(big_endian ? sig.size() - 1 - i : i, 1);
                print_spice_net(f, s, neg, pos, ncpf, nc_counter);
            }
        }

        f << stringf(" %s\n", RTLIL::id2cstr(cell->type));
    }

    for (auto &conn : module->connections())
    for (int i = 0; i < conn.first.size(); i++) {
        f << stringf("V%d", conn_counter++);
        print_spice_net(f, conn.first.extract(i, 1), neg, pos, ncpf, nc_counter);
        print_spice_net(f, conn.second.extract(i, 1), neg, pos, ncpf, nc_counter);
        f << stringf(" DC 0\n");
    }
}

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USING_YOSYS_NAMESPACE static PRIVATE_NAMESPACE_BEGIN void print_spice_net ( std::ostream &  f, RTLIL::SigBit  s, std::string &  neg, std::string &  pos, std::string &  ncpf, int &  nc_counter  )

static

Definition at line 30 of file spice.cc.

{
    if (s.wire) {
        if (s.wire->width > 1)
            f << stringf(" %s[%d]", RTLIL::id2cstr(s.wire->name), s.offset);
        else
            f << stringf(" %s", RTLIL::id2cstr(s.wire->name));
    } else {
        if (s == RTLIL::State::S0)
            f << stringf(" %s", neg.c_str());
        else if (s == RTLIL::State::S1)
            f << stringf(" %s", pos.c_str());
        else
            f << stringf(" %s%d", ncpf.c_str(), nc_counter++);
    }
}

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Variable Documentation

SpiceBackend SpiceBackend