291 log_header(
"Executing SUBMOD pass (moving cells to submodules as requested).\n");
294 std::string opt_name;
297 for (argidx = 1; argidx <
args.size(); argidx++) {
298 if (
args[argidx] ==
"-name" && argidx+1 <
args.size()) {
299 opt_name =
args[++argidx];
306 if (opt_name.empty())
311 std::set<RTLIL::IdString> handled_modules;
314 while (did_something) {
315 did_something =
false;
316 std::vector<RTLIL::IdString> queued_modules;
317 for (
auto &mod_it : design->
modules_)
319 queued_modules.push_back(mod_it.first);
320 for (
auto &modname : queued_modules)
321 if (design->
modules_.count(modname) != 0) {
323 handled_modules.insert(modname);
324 did_something =
true;
333 for (
auto &mod_it : design->
modules_) {
338 module = mod_it.second;
341 log(
"Nothing selected -> do nothing.\n");
const char * c_str() const
bool selected_module(RTLIL::IdString mod_name) const
void log_header(const char *format,...)
USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN bool did_something
bool selected_whole_module(RTLIL::IdString mod_name) const
void log_cmd_error(const char *format,...)
std::map< RTLIL::IdString, RTLIL::Module * > modules_
static void call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::string command)
void log(const char *format,...)
void extra_args(std::vector< std::string > args, size_t argidx, RTLIL::Design *design, bool select=true)
static void call(RTLIL::Design *design, std::string command)