Inheritance diagram for EdifBackend:

Collaboration diagram for EdifBackend:

Public Member Functions
	EdifBackend ()

virtual void	help ()

virtual void	execute (std::ostream &f, std::string filename, std::vector< std::string > args, RTLIL::Design design)

virtual void	run_register ()

virtual void	execute (std::vector< std::string > args, RTLIL::Design *design) YS_OVERRIDE YS_FINAL

void	extra_args (std::ostream *&f, std::string &filename, std::vector< std::string > args, size_t argidx)

void	extra_args (std::vector< std::string > args, size_t argidx, RTLIL::Design *design, bool select=true)

pre_post_exec_state_t	pre_execute ()

void	post_execute (pre_post_exec_state_t state)

void	cmd_log_args (const std::vector< std::string > &args)

void	cmd_error (const std::vector< std::string > &args, size_t argidx, std::string msg)

Static Public Member Functions
static void	backend_call (RTLIL::Design design, std::ostream f, std::string filename, std::string command)

static void	backend_call (RTLIL::Design design, std::ostream f, std::string filename, std::vector< std::string > args)

static void	call (RTLIL::Design *design, std::string command)

static void	call (RTLIL::Design *design, std::vector< std::string > args)

static void	call_on_selection (RTLIL::Design *design, const RTLIL::Selection &selection, std::string command)

static void	call_on_selection (RTLIL::Design *design, const RTLIL::Selection &selection, std::vector< std::string > args)

static void	call_on_module (RTLIL::Design design, RTLIL::Module module, std::string command)

static void	call_on_module (RTLIL::Design design, RTLIL::Module module, std::vector< std::string > args)

static void	init_register ()

static void	done_register ()

Data Fields
std::string	backend_name

std::string	pass_name

std::string	short_help

int	call_counter

int64_t	runtime_ns

Pass *	next_queued_pass

Detailed Description

Definition at line 90 of file edif.cc.

Constructor & Destructor Documentation

EdifBackend::EdifBackend ( )

inline

Definition at line 91 of file edif.cc.

91 : Backend("edif", "write design to EDIF netlist file") { }

Backend::Backend

Backend(std::string name, std::string short_help="** document me **")

Definition: register.cc:410

Member Function Documentation

void Backend::backend_call	(	RTLIL::Design *	design,
		std::ostream *	f,
		std::string	filename,
		std::string	command
	)

staticinherited

Definition at line 479 of file register.cc.

 {
     std::vector<std::string> args;
     char *s = strdup(command.c_str());
     for (char *p = strtok(s, " \t\r\n"); p; p = strtok(NULL, " \t\r\n"))
         args.push_back(p);
     free(s);
     backend_call(design, f, filename, args);
 }

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void Backend::backend_call	(	RTLIL::Design *	design,
		std::ostream *	f,
		std::string	filename,
		std::vector< std::string >	args
	)

staticinherited

Definition at line 489 of file register.cc.

 {
     if (args.size() == 0)
         return;
     if (backend_register.count(args[0]) == 0)
         log_cmd_error("No such backend: %s\n", args[0].c_str());
 
     size_t orig_sel_stack_pos = design->selection_stack.size();
 
     if (f != NULL) {
         auto state = backend_register[args[0]]->pre_execute();
         backend_register[args[0]]->execute(f, filename, args, design);
         backend_register[args[0]]->post_execute(state);
     } else if (filename == "-") {
         std::ostream *f_cout = &std::cout;
         auto state = backend_register[args[0]]->pre_execute();
         backend_register[args[0]]->execute(f_cout, "<stdout>", args, design);
         backend_register[args[0]]->post_execute(state);
     } else {
         if (!filename.empty())
             args.push_back(filename);
         backend_register[args[0]]->execute(args, design);
     }
 
     while (design->selection_stack.size() > orig_sel_stack_pos)
         design->selection_stack.pop_back();
 
     design->check();
 }

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void Pass::call	(	RTLIL::Design *	design,
		std::string	command
	)

staticinherited

Definition at line 146 of file register.cc.

 {
     std::vector<std::string> args;
 
     std::string cmd_buf = command;
     std::string tok = next_token(cmd_buf, " \t\r\n");
 
     if (tok.empty() || tok[0] == '#')
         return;
 
     if (tok[0] == '!') {
         cmd_buf = command.substr(command.find('!') + 1);
         while (!cmd_buf.empty() && (cmd_buf.back() == ' ' || cmd_buf.back() == '\t' ||
                 cmd_buf.back() == '\r' || cmd_buf.back() == '\n'))
             cmd_buf.resize(cmd_buf.size()-1);
         log_header("Shell command: %s\n", cmd_buf.c_str());
         int retCode = run_command(cmd_buf);
         if (retCode != 0)
             log_cmd_error("Shell command returned error code %d.\n", retCode);
         return;
     }
 
     while (!tok.empty()) {
         if (tok == "#")
             break;
         if (tok.back() == ';') {
             int num_semikolon = 0;
             while (!tok.empty() && tok.back() == ';')
                 tok.resize(tok.size()-1), num_semikolon++;
             if (!tok.empty())
                 args.push_back(tok);
             call(design, args);
             args.clear();
             if (num_semikolon == 2)
                 call(design, "clean");
             if (num_semikolon == 3)
                 call(design, "clean -purge");
         } else
             args.push_back(tok);
         tok = next_token(cmd_buf, " \t\r\n");
     }
 
     call(design, args);
 }

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void Pass::call	(	RTLIL::Design *	design,
		std::vector< std::string >	args
	)

staticinherited

Definition at line 191 of file register.cc.

 {
     if (args.size() == 0 || args[0][0] == '#')
         return;
 
     if (echo_mode) {
         log("%s", create_prompt(design, 0));
         for (size_t i = 0; i < args.size(); i++)
             log("%s%s", i ? " " : "", args[i].c_str());
         log("\n");
     }
 
     if (pass_register.count(args[0]) == 0)
         log_cmd_error("No such command: %s (type 'help' for a command overview)\n", args[0].c_str());
 
     size_t orig_sel_stack_pos = design->selection_stack.size();
     auto state = pass_register[args[0]]->pre_execute();
     pass_register[args[0]]->execute(args, design);
     pass_register[args[0]]->post_execute(state);
     while (design->selection_stack.size() > orig_sel_stack_pos)
         design->selection_stack.pop_back();
 
     design->check();
 }

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void Pass::call_on_module	(	RTLIL::Design *	design,
		RTLIL::Module *	module,
		std::string	command
	)

staticinherited

Definition at line 240 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module = module->name.str();
     design->selection_stack.push_back(RTLIL::Selection(false));
     design->selection_stack.back().select(module);
 
     Pass::call(design, command);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

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void Pass::call_on_module	(	RTLIL::Design *	design,
		RTLIL::Module *	module,
		std::vector< std::string >	args
	)

staticinherited

Definition at line 253 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module = module->name.str();
     design->selection_stack.push_back(RTLIL::Selection(false));
     design->selection_stack.back().select(module);
 
     Pass::call(design, args);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

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void Pass::call_on_selection	(	RTLIL::Design *	design,
		const RTLIL::Selection &	selection,
		std::string	command
	)

staticinherited

Definition at line 216 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module.clear();
     design->selection_stack.push_back(selection);
 
     Pass::call(design, command);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

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void Pass::call_on_selection	(	RTLIL::Design *	design,
		const RTLIL::Selection &	selection,
		std::vector< std::string >	args
	)

staticinherited

Definition at line 228 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module.clear();
     design->selection_stack.push_back(selection);
 
     Pass::call(design, args);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

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void Pass::cmd_error	(	const std::vector< std::string > &	args,
		size_t	argidx,
		std::string	msg
	)

inherited

Definition at line 110 of file register.cc.

 {
     std::string command_text;
     int error_pos = 0;
 
     for (size_t i = 0; i < args.size(); i++) {
         if (i < argidx)
             error_pos += args[i].size() + 1;
         command_text = command_text + (command_text.empty() ? "" : " ") + args[i];
     }
 
     log("\nSyntax error in command `%s':\n", command_text.c_str());
     help();
 
     log_cmd_error("Command syntax error: %s\n> %s\n> %*s^\n",
             msg.c_str(), command_text.c_str(), error_pos, "");
 }

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void Pass::cmd_log_args ( const std::vector< std::string > & args )

inherited

Definition at line 100 of file register.cc.

 {
     if (args.size() <= 1)
         return;
     log("Full command line:");
     for (size_t i = 0; i < args.size(); i++)
         log(" %s", args[i].c_str());
     log("\n");
 }

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void Pass::done_register ( )

staticinherited

Definition at line 62 of file register.cc.

 {
     frontend_register.clear();
     pass_register.clear();
     backend_register.clear();
     log_assert(first_queued_pass == NULL);
 }

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void Backend::execute	(	std::vector< std::string >	args,
		RTLIL::Design *	design
	)

virtualinherited

Implements Pass.

Definition at line 429 of file register.cc.

 {
     std::ostream *f = NULL;
     auto state = pre_execute();
     execute(f, std::string(), args, design);
     post_execute(state);
     if (f != &std::cout)
         delete f;
 }

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virtual void EdifBackend::execute	(	std::ostream *&	f,
		std::string	filename,
		std::vector< std::string >	args,
		RTLIL::Design *	design
	)

inlinevirtual

Implements Backend.

Definition at line 109 of file edif.cc.

     {
         log_header("Executing EDIF backend.\n");
 
         std::string top_module_name;
         std::map<RTLIL::IdString, std::set<RTLIL::IdString>> lib_cell_ports;
         CellTypes ct(design);
         EdifNames edif_names;
 
         size_t argidx;
         for (argidx = 1; argidx < args.size(); argidx++)
         {
             if (args[argidx] == "-top" && argidx+1 < args.size()) {
                 top_module_name = args[++argidx];
                 continue;
             }
             break;
         }
         extra_args(f, filename, args, argidx);
 
         if (top_module_name.empty())
             for (auto & mod_it:design->modules_)
                 if (mod_it.second->get_bool_attribute("\\top"))
                     top_module_name = mod_it.first.str();
 
         for (auto module_it : design->modules_)
         {
             RTLIL::Module *module = module_it.second;
             if (module->get_bool_attribute("\\blackbox"))
                 continue;
 
             if (top_module_name.empty())
                 top_module_name = module->name.str();
 
             if (module->processes.size() != 0)
                 log_error("Found unmapped processes in module %s: unmapped processes are not supported in EDIF backend!\n", RTLIL::id2cstr(module->name));
             if (module->memories.size() != 0)
                 log_error("Found munmapped emories in module %s: unmapped memories are not supported in EDIF backend!\n", RTLIL::id2cstr(module->name));
 
             for (auto cell_it : module->cells_)
             {
                 RTLIL::Cell *cell = cell_it.second;
                 if (!design->modules_.count(cell->type) || design->modules_.at(cell->type)->get_bool_attribute("\\blackbox")) {
                     lib_cell_ports[cell->type];
                     for (auto p : cell->connections()) {
                         if (p.second.size() > 1)
                             log_error("Found multi-bit port %s on library cell %s.%s (%s): not supported in EDIF backend!\n",
                                     RTLIL::id2cstr(p.first), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
                         lib_cell_ports[cell->type].insert(p.first);
                     }
                 }
             }
         }
 
         if (top_module_name.empty())
             log_error("No module found in design!\n");
 
         *f << stringf("(edif %s\n", EDIF_DEF(top_module_name));
         *f << stringf("  (edifVersion 2 0 0)\n");
         *f << stringf("  (edifLevel 0)\n");
         *f << stringf("  (keywordMap (keywordLevel 0))\n");
         *f << stringf("  (comment \"Generated by %s\")\n", yosys_version_str);
 
         *f << stringf("  (external LIB\n");
         *f << stringf("    (edifLevel 0)\n");
         *f << stringf("    (technology (numberDefinition))\n");
 
         *f << stringf("    (cell GND\n");
         *f << stringf("      (cellType GENERIC)\n");
         *f << stringf("      (view VIEW_NETLIST\n");
         *f << stringf("        (viewType NETLIST)\n");
         *f << stringf("        (interface (port G (direction OUTPUT)))\n");
         *f << stringf("      )\n");
         *f << stringf("    )\n");
 
         *f << stringf("    (cell VCC\n");
         *f << stringf("      (cellType GENERIC)\n");
         *f << stringf("      (view VIEW_NETLIST\n");
         *f << stringf("        (viewType NETLIST)\n");
         *f << stringf("        (interface (port P (direction OUTPUT)))\n");
         *f << stringf("      )\n");
         *f << stringf("    )\n");
 
         for (auto &cell_it : lib_cell_ports) {
             *f << stringf("    (cell %s\n", EDIF_DEF(cell_it.first));
             *f << stringf("      (cellType GENERIC)\n");
             *f << stringf("      (view VIEW_NETLIST\n");
             *f << stringf("        (viewType NETLIST)\n");
             *f << stringf("        (interface\n");
             for (auto &port_it : cell_it.second) {
                 const char *dir = "INOUT";
                 if (ct.cell_known(cell_it.first)) {
                     if (!ct.cell_output(cell_it.first, port_it))
                         dir = "INPUT";
                     else if (!ct.cell_input(cell_it.first, port_it))
                         dir = "OUTPUT";
                 }
                 *f << stringf("          (port %s (direction %s))\n", EDIF_DEF(port_it), dir);
             }
             *f << stringf("        )\n");
             *f << stringf("      )\n");
             *f << stringf("    )\n");
         }
         *f << stringf("  )\n");
 
         std::vector<RTLIL::Module*> sorted_modules;
 
         // extract module dependencies
         std::map<RTLIL::Module*, std::set<RTLIL::Module*>> module_deps;
         for (auto &mod_it : design->modules_) {
             module_deps[mod_it.second] = std::set<RTLIL::Module*>();
             for (auto &cell_it : mod_it.second->cells_)
                 if (design->modules_.count(cell_it.second->type) > 0)
                     module_deps[mod_it.second].insert(design->modules_.at(cell_it.second->type));
         }
 
         // simple good-enough topological sort
         // (O(n*m) on n elements and depth m)
         while (module_deps.size() > 0) {
             size_t sorted_modules_idx = sorted_modules.size();
             for (auto &it : module_deps) {
                 for (auto &dep : it.second)
                     if (module_deps.count(dep) > 0)
                         goto not_ready_yet;
                 // log("Next in topological sort: %s\n", RTLIL::id2cstr(it.first->name));
                 sorted_modules.push_back(it.first);
             not_ready_yet:;
             }
             if (sorted_modules_idx == sorted_modules.size())
                 log_error("Cyclic dependency between modules found! Cycle includes module %s.\n", RTLIL::id2cstr(module_deps.begin()->first->name));
             while (sorted_modules_idx < sorted_modules.size())
                 module_deps.erase(sorted_modules.at(sorted_modules_idx++));
         }
 
 
         *f << stringf("  (library DESIGN\n");
         *f << stringf("    (edifLevel 0)\n");
         *f << stringf("    (technology (numberDefinition))\n");
         for (auto module : sorted_modules)
         {
             if (module->get_bool_attribute("\\blackbox"))
                 continue;
 
             SigMap sigmap(module);
             std::map<RTLIL::SigSpec, std::set<std::string>> net_join_db;
 
             *f << stringf("    (cell %s\n", EDIF_DEF(module->name));
             *f << stringf("      (cellType GENERIC)\n");
             *f << stringf("      (view VIEW_NETLIST\n");
             *f << stringf("        (viewType NETLIST)\n");
             *f << stringf("        (interface\n");
             for (auto &wire_it : module->wires_) {
                 RTLIL::Wire *wire = wire_it.second;
                 if (wire->port_id == 0)
                     continue;
                 const char *dir = "INOUT";
                 if (!wire->port_output)
                     dir = "INPUT";
                 else if (!wire->port_input)
                     dir = "OUTPUT";
                 if (wire->width == 1) {
                     *f << stringf("          (port %s (direction %s))\n", EDIF_DEF(wire->name), dir);
                     RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire));
                     net_join_db[sig].insert(stringf("(portRef %s)", EDIF_REF(wire->name)));
                 } else {
                     *f << stringf("          (port (array %s %d) (direction %s))\n", EDIF_DEF(wire->name), wire->width, dir);
                     for (int i = 0; i < wire->width; i++) {
                         RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire, i));
                         net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), i));
                     }
                 }
             }
             *f << stringf("        )\n");
             *f << stringf("        (contents\n");
             *f << stringf("          (instance GND (viewRef VIEW_NETLIST (cellRef GND (libraryRef LIB))))\n");
             *f << stringf("          (instance VCC (viewRef VIEW_NETLIST (cellRef VCC (libraryRef LIB))))\n");
             for (auto &cell_it : module->cells_) {
                 RTLIL::Cell *cell = cell_it.second;
                 *f << stringf("          (instance %s\n", EDIF_DEF(cell->name));
                 *f << stringf("            (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_REF(cell->type),
                         lib_cell_ports.count(cell->type) > 0 ? " (libraryRef LIB)" : "");
                 for (auto &p : cell->parameters)
                     if ((p.second.flags & RTLIL::CONST_FLAG_STRING) != 0)
                         *f << stringf("\n            (property %s (string \"%s\"))", EDIF_DEF(p.first), p.second.decode_string().c_str());
                     else if (p.second.bits.size() <= 32 && RTLIL::SigSpec(p.second).is_fully_def())
                         *f << stringf("\n            (property %s (integer %u))", EDIF_DEF(p.first), p.second.as_int());
                     else {
                         std::string hex_string = "";
                         for (size_t i = 0; i < p.second.bits.size(); i += 4) {
                             int digit_value = 0;
                             if (i+0 < p.second.bits.size() && p.second.bits.at(i+0) == RTLIL::State::S1) digit_value |= 1;
                             if (i+1 < p.second.bits.size() && p.second.bits.at(i+1) == RTLIL::State::S1) digit_value |= 2;
                             if (i+2 < p.second.bits.size() && p.second.bits.at(i+2) == RTLIL::State::S1) digit_value |= 4;
                             if (i+3 < p.second.bits.size() && p.second.bits.at(i+3) == RTLIL::State::S1) digit_value |= 8;
                             char digit_str[2] = { "0123456789abcdef"[digit_value], 0 };
                             hex_string = std::string(digit_str) + hex_string;
                         }
                         *f << stringf("\n            (property %s (string \"%s\"))", EDIF_DEF(p.first), hex_string.c_str());
                     }
                 *f << stringf(")\n");
                 for (auto &p : cell->connections()) {
                     RTLIL::SigSpec sig = sigmap(p.second);
                     for (int i = 0; i < GetSize(sig); i++)
                         if (sig.size() == 1)
                             net_join_db[sig[i]].insert(stringf("(portRef %s (instanceRef %s))", EDIF_REF(p.first), EDIF_REF(cell->name)));
                         else
                             net_join_db[sig[i]].insert(stringf("(portRef (member %s %d) (instanceRef %s))", EDIF_REF(p.first), i, EDIF_REF(cell->name)));
                 }
             }
             for (auto &it : net_join_db) {
                 RTLIL::SigBit sig = it.first;
                 if (sig.wire == NULL && sig != RTLIL::State::S0 && sig != RTLIL::State::S1)
                     continue;
                 std::string netname = log_signal(sig);
                 for (size_t i = 0; i < netname.size(); i++)
                     if (netname[i] == ' ' || netname[i] == '\\')
                         netname.erase(netname.begin() + i--);
                 *f << stringf("          (net %s (joined\n", EDIF_DEF(netname));
                 for (auto &ref : it.second)
                     *f << stringf("            %s\n", ref.c_str());
                 if (sig.wire == NULL) {
                     if (sig == RTLIL::State::S0)
                         *f << stringf("            (portRef G (instanceRef GND))\n");
                     if (sig == RTLIL::State::S1)
                         *f << stringf("            (portRef P (instanceRef VCC))\n");
                 }
                 *f << stringf("          ))\n");
             }
             *f << stringf("        )\n");
             *f << stringf("      )\n");
             *f << stringf("    )\n");
         }
         *f << stringf("  )\n");
 
         *f << stringf("  (design %s\n", EDIF_DEF(top_module_name));
         *f << stringf("    (cellRef %s (libraryRef DESIGN))\n", EDIF_REF(top_module_name));
         *f << stringf("  )\n");
 
         *f << stringf(")\n");
     }

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void Pass::extra_args	(	std::vector< std::string >	args,
		size_t	argidx,
		RTLIL::Design *	design,
		bool	select = `true`
	)

inherited

Definition at line 128 of file register.cc.

 {
     for (; argidx < args.size(); argidx++)
     {
         std::string arg = args[argidx];
 
         if (arg.substr(0, 1) == "-")
             cmd_error(args, argidx, "Unknown option or option in arguments.");
 
         if (!select)
             cmd_error(args, argidx, "Extra argument.");
 
         handle_extra_select_args(this, args, argidx, args.size(), design);
         break;
     }
     // cmd_log_args(args);
 }

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void Backend::extra_args	(	std::ostream *&	f,
		std::string &	filename,
		std::vector< std::string >	args,
		size_t	argidx
	)

inherited

Definition at line 439 of file register.cc.

 {
     bool called_with_fp = f != NULL;
 
     for (; argidx < args.size(); argidx++)
     {
         std::string arg = args[argidx];
 
         if (arg.substr(0, 1) == "-" && arg != "-")
             cmd_error(args, argidx, "Unknown option or option in arguments.");
         if (f != NULL)
             cmd_error(args, argidx, "Extra filename argument in direct file mode.");
 
         if (arg == "-") {
             filename = "<stdout>";
             f = &std::cout;
             continue;
         }
 
         filename = arg;
         std::ofstream *ff = new std::ofstream;
         ff->open(filename.c_str(), std::ofstream::trunc);
         if (ff->fail()) {
             delete ff;
             log_cmd_error("Can't open output file `%s' for writing: %s\n", filename.c_str(), strerror(errno));
         }
         f = ff;
     }
 
     if (called_with_fp)
         args.push_back(filename);
     args[0] = pass_name;
     // cmd_log_args(args);
 
     if (f == NULL) {
         filename = "<stdout>";
         f = &std::cout;
     }
 }

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virtual void EdifBackend::help ( )

inlinevirtual

Reimplemented from Pass.

Definition at line 92 of file edif.cc.

     {
         //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
         log("\n");
         log("    write_edif [options] [filename]\n");
         log("\n");
         log("Write the current design to an EDIF netlist file.\n");
         log("\n");
         log("    -top top_module\n");
         log("        set the specified module as design top module\n");
         log("\n");
         log("Unfortunately there are different \"flavors\" of the EDIF file format. This\n");
         log("command generates EDIF files for the Xilinx place&route tools. It might be\n");
         log("necessary to make small modifications to this command when a different tool\n");
         log("is targeted.\n");
         log("\n");
     }

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void Pass::init_register ( )

staticinherited

Definition at line 54 of file register.cc.

 {
     while (first_queued_pass) {
         first_queued_pass->run_register();
         first_queued_pass = first_queued_pass->next_queued_pass;
     }
 }

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void Pass::post_execute ( Pass::pre_post_exec_state_t state )

inherited

Definition at line 84 of file register.cc.

 {
     int64_t time_ns = PerformanceTimer::query() - state.begin_ns;
     runtime_ns += time_ns;
     current_pass = state.parent_pass;
     if (current_pass)
         current_pass->runtime_ns -= time_ns;
 }

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Pass::pre_post_exec_state_t Pass::pre_execute ( )

inherited

Definition at line 74 of file register.cc.

 {
     pre_post_exec_state_t state;
     call_counter++;
     state.begin_ns = PerformanceTimer::query();
     state.parent_pass = current_pass;
     current_pass = this;
     return state;
 }

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void Backend::run_register ( )

virtualinherited

Reimplemented from Pass.

Definition at line 416 of file register.cc.

 {
     log_assert(pass_register.count(pass_name) == 0);
     pass_register[pass_name] = this;
 
     log_assert(backend_register.count(backend_name) == 0);
     backend_register[backend_name] = this;
 }

Field Documentation

std::string Backend::backend_name

inherited

Definition at line 88 of file register.h.

int Pass::call_counter

inherited

Definition at line 36 of file register.h.

Pass* Pass::next_queued_pass

inherited

Definition at line 60 of file register.h.

std::string Pass::pass_name

inherited

Definition at line 29 of file register.h.

int64_t Pass::runtime_ns

inherited

Definition at line 37 of file register.h.

std::string Pass::short_help

inherited

Definition at line 29 of file register.h.

The documentation for this struct was generated from the following file:

edif.cc

Public Member Functions

Static Public Member Functions

Data Fields

Detailed Description

Constructor & Destructor Documentation

Member Function Documentation

Field Documentation