Inheritance diagram for IntersynthBackend:

Collaboration diagram for IntersynthBackend:

Public Member Functions
	IntersynthBackend ()

virtual void	help ()

virtual void	execute (std::ostream &f, std::string filename, std::vector< std::string > args, RTLIL::Design design)

virtual void	run_register ()

virtual void	execute (std::vector< std::string > args, RTLIL::Design *design) YS_OVERRIDE YS_FINAL

void	extra_args (std::ostream *&f, std::string &filename, std::vector< std::string > args, size_t argidx)

void	extra_args (std::vector< std::string > args, size_t argidx, RTLIL::Design *design, bool select=true)

pre_post_exec_state_t	pre_execute ()

void	post_execute (pre_post_exec_state_t state)

void	cmd_log_args (const std::vector< std::string > &args)

void	cmd_error (const std::vector< std::string > &args, size_t argidx, std::string msg)

Static Public Member Functions
static void	backend_call (RTLIL::Design design, std::ostream f, std::string filename, std::string command)

static void	backend_call (RTLIL::Design design, std::ostream f, std::string filename, std::vector< std::string > args)

static void	call (RTLIL::Design *design, std::string command)

static void	call (RTLIL::Design *design, std::vector< std::string > args)

static void	call_on_selection (RTLIL::Design *design, const RTLIL::Selection &selection, std::string command)

static void	call_on_selection (RTLIL::Design *design, const RTLIL::Selection &selection, std::vector< std::string > args)

static void	call_on_module (RTLIL::Design design, RTLIL::Module module, std::string command)

static void	call_on_module (RTLIL::Design design, RTLIL::Module module, std::vector< std::string > args)

static void	init_register ()

static void	done_register ()

Data Fields
std::string	backend_name

std::string	pass_name

std::string	short_help

int	call_counter

int64_t	runtime_ns

Pass *	next_queued_pass

Detailed Description

Definition at line 47 of file intersynth.cc.

Constructor & Destructor Documentation

IntersynthBackend::IntersynthBackend ( )

inline

Definition at line 48 of file intersynth.cc.

48 : Backend("intersynth", "write design to InterSynth netlist file") { }

Backend::Backend

Backend(std::string name, std::string short_help="** document me **")

Definition: register.cc:410

Member Function Documentation

void Backend::backend_call	(	RTLIL::Design *	design,
		std::ostream *	f,
		std::string	filename,
		std::string	command
	)

staticinherited

Definition at line 479 of file register.cc.

 {
     std::vector<std::string> args;
     char *s = strdup(command.c_str());
     for (char *p = strtok(s, " \t\r\n"); p; p = strtok(NULL, " \t\r\n"))
         args.push_back(p);
     free(s);
     backend_call(design, f, filename, args);
 }

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void Backend::backend_call	(	RTLIL::Design *	design,
		std::ostream *	f,
		std::string	filename,
		std::vector< std::string >	args
	)

staticinherited

Definition at line 489 of file register.cc.

 {
     if (args.size() == 0)
         return;
     if (backend_register.count(args[0]) == 0)
         log_cmd_error("No such backend: %s\n", args[0].c_str());
 
     size_t orig_sel_stack_pos = design->selection_stack.size();
 
     if (f != NULL) {
         auto state = backend_register[args[0]]->pre_execute();
         backend_register[args[0]]->execute(f, filename, args, design);
         backend_register[args[0]]->post_execute(state);
     } else if (filename == "-") {
         std::ostream *f_cout = &std::cout;
         auto state = backend_register[args[0]]->pre_execute();
         backend_register[args[0]]->execute(f_cout, "<stdout>", args, design);
         backend_register[args[0]]->post_execute(state);
     } else {
         if (!filename.empty())
             args.push_back(filename);
         backend_register[args[0]]->execute(args, design);
     }
 
     while (design->selection_stack.size() > orig_sel_stack_pos)
         design->selection_stack.pop_back();
 
     design->check();
 }

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void Pass::call	(	RTLIL::Design *	design,
		std::string	command
	)

staticinherited

Definition at line 146 of file register.cc.

 {
     std::vector<std::string> args;
 
     std::string cmd_buf = command;
     std::string tok = next_token(cmd_buf, " \t\r\n");
 
     if (tok.empty() || tok[0] == '#')
         return;
 
     if (tok[0] == '!') {
         cmd_buf = command.substr(command.find('!') + 1);
         while (!cmd_buf.empty() && (cmd_buf.back() == ' ' || cmd_buf.back() == '\t' ||
                 cmd_buf.back() == '\r' || cmd_buf.back() == '\n'))
             cmd_buf.resize(cmd_buf.size()-1);
         log_header("Shell command: %s\n", cmd_buf.c_str());
         int retCode = run_command(cmd_buf);
         if (retCode != 0)
             log_cmd_error("Shell command returned error code %d.\n", retCode);
         return;
     }
 
     while (!tok.empty()) {
         if (tok == "#")
             break;
         if (tok.back() == ';') {
             int num_semikolon = 0;
             while (!tok.empty() && tok.back() == ';')
                 tok.resize(tok.size()-1), num_semikolon++;
             if (!tok.empty())
                 args.push_back(tok);
             call(design, args);
             args.clear();
             if (num_semikolon == 2)
                 call(design, "clean");
             if (num_semikolon == 3)
                 call(design, "clean -purge");
         } else
             args.push_back(tok);
         tok = next_token(cmd_buf, " \t\r\n");
     }
 
     call(design, args);
 }

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void Pass::call	(	RTLIL::Design *	design,
		std::vector< std::string >	args
	)

staticinherited

Definition at line 191 of file register.cc.

 {
     if (args.size() == 0 || args[0][0] == '#')
         return;
 
     if (echo_mode) {
         log("%s", create_prompt(design, 0));
         for (size_t i = 0; i < args.size(); i++)
             log("%s%s", i ? " " : "", args[i].c_str());
         log("\n");
     }
 
     if (pass_register.count(args[0]) == 0)
         log_cmd_error("No such command: %s (type 'help' for a command overview)\n", args[0].c_str());
 
     size_t orig_sel_stack_pos = design->selection_stack.size();
     auto state = pass_register[args[0]]->pre_execute();
     pass_register[args[0]]->execute(args, design);
     pass_register[args[0]]->post_execute(state);
     while (design->selection_stack.size() > orig_sel_stack_pos)
         design->selection_stack.pop_back();
 
     design->check();
 }

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void Pass::call_on_module	(	RTLIL::Design *	design,
		RTLIL::Module *	module,
		std::string	command
	)

staticinherited

Definition at line 240 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module = module->name.str();
     design->selection_stack.push_back(RTLIL::Selection(false));
     design->selection_stack.back().select(module);
 
     Pass::call(design, command);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

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void Pass::call_on_module	(	RTLIL::Design *	design,
		RTLIL::Module *	module,
		std::vector< std::string >	args
	)

staticinherited

Definition at line 253 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module = module->name.str();
     design->selection_stack.push_back(RTLIL::Selection(false));
     design->selection_stack.back().select(module);
 
     Pass::call(design, args);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

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void Pass::call_on_selection	(	RTLIL::Design *	design,
		const RTLIL::Selection &	selection,
		std::string	command
	)

staticinherited

Definition at line 216 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module.clear();
     design->selection_stack.push_back(selection);
 
     Pass::call(design, command);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

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void Pass::call_on_selection	(	RTLIL::Design *	design,
		const RTLIL::Selection &	selection,
		std::vector< std::string >	args
	)

staticinherited

Definition at line 228 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module.clear();
     design->selection_stack.push_back(selection);
 
     Pass::call(design, args);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

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void Pass::cmd_error	(	const std::vector< std::string > &	args,
		size_t	argidx,
		std::string	msg
	)

inherited

Definition at line 110 of file register.cc.

 {
     std::string command_text;
     int error_pos = 0;
 
     for (size_t i = 0; i < args.size(); i++) {
         if (i < argidx)
             error_pos += args[i].size() + 1;
         command_text = command_text + (command_text.empty() ? "" : " ") + args[i];
     }
 
     log("\nSyntax error in command `%s':\n", command_text.c_str());
     help();
 
     log_cmd_error("Command syntax error: %s\n> %s\n> %*s^\n",
             msg.c_str(), command_text.c_str(), error_pos, "");
 }

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void Pass::cmd_log_args ( const std::vector< std::string > & args )

inherited

Definition at line 100 of file register.cc.

 {
     if (args.size() <= 1)
         return;
     log("Full command line:");
     for (size_t i = 0; i < args.size(); i++)
         log(" %s", args[i].c_str());
     log("\n");
 }

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void Pass::done_register ( )

staticinherited

Definition at line 62 of file register.cc.

 {
     frontend_register.clear();
     pass_register.clear();
     backend_register.clear();
     log_assert(first_queued_pass == NULL);
 }

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virtual void IntersynthBackend::execute	(	std::ostream *&	f,
		std::string	filename,
		std::vector< std::string >	args,
		RTLIL::Design *	design
	)

inlinevirtual

Implements Backend.

Definition at line 74 of file intersynth.cc.

     {
         log_header("Executing INTERSYNTH backend.\n");
         log_push();
 
         std::vector<std::string> libfiles;
         std::vector<RTLIL::Design*> libs;
         bool flag_notypes = false;
         bool selected = false;
 
         size_t argidx;
         for (argidx = 1; argidx < args.size(); argidx++)
         {
             if (args[argidx] == "-notypes") {
                 flag_notypes = true;
                 continue;
             }
             if (args[argidx] == "-lib" && argidx+1 < args.size()) {
                 libfiles.push_back(args[++argidx]);
                 continue;
             }
             if (args[argidx] == "-selected") {
                 selected = true;
                 continue;
             }
             break;
         }
         extra_args(f, filename, args, argidx);
 
         log("Output filename: %s\n", filename.c_str());
 
         for (auto filename : libfiles) {
             std::ifstream f;
             f.open(filename.c_str());
             if (f.fail())
                 log_error("Can't open lib file `%s'.\n", filename.c_str());
             RTLIL::Design *lib = new RTLIL::Design;
             Frontend::frontend_call(lib, &f, filename, (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") ? "ilang" : "verilog");
             libs.push_back(lib);
         }
 
         if (libs.size() > 0)
             log_header("Continuing INTERSYNTH backend.\n");
 
         std::set<std::string> conntypes_code, celltypes_code;
         std::string netlists_code;
         CellTypes ct(design);
 
         for (auto lib : libs)
             ct.setup_design(lib);
 
         for (auto module_it : design->modules_)
         {
             RTLIL::Module *module = module_it.second;
             SigMap sigmap(module);
 
             if (module->get_bool_attribute("\\blackbox"))
                 continue;
             if (module->memories.size() == 0 && module->processes.size() == 0 && module->cells_.size() == 0)
                 continue;
 
             if (selected && !design->selected_whole_module(module->name)) {
                 if (design->selected_module(module->name))
                     log_cmd_error("Can't handle partially selected module %s!\n", RTLIL::id2cstr(module->name));
                 continue;
             }
 
             log("Generating netlist %s.\n", RTLIL::id2cstr(module->name));
 
             if (module->memories.size() != 0 || module->processes.size() != 0)
                 log_error("Can't generate a netlist for a module with unprocessed memories or processes!\n");
 
             std::set<std::string> constcells_code;
             netlists_code += stringf("# Netlist of module %s\n", RTLIL::id2cstr(module->name));
             netlists_code += stringf("netlist %s\n", RTLIL::id2cstr(module->name));
 
             // Module Ports: "std::set<string> celltypes_code" prevents duplicate top level ports
             for (auto wire_it : module->wires_) {
                 RTLIL::Wire *wire = wire_it.second;
                 if (wire->port_input || wire->port_output) {
                     celltypes_code.insert(stringf("celltype !%s b%d %sPORT\n" "%s %s %d %s PORT\n",
                             RTLIL::id2cstr(wire->name), wire->width, wire->port_input ? "*" : "",
                             wire->port_input ? "input" : "output", RTLIL::id2cstr(wire->name), wire->width, RTLIL::id2cstr(wire->name)));
                     netlists_code += stringf("node %s %s PORT %s\n", RTLIL::id2cstr(wire->name), RTLIL::id2cstr(wire->name),
                             netname(conntypes_code, celltypes_code, constcells_code, sigmap(wire)).c_str());
                 }
             }
 
             // Submodules: "std::set<string> celltypes_code" prevents duplicate cell types 
             for (auto cell_it : module->cells_)
             {
                 RTLIL::Cell *cell = cell_it.second;
                 std::string celltype_code, node_code;
 
                 if (!ct.cell_known(cell->type))
                     log_error("Found unknown cell type %s in module!\n", RTLIL::id2cstr(cell->type));
 
                 celltype_code = stringf("celltype %s", RTLIL::id2cstr(cell->type));
                 node_code = stringf("node %s %s", RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
                 for (auto &port : cell->connections()) {
                     RTLIL::SigSpec sig = sigmap(port.second);
                     if (sig.size() != 0) {
                         conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.size(), sig.size(), sig.size()));
                         celltype_code += stringf(" b%d %s%s", sig.size(), ct.cell_output(cell->type, port.first) ? "*" : "", RTLIL::id2cstr(port.first));
                         node_code += stringf(" %s %s", RTLIL::id2cstr(port.first), netname(conntypes_code, celltypes_code, constcells_code, sig).c_str());
                     }
                 }
                 for (auto &param : cell->parameters) {
                     celltype_code += stringf(" cfg:%d %s", int(param.second.bits.size()), RTLIL::id2cstr(param.first));
                     if (param.second.bits.size() != 32) {
                         node_code += stringf(" %s '", RTLIL::id2cstr(param.first));
                         for (int i = param.second.bits.size()-1; i >= 0; i--)
                             node_code += param.second.bits[i] == RTLIL::S1 ? "1" : "0";
                     } else
                         node_code += stringf(" %s 0x%x", RTLIL::id2cstr(param.first), param.second.as_int());
                 }
 
                 celltypes_code.insert(celltype_code + "\n");
                 netlists_code += node_code + "\n";
             }
 
             if (constcells_code.size() > 0)
               netlists_code += "# constant cells\n";
             for (auto code : constcells_code)
                 netlists_code += code;
             netlists_code += "\n";
         }
 
         if (!flag_notypes) {
             *f << stringf("### Connection Types\n");
             for (auto code : conntypes_code)
                 *f << stringf("%s", code.c_str());
             *f << stringf("\n### Cell Types\n");
             for (auto code : celltypes_code)
                 *f << stringf("%s", code.c_str());
         }
         *f << stringf("\n### Netlists\n");
         *f << stringf("%s", netlists_code.c_str());
 
         for (auto lib : libs)
             delete lib;
 
         log_pop();
     }

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void Backend::execute	(	std::vector< std::string >	args,
		RTLIL::Design *	design
	)

virtualinherited

Implements Pass.

Definition at line 429 of file register.cc.

 {
     std::ostream *f = NULL;
     auto state = pre_execute();
     execute(f, std::string(), args, design);
     post_execute(state);
     if (f != &std::cout)
         delete f;
 }

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void Pass::extra_args	(	std::vector< std::string >	args,
		size_t	argidx,
		RTLIL::Design *	design,
		bool	select = `true`
	)

inherited

Definition at line 128 of file register.cc.

 {
     for (; argidx < args.size(); argidx++)
     {
         std::string arg = args[argidx];
 
         if (arg.substr(0, 1) == "-")
             cmd_error(args, argidx, "Unknown option or option in arguments.");
 
         if (!select)
             cmd_error(args, argidx, "Extra argument.");
 
         handle_extra_select_args(this, args, argidx, args.size(), design);
         break;
     }
     // cmd_log_args(args);
 }

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void Backend::extra_args	(	std::ostream *&	f,
		std::string &	filename,
		std::vector< std::string >	args,
		size_t	argidx
	)

inherited

Definition at line 439 of file register.cc.

 {
     bool called_with_fp = f != NULL;
 
     for (; argidx < args.size(); argidx++)
     {
         std::string arg = args[argidx];
 
         if (arg.substr(0, 1) == "-" && arg != "-")
             cmd_error(args, argidx, "Unknown option or option in arguments.");
         if (f != NULL)
             cmd_error(args, argidx, "Extra filename argument in direct file mode.");
 
         if (arg == "-") {
             filename = "<stdout>";
             f = &std::cout;
             continue;
         }
 
         filename = arg;
         std::ofstream *ff = new std::ofstream;
         ff->open(filename.c_str(), std::ofstream::trunc);
         if (ff->fail()) {
             delete ff;
             log_cmd_error("Can't open output file `%s' for writing: %s\n", filename.c_str(), strerror(errno));
         }
         f = ff;
     }
 
     if (called_with_fp)
         args.push_back(filename);
     args[0] = pass_name;
     // cmd_log_args(args);
 
     if (f == NULL) {
         filename = "<stdout>";
         f = &std::cout;
     }
 }

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virtual void IntersynthBackend::help ( )

inlinevirtual

Reimplemented from Pass.

Definition at line 49 of file intersynth.cc.

     {
         //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
         log("\n");
         log("    write_intersynth [options] [filename]\n");
         log("\n");
         log("Write the current design to an 'intersynth' netlist file. InterSynth is\n");
         log("a tool for Coarse-Grain Example-Driven Interconnect Synthesis.\n");
         log("\n");
         log("    -notypes\n");
         log("        do not generate celltypes and conntypes commands. i.e. just output\n");
         log("        the netlists. this is used for postsilicon synthesis.\n");
         log("\n");
         log("    -lib <verilog_or_ilang_file>\n");
         log("        Use the specified library file for determining whether cell ports are\n");
         log("        inputs or outputs. This option can be used multiple times to specify\n");
         log("        more than one library.\n");
         log("\n");
         log("    -selected\n");
         log("        only write selected modules. modules must be selected entirely or\n");
         log("        not at all.\n");
         log("\n");
         log("http://www.clifford.at/intersynth/\n");
         log("\n");
     }

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void Pass::init_register ( )

staticinherited

Definition at line 54 of file register.cc.

 {
     while (first_queued_pass) {
         first_queued_pass->run_register();
         first_queued_pass = first_queued_pass->next_queued_pass;
     }
 }

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void Pass::post_execute ( Pass::pre_post_exec_state_t state )

inherited

Definition at line 84 of file register.cc.

 {
     int64_t time_ns = PerformanceTimer::query() - state.begin_ns;
     runtime_ns += time_ns;
     current_pass = state.parent_pass;
     if (current_pass)
         current_pass->runtime_ns -= time_ns;
 }

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Pass::pre_post_exec_state_t Pass::pre_execute ( )

inherited

Definition at line 74 of file register.cc.

 {
     pre_post_exec_state_t state;
     call_counter++;
     state.begin_ns = PerformanceTimer::query();
     state.parent_pass = current_pass;
     current_pass = this;
     return state;
 }

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void Backend::run_register ( )

virtualinherited

Reimplemented from Pass.

Definition at line 416 of file register.cc.

 {
     log_assert(pass_register.count(pass_name) == 0);
     pass_register[pass_name] = this;
 
     log_assert(backend_register.count(backend_name) == 0);
     backend_register[backend_name] = this;
 }

Field Documentation

std::string Backend::backend_name

inherited

Definition at line 88 of file register.h.

int Pass::call_counter

inherited

Definition at line 36 of file register.h.

Pass* Pass::next_queued_pass

inherited

Definition at line 60 of file register.h.

std::string Pass::pass_name

inherited

Definition at line 29 of file register.h.

int64_t Pass::runtime_ns

inherited

Definition at line 37 of file register.h.

std::string Pass::short_help

inherited

Definition at line 29 of file register.h.

The documentation for this struct was generated from the following file:

intersynth.cc

Public Member Functions

Static Public Member Functions

Data Fields

Detailed Description

Constructor & Destructor Documentation

Member Function Documentation

Field Documentation