Inheritance diagram for HierarchyPass:

Collaboration diagram for HierarchyPass:

Public Member Functions
	HierarchyPass ()

virtual void	help ()

virtual void	execute (std::vector< std::string > args, RTLIL::Design *design)

pre_post_exec_state_t	pre_execute ()

void	post_execute (pre_post_exec_state_t state)

void	cmd_log_args (const std::vector< std::string > &args)

void	cmd_error (const std::vector< std::string > &args, size_t argidx, std::string msg)

void	extra_args (std::vector< std::string > args, size_t argidx, RTLIL::Design *design, bool select=true)

virtual void	run_register ()

Static Public Member Functions
static void	call (RTLIL::Design *design, std::string command)

static void	call (RTLIL::Design *design, std::vector< std::string > args)

static void	call_on_selection (RTLIL::Design *design, const RTLIL::Selection &selection, std::string command)

static void	call_on_selection (RTLIL::Design *design, const RTLIL::Selection &selection, std::vector< std::string > args)

static void	call_on_module (RTLIL::Design design, RTLIL::Module module, std::string command)

static void	call_on_module (RTLIL::Design design, RTLIL::Module module, std::vector< std::string > args)

static void	init_register ()

static void	done_register ()

Data Fields
std::string	pass_name

std::string	short_help

int	call_counter

int64_t	runtime_ns

Pass *	next_queued_pass

Detailed Description

Definition at line 309 of file hierarchy.cc.

Constructor & Destructor Documentation

HierarchyPass::HierarchyPass ( )

inline

Definition at line 310 of file hierarchy.cc.

310 : Pass("hierarchy", "check, expand and clean up design hierarchy") { }

Pass::Pass

Pass(std::string name, std::string short_help="** document me **")

Definition: register.cc:40

Member Function Documentation

void Pass::call	(	RTLIL::Design *	design,
		std::string	command
	)

staticinherited

Definition at line 146 of file register.cc.

 {
     std::vector<std::string> args;
 
     std::string cmd_buf = command;
     std::string tok = next_token(cmd_buf, " \t\r\n");
 
     if (tok.empty() || tok[0] == '#')
         return;
 
     if (tok[0] == '!') {
         cmd_buf = command.substr(command.find('!') + 1);
         while (!cmd_buf.empty() && (cmd_buf.back() == ' ' || cmd_buf.back() == '\t' ||
                 cmd_buf.back() == '\r' || cmd_buf.back() == '\n'))
             cmd_buf.resize(cmd_buf.size()-1);
         log_header("Shell command: %s\n", cmd_buf.c_str());
         int retCode = run_command(cmd_buf);
         if (retCode != 0)
             log_cmd_error("Shell command returned error code %d.\n", retCode);
         return;
     }
 
     while (!tok.empty()) {
         if (tok == "#")
             break;
         if (tok.back() == ';') {
             int num_semikolon = 0;
             while (!tok.empty() && tok.back() == ';')
                 tok.resize(tok.size()-1), num_semikolon++;
             if (!tok.empty())
                 args.push_back(tok);
             call(design, args);
             args.clear();
             if (num_semikolon == 2)
                 call(design, "clean");
             if (num_semikolon == 3)
                 call(design, "clean -purge");
         } else
             args.push_back(tok);
         tok = next_token(cmd_buf, " \t\r\n");
     }
 
     call(design, args);
 }

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void Pass::call	(	RTLIL::Design *	design,
		std::vector< std::string >	args
	)

staticinherited

Definition at line 191 of file register.cc.

 {
     if (args.size() == 0 || args[0][0] == '#')
         return;
 
     if (echo_mode) {
         log("%s", create_prompt(design, 0));
         for (size_t i = 0; i < args.size(); i++)
             log("%s%s", i ? " " : "", args[i].c_str());
         log("\n");
     }
 
     if (pass_register.count(args[0]) == 0)
         log_cmd_error("No such command: %s (type 'help' for a command overview)\n", args[0].c_str());
 
     size_t orig_sel_stack_pos = design->selection_stack.size();
     auto state = pass_register[args[0]]->pre_execute();
     pass_register[args[0]]->execute(args, design);
     pass_register[args[0]]->post_execute(state);
     while (design->selection_stack.size() > orig_sel_stack_pos)
         design->selection_stack.pop_back();
 
     design->check();
 }

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void Pass::call_on_module	(	RTLIL::Design *	design,
		RTLIL::Module *	module,
		std::string	command
	)

staticinherited

Definition at line 240 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module = module->name.str();
     design->selection_stack.push_back(RTLIL::Selection(false));
     design->selection_stack.back().select(module);
 
     Pass::call(design, command);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

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void Pass::call_on_module	(	RTLIL::Design *	design,
		RTLIL::Module *	module,
		std::vector< std::string >	args
	)

staticinherited

Definition at line 253 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module = module->name.str();
     design->selection_stack.push_back(RTLIL::Selection(false));
     design->selection_stack.back().select(module);
 
     Pass::call(design, args);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

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void Pass::call_on_selection	(	RTLIL::Design *	design,
		const RTLIL::Selection &	selection,
		std::string	command
	)

staticinherited

Definition at line 216 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module.clear();
     design->selection_stack.push_back(selection);
 
     Pass::call(design, command);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

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void Pass::call_on_selection	(	RTLIL::Design *	design,
		const RTLIL::Selection &	selection,
		std::vector< std::string >	args
	)

staticinherited

Definition at line 228 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module.clear();
     design->selection_stack.push_back(selection);
 
     Pass::call(design, args);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

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void Pass::cmd_error	(	const std::vector< std::string > &	args,
		size_t	argidx,
		std::string	msg
	)

inherited

Definition at line 110 of file register.cc.

 {
     std::string command_text;
     int error_pos = 0;
 
     for (size_t i = 0; i < args.size(); i++) {
         if (i < argidx)
             error_pos += args[i].size() + 1;
         command_text = command_text + (command_text.empty() ? "" : " ") + args[i];
     }
 
     log("\nSyntax error in command `%s':\n", command_text.c_str());
     help();
 
     log_cmd_error("Command syntax error: %s\n> %s\n> %*s^\n",
             msg.c_str(), command_text.c_str(), error_pos, "");
 }

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void Pass::cmd_log_args ( const std::vector< std::string > & args )

inherited

Definition at line 100 of file register.cc.

 {
     if (args.size() <= 1)
         return;
     log("Full command line:");
     for (size_t i = 0; i < args.size(); i++)
         log(" %s", args[i].c_str());
     log("\n");
 }

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void Pass::done_register ( )

staticinherited

Definition at line 62 of file register.cc.

 {
     frontend_register.clear();
     pass_register.clear();
     backend_register.clear();
     log_assert(first_queued_pass == NULL);
 }

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virtual void HierarchyPass::execute	(	std::vector< std::string >	args,
		RTLIL::Design *	design
	)

inlinevirtual

Implements Pass.

Definition at line 370 of file hierarchy.cc.

     {
         log_header("Executing HIERARCHY pass (managing design hierarchy).\n");
 
         bool flag_check = false;
         bool purge_lib = false;
         RTLIL::Module *top_mod = NULL;
         std::vector<std::string> libdirs;
 
         bool generate_mode = false;
         bool keep_positionals = false;
         bool nokeep_asserts = false;
         std::vector<std::string> generate_cells;
         std::vector<generate_port_decl_t> generate_ports;
 
         size_t argidx;
         for (argidx = 1; argidx < args.size(); argidx++)
         {
             if (args[argidx] == "-generate" && !flag_check && !top_mod) {
                 generate_mode = true;
                 log("Entering generate mode.\n");
                 while (++argidx < args.size()) {
                     const char *p = args[argidx].c_str();
                     generate_port_decl_t decl;
                     if (p[0] == 'i' && p[1] == 'o')
                         decl.input = true, decl.output = true, p += 2;
                     else if (*p == 'i')
                         decl.input = true, decl.output = false, p++;
                     else if (*p == 'o')
                         decl.input = false, decl.output = true, p++;
                     else
                         goto is_celltype;
                     if (*p == '@') {
                         char *endptr;
                         decl.index = strtol(++p, &endptr, 10);
                         if (decl.index < 1)
                             goto is_celltype;
                         p = endptr;
                     } else
                         decl.index = 0;
                     if (*(p++) != ':')
                         goto is_celltype;
                     if (*p == 0)
                         goto is_celltype;
                     decl.portname = p;
                     log("Port declaration: %s", decl.input ? decl.output ? "inout" : "input" : "output");
                     if (decl.index >= 1)
                         log(" [at position %d]", decl.index);
                     log(" %s\n", decl.portname.c_str());
                     generate_ports.push_back(decl);
                     continue;
                 is_celltype:
                     log("Celltype: %s\n", args[argidx].c_str());
                     generate_cells.push_back(RTLIL::unescape_id(args[argidx]));
                 }
                 continue;
             }
             if (args[argidx] == "-check") {
                 flag_check = true;
                 continue;
             }
             if (args[argidx] == "-purge_lib") {
                 purge_lib = true;
                 continue;
             }
             if (args[argidx] == "-keep_positionals") {
                 keep_positionals = true;
                 continue;
             }
             if (args[argidx] == "-nokeep_asserts") {
                 nokeep_asserts = true;
                 continue;
             }
             if (args[argidx] == "-libdir" && argidx+1 < args.size()) {
                 libdirs.push_back(args[++argidx]);
                 continue;
             }
             if (args[argidx] == "-top") {
                 if (++argidx >= args.size())
                     log_cmd_error("Option -top requires an additional argument!\n");
                 top_mod = design->modules_.count(RTLIL::escape_id(args[argidx])) ? design->modules_.at(RTLIL::escape_id(args[argidx])) : NULL;
                 if (top_mod == NULL && design->modules_.count("$abstract" + RTLIL::escape_id(args[argidx]))) {
                     std::map<RTLIL::IdString, RTLIL::Const> empty_parameters;
                     design->modules_.at("$abstract" + RTLIL::escape_id(args[argidx]))->derive(design, empty_parameters);
                     top_mod = design->modules_.count(RTLIL::escape_id(args[argidx])) ? design->modules_.at(RTLIL::escape_id(args[argidx])) : NULL;
                 }
                 if (top_mod == NULL)
                     log_cmd_error("Module `%s' not found!\n", args[argidx].c_str());
                 continue;
             }
             break;
         }
         extra_args(args, argidx, design, false);
 
         if (generate_mode) {
             generate(design, generate_cells, generate_ports);
             return;
         }
 
         log_push();
 
         if (top_mod == NULL)
             for (auto &mod_it : design->modules_)
                 if (mod_it.second->get_bool_attribute("\\top"))
                     top_mod = mod_it.second;
 
         if (top_mod != NULL)
             hierarchy(design, top_mod, purge_lib, true);
 
         bool did_something = true;
         bool did_something_once = false;
         while (did_something) {
             did_something = false;
             std::vector<RTLIL::IdString> modnames;
             modnames.reserve(design->modules_.size());
             for (auto &mod_it : design->modules_)
                 modnames.push_back(mod_it.first);
             for (auto &modname : modnames) {
                 if (design->modules_.count(modname) == 0)
                     continue;
                 if (expand_module(design, design->modules_[modname], flag_check, libdirs))
                     did_something = true;
             }
             if (did_something)
                 did_something_once = true;
         }
 
         if (top_mod != NULL && did_something_once) {
             log_header("Re-running hierarchy analysis..\n");
             hierarchy(design, top_mod, purge_lib, false);
         }
 
         if (top_mod != NULL) {
             for (auto &mod_it : design->modules_)
                 if (mod_it.second == top_mod)
                     mod_it.second->attributes["\\top"] = RTLIL::Const(1);
                 else
                     mod_it.second->attributes.erase("\\top");
         }
 
         if (!nokeep_asserts) {
             std::map<RTLIL::Module*, bool> cache;
             for (auto mod : design->modules())
                 if (set_keep_assert(cache, mod)) {
                     log("Module %s directly or indirectly contains $assert cells -> setting \"keep\" attribute.\n", log_id(mod));
                     mod->set_bool_attribute("\\keep");
                 }
         }
 
         if (!keep_positionals)
         {
             std::set<RTLIL::Module*> pos_mods;
             std::map<std::pair<RTLIL::Module*,int>, RTLIL::IdString> pos_map;
             std::vector<std::pair<RTLIL::Module*,RTLIL::Cell*>> pos_work;
 
             for (auto &mod_it : design->modules_)
             for (auto &cell_it : mod_it.second->cells_) {
                 RTLIL::Cell *cell = cell_it.second;
                 if (design->modules_.count(cell->type) == 0)
                     continue;
                 for (auto &conn : cell->connections())
                     if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') {
                         pos_mods.insert(design->modules_.at(cell->type));
                         pos_work.push_back(std::pair<RTLIL::Module*,RTLIL::Cell*>(mod_it.second, cell));
                         break;
                     }
             }
 
             for (auto module : pos_mods)
             for (auto &wire_it : module->wires_) {
                 RTLIL::Wire *wire = wire_it.second;
                 if (wire->port_id > 0)
                     pos_map[std::pair<RTLIL::Module*,int>(module, wire->port_id)] = wire->name;
             }
 
             for (auto &work : pos_work) {
                 RTLIL::Module *module = work.first;
                 RTLIL::Cell *cell = work.second;
                 log("Mapping positional arguments of cell %s.%s (%s).\n",
                         RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
                 std::map<RTLIL::IdString, RTLIL::SigSpec> new_connections;
                 for (auto &conn : cell->connections())
                     if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') {
                         int id = atoi(conn.first.c_str()+1);
                         std::pair<RTLIL::Module*,int> key(design->modules_.at(cell->type), id);
                         if (pos_map.count(key) == 0) {
                             log("  Failed to map positional argument %d of cell %s.%s (%s).\n",
                                     id, RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
                             new_connections[conn.first] = conn.second;
                         } else
                             new_connections[pos_map.at(key)] = conn.second;
                     } else
                         new_connections[conn.first] = conn.second;
                 cell->connections_ = new_connections;
             }
         }
 
         log_pop();
     }

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void Pass::extra_args	(	std::vector< std::string >	args,
		size_t	argidx,
		RTLIL::Design *	design,
		bool	select = `true`
	)

inherited

Definition at line 128 of file register.cc.

 {
     for (; argidx < args.size(); argidx++)
     {
         std::string arg = args[argidx];
 
         if (arg.substr(0, 1) == "-")
             cmd_error(args, argidx, "Unknown option or option in arguments.");
 
         if (!select)
             cmd_error(args, argidx, "Extra argument.");
 
         handle_extra_select_args(this, args, argidx, args.size(), design);
         break;
     }
     // cmd_log_args(args);
 }

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virtual void HierarchyPass::help ( )

inlinevirtual

Reimplemented from Pass.

Definition at line 311 of file hierarchy.cc.

     {
         //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
         log("\n");
         log("    hierarchy [-check] [-top <module>]\n");
         log("    hierarchy -generate <cell-types> <port-decls>\n");
         log("\n");
         log("In parametric designs, a module might exists in several variations with\n");
         log("different parameter values. This pass looks at all modules in the current\n");
         log("design an re-runs the language frontends for the parametric modules as\n");
         log("needed.\n");
         log("\n");
         log("    -check\n");
         log("        also check the design hierarchy. this generates an error when\n");
         log("        an unknown module is used as cell type.\n");
         log("\n");
         log("    -purge_lib\n");
         log("        by default the hierarchy command will not remove library (blackbox)\n");
         log("        module. use this options to also remove unused blackbox modules.\n");
         log("\n");
         log("    -libdir <directory>\n");
         log("        search for files named <module_name>.v in the specified directory\n");
         log("        for unknown modules and automatically run read_verilog for each\n");
         log("        unknown module.\n");
         log("\n");
         log("    -keep_positionals\n");
         log("        per default this pass also converts positional arguments in cells\n");
         log("        to arguments using port names. this option disables this behavior.\n");
         log("\n");
         log("    -nokeep_asserts\n");
         log("        per default this pass sets the \"keep\" attribute on all modules\n");
         log("        that directly or indirectly contain one or more $assert cells. this\n");
         log("        option disables this behavior.\n");
         log("\n");
         log("    -top <module>\n");
         log("        use the specified top module to built a design hierarchy. modules\n");
         log("        outside this tree (unused modules) are removed.\n");
         log("\n");
         log("        when the -top option is used, the 'top' attribute will be set on the\n");
         log("        specified top module. otherwise a module with the 'top' attribute set\n");
         log("        will implicitly be used as top module, if such a module exists.\n");
         log("\n");
         log("In -generate mode this pass generates blackbox modules for the given cell\n");
         log("types (wildcards supported). For this the design is searched for cells that\n");
         log("match the given types and then the given port declarations are used to\n");
         log("determine the direction of the ports. The syntax for a port declaration is:\n");
         log("\n");
         log("    {i|o|io}[@<num>]:<portname>\n");
         log("\n");
         log("Input ports are specified with the 'i' prefix, output ports with the 'o'\n");
         log("prefix and inout ports with the 'io' prefix. The optional <num> specifies\n");
         log("the position of the port in the parameter list (needed when instanciated\n");
         log("using positional arguments). When <num> is not specified, the <portname> can\n");
         log("also contain wildcard characters.\n");
         log("\n");
         log("This pass ignores the current selection and always operates on all modules\n");
         log("in the current design.\n");
         log("\n");
     }

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void Pass::init_register ( )

staticinherited

Definition at line 54 of file register.cc.

 {
     while (first_queued_pass) {
         first_queued_pass->run_register();
         first_queued_pass = first_queued_pass->next_queued_pass;
     }
 }

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void Pass::post_execute ( Pass::pre_post_exec_state_t state )

inherited

Definition at line 84 of file register.cc.

 {
     int64_t time_ns = PerformanceTimer::query() - state.begin_ns;
     runtime_ns += time_ns;
     current_pass = state.parent_pass;
     if (current_pass)
         current_pass->runtime_ns -= time_ns;
 }

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Pass::pre_post_exec_state_t Pass::pre_execute ( )

inherited

Definition at line 74 of file register.cc.

 {
     pre_post_exec_state_t state;
     call_counter++;
     state.begin_ns = PerformanceTimer::query();
     state.parent_pass = current_pass;
     current_pass = this;
     return state;
 }

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void Pass::run_register ( )

virtualinherited

Reimplemented in Backend, and Frontend.

Definition at line 48 of file register.cc.

 {
     log_assert(pass_register.count(pass_name) == 0);
     pass_register[pass_name] = this;
 }

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Field Documentation

int Pass::call_counter

inherited

Definition at line 36 of file register.h.

Pass* Pass::next_queued_pass

inherited

Definition at line 60 of file register.h.

std::string Pass::pass_name

inherited

Definition at line 29 of file register.h.

int64_t Pass::runtime_ns

inherited

Definition at line 37 of file register.h.

std::string Pass::short_help

inherited

Definition at line 29 of file register.h.

The documentation for this struct was generated from the following file:

hierarchy.cc

Public Member Functions

Static Public Member Functions

Data Fields

Detailed Description

Constructor & Destructor Documentation

Member Function Documentation

Field Documentation