hierarchy.cc File Reference

#include "kernel/yosys.h"
#include <stdlib.h>
#include <stdio.h>
#include <set>
#include <unistd.h>

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Data Structures
struct	generate_port_decl_t
struct	HierarchyPass

Functions
void	generate (RTLIL::Design *design, const std::vector< std::string > &celltypes, const std::vector< generate_port_decl_t > &portdecls)
bool	expand_module (RTLIL::Design *design, RTLIL::Module *module, bool flag_check, std::vector< std::string > &libdirs)
void	hierarchy_worker (RTLIL::Design *design, std::set< RTLIL::Module * > &used, RTLIL::Module *mod, int indent)
void	hierarchy (RTLIL::Design *design, RTLIL::Module *top, bool purge_lib, bool first_pass)
bool	set_keep_assert (std::map< RTLIL::Module *, bool > &cache, RTLIL::Module *mod)

Variables
HierarchyPass	HierarchyPass

Function Documentation

bool expand_module	(	RTLIL::Design *	design,
		RTLIL::Module *	module,
		bool	flag_check,
		std::vector< std::string > &	libdirs
	)

Definition at line 141 of file hierarchy.cc.

{
    bool did_something = false;
    std::map<RTLIL::Cell*, std::pair<int, int>> array_cells;
    std::string filename;

    for (auto &cell_it : module->cells_)
    {
        RTLIL::Cell *cell = cell_it.second;

        if (cell->type.substr(0, 7) == "$array:") {
            int pos_idx = cell->type.str().find_first_of(':');
            int pos_num = cell->type.str().find_first_of(':', pos_idx + 1);
            int pos_type = cell->type.str().find_first_of(':', pos_num + 1);
            int idx = atoi(cell->type.str().substr(pos_idx + 1, pos_num).c_str());
            int num = atoi(cell->type.str().substr(pos_num + 1, pos_type).c_str());
            array_cells[cell] = std::pair<int, int>(idx, num);
            cell->type = cell->type.str().substr(pos_type + 1);
        }

        if (design->modules_.count(cell->type) == 0)
        {
            if (design->modules_.count("$abstract" + cell->type.str()))
            {
                cell->type = design->modules_.at("$abstract" + cell->type.str())->derive(design, cell->parameters);
                cell->parameters.clear();
                did_something = true;
                continue;
            }

            if (cell->type[0] == '$')
                continue;

            for (auto &dir : libdirs)
            {
                filename = dir + "/" + RTLIL::unescape_id(cell->type) + ".v";
                if (check_file_exists(filename)) {
                    std::vector<std::string> args;
                    args.push_back(filename);
                    Frontend::frontend_call(design, NULL, filename, "verilog");
                    goto loaded_module;
                }

                filename = dir + "/" + RTLIL::unescape_id(cell->type) + ".il";
                if (check_file_exists(filename)) {
                    std::vector<std::string> args;
                    args.push_back(filename);
                    Frontend::frontend_call(design, NULL, filename, "ilang");
                    goto loaded_module;
                }
            }

            if (flag_check && cell->type[0] != '$')
                log_error("Module `%s' referenced in module `%s' in cell `%s' is not part of the design.\n",
                        cell->type.c_str(), module->name.c_str(), cell->name.c_str());
            continue;

        loaded_module:
            if (design->modules_.count(cell->type) == 0)
                log_error("File `%s' from libdir does not declare module `%s'.\n", filename.c_str(), cell->type.c_str());
            did_something = true;
        }

        if (cell->parameters.size() == 0)
            continue;

        if (design->modules_.at(cell->type)->get_bool_attribute("\\blackbox"))
            continue;

        RTLIL::Module *mod = design->modules_[cell->type];
        cell->type = mod->derive(design, cell->parameters);
        cell->parameters.clear();
        did_something = true;
    }

    for (auto &it : array_cells)
    {
        RTLIL::Cell *cell = it.first;
        int idx = it.second.first, num = it.second.second;

        if (design->modules_.count(cell->type) == 0)
            log_error("Array cell `%s.%s' of unknown type `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));

        RTLIL::Module *mod = design->modules_[cell->type];

        for (auto &conn : cell->connections_) {
            int conn_size = conn.second.size();
            RTLIL::IdString portname = conn.first;
            if (portname.substr(0, 1) == "$") {
                int port_id = atoi(portname.substr(1).c_str());
                for (auto &wire_it : mod->wires_)
                    if (wire_it.second->port_id == port_id) {
                        portname = wire_it.first;
                        break;
                    }
            }
            if (mod->wires_.count(portname) == 0)
                log_error("Array cell `%s.%s' connects to unknown port `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first));
            int port_size = mod->wires_.at(portname)->width;
            if (conn_size == port_size)
                continue;
            if (conn_size != port_size*num)
                log_error("Array cell `%s.%s' has invalid port vs. signal size for port `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first));
            conn.second = conn.second.extract(port_size*idx, port_size);
        }
    }

    return did_something;
}

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void generate	(	RTLIL::Design *	design,
		const std::vector< std::string > &	celltypes,
		const std::vector< generate_port_decl_t > &	portdecls
	)

Definition at line 39 of file hierarchy.cc.

{
    std::set<RTLIL::IdString> found_celltypes;

    for (auto i1 : design->modules_)
    for (auto i2 : i1.second->cells_)
    {
        RTLIL::Cell *cell = i2.second;
        if (design->has(cell->type))
            continue;
        if (cell->type.substr(0, 1) == "$" && cell->type.substr(0, 3) != "$__")
            continue;
        for (auto &pattern : celltypes)
            if (patmatch(pattern.c_str(), RTLIL::unescape_id(cell->type).c_str()))
                found_celltypes.insert(cell->type);
    }

    for (auto &celltype : found_celltypes)
    {
        std::set<RTLIL::IdString> portnames;
        std::set<RTLIL::IdString> parameters;
        std::map<RTLIL::IdString, int> portwidths;
        log("Generate module for cell type %s:\n", celltype.c_str());

        for (auto i1 : design->modules_)
        for (auto i2 : i1.second->cells_)
            if (i2.second->type == celltype) {
                for (auto &conn : i2.second->connections()) {
                    if (conn.first[0] != '$')
                        portnames.insert(conn.first);
                    portwidths[conn.first] = std::max(portwidths[conn.first], conn.second.size());
                }
                for (auto &para : i2.second->parameters)
                    parameters.insert(para.first);
            }

        for (auto &decl : portdecls)
            if (decl.index > 0)
                portnames.insert(decl.portname);

        std::set<int> indices;
        for (int i = 0; i < int(portnames.size()); i++)
            indices.insert(i+1);

        std::vector<generate_port_decl_t> ports(portnames.size());

        for (auto &decl : portdecls)
            if (decl.index > 0) {
                portwidths[decl.portname] = std::max(portwidths[decl.portname], 1);
                portwidths[decl.portname] = std::max(portwidths[decl.portname], portwidths[stringf("$%d", decl.index)]);
                log("  port %d: %s [%d:0] %s\n", decl.index, decl.input ? decl.output ? "inout" : "input" : "output", portwidths[decl.portname]-1, RTLIL::id2cstr(decl.portname));
                if (indices.count(decl.index) > ports.size())
                    log_error("Port index (%d) exceeds number of found ports (%d).\n", decl.index, int(ports.size()));
                if (indices.count(decl.index) == 0)
                    log_error("Conflict on port index %d.\n", decl.index);
                indices.erase(decl.index);
                portnames.erase(decl.portname);
                ports[decl.index-1] = decl;
            }

        while (portnames.size() > 0) {
            RTLIL::IdString portname = *portnames.begin();
            for (auto &decl : portdecls)
                if (decl.index == 0 && patmatch(decl.portname.c_str(), RTLIL::unescape_id(portname).c_str())) {
                    generate_port_decl_t d = decl;
                    d.portname = portname;
                    d.index = *indices.begin();
                    log_assert(!indices.empty());
                    indices.erase(d.index);
                    ports[d.index-1] = d;
                    portwidths[d.portname] = std::max(portwidths[d.portname], 1);
                    log("  port %d: %s [%d:0] %s\n", d.index, d.input ? d.output ? "inout" : "input" : "output", portwidths[d.portname]-1, RTLIL::id2cstr(d.portname));
                    goto found_matching_decl;
                }
            log_error("Can't match port %s.\n", RTLIL::id2cstr(portname));
        found_matching_decl:;
            portnames.erase(portname);
        }

        log_assert(indices.empty());

        RTLIL::Module *mod = new RTLIL::Module;
        mod->name = celltype;
        mod->attributes["\\blackbox"] = RTLIL::Const(1);
        design->add(mod);

        for (auto &decl : ports) {
            RTLIL::Wire *wire = mod->addWire(decl.portname, portwidths.at(decl.portname));
            wire->port_id = decl.index;
            wire->port_input = decl.input;
            wire->port_output = decl.output;
        }

        mod->fixup_ports();

        for (auto &para : parameters)
            log("  ignoring parameter %s.\n", RTLIL::id2cstr(para));

        log("  module %s created.\n", RTLIL::id2cstr(mod->name));
    }
}

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void hierarchy	(	RTLIL::Design *	design,
		RTLIL::Module *	top,
		bool	purge_lib,
		bool	first_pass
	)

Definition at line 275 of file hierarchy.cc.

{
    std::set<RTLIL::Module*> used;
    hierarchy_worker(design, used, top, 0);

    std::vector<RTLIL::Module*> del_modules;
    for (auto &it : design->modules_)
        if (used.count(it.second) == 0)
            del_modules.push_back(it.second);

    for (auto mod : del_modules) {
        if (first_pass && mod->name.substr(0, 9) == "$abstract")
            continue;
        if (!purge_lib && mod->get_bool_attribute("\\blackbox"))
            continue;
        log("Removing unused module `%s'.\n", mod->name.c_str());
        design->modules_.erase(mod->name);
        delete mod;
    }

    log("Removed %d unused modules.\n", GetSize(del_modules));
}

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void hierarchy_worker	(	RTLIL::Design *	design,
		std::set< RTLIL::Module * > &	used,
		RTLIL::Module *	mod,
		int	indent
	)

Definition at line 251 of file hierarchy.cc.

{
    if (used.count(mod) > 0)
        return;

    if (indent == 0)
        log("Top module:  %s\n", mod->name.c_str());
    else
        log("Used module: %*s%s\n", indent, "", mod->name.c_str());
    used.insert(mod);

    for (auto cell : mod->cells()) {
        std::string celltype = cell->type.str();
        if (celltype.substr(0, 7) == "$array:") {
            int pos_idx = celltype.find_first_of(':');
            int pos_num = celltype.find_first_of(':', pos_idx + 1);
            int pos_type = celltype.find_first_of(':', pos_num + 1);
            celltype = celltype.substr(pos_type + 1);
        }
        if (design->module(celltype))
            hierarchy_worker(design, used, design->module(celltype), indent+4);
    }
}

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bool set_keep_assert	(	std::map< RTLIL::Module *, bool > &	cache,
		RTLIL::Module *	mod
	)

Definition at line 298 of file hierarchy.cc.

{
    if (cache.count(mod) == 0)
        for (auto c : mod->cells()) {
            RTLIL::Module *m = mod->design->module(c->type);
            if ((m != nullptr && set_keep_assert(cache, m)) || c->type == "$assert")
                return cache[mod] = true;
        }
    return cache[mod];
}

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Variable Documentation

HierarchyPass HierarchyPass