Inheritance diagram for EvalPass:

Collaboration diagram for EvalPass:

Public Member Functions
	EvalPass ()

virtual void	help ()

virtual void	execute (std::vector< std::string > args, RTLIL::Design *design)

pre_post_exec_state_t	pre_execute ()

void	post_execute (pre_post_exec_state_t state)

void	cmd_log_args (const std::vector< std::string > &args)

void	cmd_error (const std::vector< std::string > &args, size_t argidx, std::string msg)

void	extra_args (std::vector< std::string > args, size_t argidx, RTLIL::Design *design, bool select=true)

virtual void	run_register ()

Static Public Member Functions
static void	call (RTLIL::Design *design, std::string command)

static void	call (RTLIL::Design *design, std::vector< std::string > args)

static void	call_on_selection (RTLIL::Design *design, const RTLIL::Selection &selection, std::string command)

static void	call_on_selection (RTLIL::Design *design, const RTLIL::Selection &selection, std::vector< std::string > args)

static void	call_on_module (RTLIL::Design design, RTLIL::Module module, std::string command)

static void	call_on_module (RTLIL::Design design, RTLIL::Module module, std::vector< std::string > args)

static void	init_register ()

static void	done_register ()

Data Fields
std::string	pass_name

std::string	short_help

int	call_counter

int64_t	runtime_ns

Pass *	next_queued_pass

Detailed Description

Definition at line 361 of file eval.cc.

Constructor & Destructor Documentation

EvalPass::EvalPass ( )

inline

Definition at line 362 of file eval.cc.

362 : Pass("eval", "evaluate the circuit given an input") { }

Pass::Pass

Pass(std::string name, std::string short_help="** document me **")

Definition: register.cc:40

Member Function Documentation

void Pass::call	(	RTLIL::Design *	design,
		std::string	command
	)

staticinherited

Definition at line 146 of file register.cc.

 {
     std::vector<std::string> args;
 
     std::string cmd_buf = command;
     std::string tok = next_token(cmd_buf, " \t\r\n");
 
     if (tok.empty() || tok[0] == '#')
         return;
 
     if (tok[0] == '!') {
         cmd_buf = command.substr(command.find('!') + 1);
         while (!cmd_buf.empty() && (cmd_buf.back() == ' ' || cmd_buf.back() == '\t' ||
                 cmd_buf.back() == '\r' || cmd_buf.back() == '\n'))
             cmd_buf.resize(cmd_buf.size()-1);
         log_header("Shell command: %s\n", cmd_buf.c_str());
         int retCode = run_command(cmd_buf);
         if (retCode != 0)
             log_cmd_error("Shell command returned error code %d.\n", retCode);
         return;
     }
 
     while (!tok.empty()) {
         if (tok == "#")
             break;
         if (tok.back() == ';') {
             int num_semikolon = 0;
             while (!tok.empty() && tok.back() == ';')
                 tok.resize(tok.size()-1), num_semikolon++;
             if (!tok.empty())
                 args.push_back(tok);
             call(design, args);
             args.clear();
             if (num_semikolon == 2)
                 call(design, "clean");
             if (num_semikolon == 3)
                 call(design, "clean -purge");
         } else
             args.push_back(tok);
         tok = next_token(cmd_buf, " \t\r\n");
     }
 
     call(design, args);
 }

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void Pass::call	(	RTLIL::Design *	design,
		std::vector< std::string >	args
	)

staticinherited

Definition at line 191 of file register.cc.

 {
     if (args.size() == 0 || args[0][0] == '#')
         return;
 
     if (echo_mode) {
         log("%s", create_prompt(design, 0));
         for (size_t i = 0; i < args.size(); i++)
             log("%s%s", i ? " " : "", args[i].c_str());
         log("\n");
     }
 
     if (pass_register.count(args[0]) == 0)
         log_cmd_error("No such command: %s (type 'help' for a command overview)\n", args[0].c_str());
 
     size_t orig_sel_stack_pos = design->selection_stack.size();
     auto state = pass_register[args[0]]->pre_execute();
     pass_register[args[0]]->execute(args, design);
     pass_register[args[0]]->post_execute(state);
     while (design->selection_stack.size() > orig_sel_stack_pos)
         design->selection_stack.pop_back();
 
     design->check();
 }

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void Pass::call_on_module	(	RTLIL::Design *	design,
		RTLIL::Module *	module,
		std::string	command
	)

staticinherited

Definition at line 240 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module = module->name.str();
     design->selection_stack.push_back(RTLIL::Selection(false));
     design->selection_stack.back().select(module);
 
     Pass::call(design, command);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

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void Pass::call_on_module	(	RTLIL::Design *	design,
		RTLIL::Module *	module,
		std::vector< std::string >	args
	)

staticinherited

Definition at line 253 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module = module->name.str();
     design->selection_stack.push_back(RTLIL::Selection(false));
     design->selection_stack.back().select(module);
 
     Pass::call(design, args);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

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void Pass::call_on_selection	(	RTLIL::Design *	design,
		const RTLIL::Selection &	selection,
		std::string	command
	)

staticinherited

Definition at line 216 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module.clear();
     design->selection_stack.push_back(selection);
 
     Pass::call(design, command);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

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void Pass::call_on_selection	(	RTLIL::Design *	design,
		const RTLIL::Selection &	selection,
		std::vector< std::string >	args
	)

staticinherited

Definition at line 228 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module.clear();
     design->selection_stack.push_back(selection);
 
     Pass::call(design, args);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

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void Pass::cmd_error	(	const std::vector< std::string > &	args,
		size_t	argidx,
		std::string	msg
	)

inherited

Definition at line 110 of file register.cc.

 {
     std::string command_text;
     int error_pos = 0;
 
     for (size_t i = 0; i < args.size(); i++) {
         if (i < argidx)
             error_pos += args[i].size() + 1;
         command_text = command_text + (command_text.empty() ? "" : " ") + args[i];
     }
 
     log("\nSyntax error in command `%s':\n", command_text.c_str());
     help();
 
     log_cmd_error("Command syntax error: %s\n> %s\n> %*s^\n",
             msg.c_str(), command_text.c_str(), error_pos, "");
 }

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void Pass::cmd_log_args ( const std::vector< std::string > & args )

inherited

Definition at line 100 of file register.cc.

 {
     if (args.size() <= 1)
         return;
     log("Full command line:");
     for (size_t i = 0; i < args.size(); i++)
         log(" %s", args[i].c_str());
     log("\n");
 }

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void Pass::done_register ( )

staticinherited

Definition at line 62 of file register.cc.

 {
     frontend_register.clear();
     pass_register.clear();
     backend_register.clear();
     log_assert(first_queued_pass == NULL);
 }

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virtual void EvalPass::execute	(	std::vector< std::string >	args,
		RTLIL::Design *	design
	)

inlinevirtual

Implements Pass.

Definition at line 386 of file eval.cc.

     {
         std::vector<std::pair<std::string, std::string>> sets;
         std::vector<std::string> shows, tables;
         bool set_undef = false;
 
         log_header("Executing EVAL pass (evaluate the circuit given an input).\n");
 
         size_t argidx;
         for (argidx = 1; argidx < args.size(); argidx++) {
             if (args[argidx] == "-set" && argidx+2 < args.size()) {
                 std::string lhs = args[++argidx].c_str();
                 std::string rhs = args[++argidx].c_str();
                 sets.push_back(std::pair<std::string, std::string>(lhs, rhs));
                 continue;
             }
             if (args[argidx] == "-set-undef") {
                 set_undef = true;
                 continue;
             }
             if (args[argidx] == "-show" && argidx+1 < args.size()) {
                 shows.push_back(args[++argidx]);
                 continue;
             }
             if (args[argidx] == "-table" && argidx+1 < args.size()) {
                 tables.push_back(args[++argidx]);
                 continue;
             }
             if ((args[argidx] == "-brute_force_equiv_checker" || args[argidx] == "-brute_force_equiv_checker_x") && argidx+3 == args.size()) {
                 /* this should only be used for regression testing of ConstEval -- see vloghammer */
                 std::string mod1_name = RTLIL::escape_id(args[++argidx]);
                 std::string mod2_name = RTLIL::escape_id(args[++argidx]);
                 if (design->modules_.count(mod1_name) == 0)
                     log_error("Can't find module `%s'!\n", mod1_name.c_str());
                 if (design->modules_.count(mod2_name) == 0)
                     log_error("Can't find module `%s'!\n", mod2_name.c_str());
                 BruteForceEquivChecker checker(design->modules_.at(mod1_name), design->modules_.at(mod2_name), args[argidx-2] == "-brute_force_equiv_checker_x");
                 if (checker.errors > 0)
                     log_cmd_error("Modules are not equivialent!\n");
                 log("Verified %s = %s (using brute-force check on %d cases).\n",
                         mod1_name.c_str(), mod2_name.c_str(), checker.counter);
                 return;
             }
             if (args[argidx] == "-vloghammer_report" && argidx+5 == args.size()) {
                 /* this should only be used for regression testing of ConstEval -- see vloghammer */
                 std::string module_prefix = args[++argidx];
                 std::string module_list = args[++argidx];
                 std::string input_list = args[++argidx];
                 std::string pattern_list = args[++argidx];
                 VlogHammerReporter reporter(design, module_prefix, module_list, input_list, pattern_list);
                 reporter.run();
                 return;
             }
             break;
         }
         extra_args(args, argidx, design);
 
         RTLIL::Module *module = NULL;
         for (auto &mod_it : design->modules_)
             if (design->selected(mod_it.second)) {
                 if (module)
                     log_cmd_error("Only one module must be selected for the EVAL pass! (selected: %s and %s)\n",
                             RTLIL::id2cstr(module->name), RTLIL::id2cstr(mod_it.first));
                 module = mod_it.second;
             }
         if (module == NULL) 
             log_cmd_error("Can't perform EVAL on an empty selection!\n");
 
         ConstEval ce(module);
 
         for (auto &it : sets) {
             RTLIL::SigSpec lhs, rhs;
             if (!RTLIL::SigSpec::parse_sel(lhs, design, module, it.first))
                 log_cmd_error("Failed to parse lhs set expression `%s'.\n", it.first.c_str());
             if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, it.second))
                 log_cmd_error("Failed to parse rhs set expression `%s'.\n", it.second.c_str());
             if (!rhs.is_fully_const())
                 log_cmd_error("Right-hand-side set expression `%s' is not constant.\n", it.second.c_str());
             if (lhs.size() != rhs.size())
                 log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n",
                         it.first.c_str(), log_signal(lhs), lhs.size(), it.second.c_str(), log_signal(rhs), rhs.size());
             ce.set(lhs, rhs.as_const());
         }
 
         if (shows.size() == 0) {
             for (auto &it : module->wires_)
                 if (it.second->port_output)
                     shows.push_back(it.second->name.str());
         }
 
         if (tables.empty())
         {
             for (auto &it : shows) {
                 RTLIL::SigSpec signal, value, undef;
                 if (!RTLIL::SigSpec::parse_sel(signal, design, module, it))
                     log_cmd_error("Failed to parse show expression `%s'.\n", it.c_str());
                 value = signal;
                 if (set_undef) {
                     while (!ce.eval(value, undef)) {
                         log("Failed to evaluate signal %s: Missing value for %s. -> setting to undef\n", log_signal(signal), log_signal(undef));
                         ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.size()));
                         undef = RTLIL::SigSpec();
                     }
                     log("Eval result: %s = %s.\n", log_signal(signal), log_signal(value));
                 } else {
                     if (!ce.eval(value, undef))
                         log("Failed to evaluate signal %s: Missing value for %s.\n", log_signal(signal), log_signal(undef));
                     else
                         log("Eval result: %s = %s.\n", log_signal(signal), log_signal(value));
                 }
             }
         }
         else
         {
             RTLIL::SigSpec tabsigs, signal, value, undef;
             std::vector<std::vector<std::string>> tab;
             int tab_sep_colidx = 0;
 
             for (auto &it : shows) {
                 RTLIL::SigSpec sig;
                 if (!RTLIL::SigSpec::parse_sel(sig, design, module, it))
                     log_cmd_error("Failed to parse show expression `%s'.\n", it.c_str());
                 signal.append(sig);
             }
 
             for (auto &it : tables) {
                 RTLIL::SigSpec sig;
                 if (!RTLIL::SigSpec::parse_sel(sig, design, module, it))
                     log_cmd_error("Failed to parse table expression `%s'.\n", it.c_str());
                 tabsigs.append(sig);
             }
 
             std::vector<std::string> tab_line;
             for (auto &c : tabsigs.chunks())
                 tab_line.push_back(log_signal(c));
             tab_sep_colidx = tab_line.size();
             for (auto &c : signal.chunks())
                 tab_line.push_back(log_signal(c));
             tab.push_back(tab_line);
             tab_line.clear();
 
             RTLIL::Const tabvals(0, tabsigs.size());
             do
             {
                 ce.push();
                 ce.set(tabsigs, tabvals);
                 value = signal;
 
                 RTLIL::SigSpec this_undef;
                 while (!ce.eval(value, this_undef)) {
                     if (!set_undef) {
                         log("Failed to evaluate signal %s at %s = %s: Missing value for %s.\n", log_signal(signal),
                                 log_signal(tabsigs), log_signal(tabvals), log_signal(this_undef));
                         return;
                     }
                     ce.set(this_undef, RTLIL::Const(RTLIL::State::Sx, this_undef.size()));
                     undef.append(this_undef);
                     this_undef = RTLIL::SigSpec();
                 }
 
                 int pos = 0;
                 for (auto &c : tabsigs.chunks()) {
                     tab_line.push_back(log_signal(RTLIL::SigSpec(tabvals).extract(pos, c.width)));
                     pos += c.width;
                 }
 
                 pos = 0;
                 for (auto &c : signal.chunks()) {
                     tab_line.push_back(log_signal(value.extract(pos, c.width)));
                     pos += c.width;
                 }
 
                 tab.push_back(tab_line);
                 tab_line.clear();
                 ce.pop();
 
                 tabvals = RTLIL::const_add(tabvals, RTLIL::Const(1), false, false, tabvals.bits.size());
             }
             while (tabvals.as_bool());
 
             std::vector<int> tab_column_width;
             for (auto &row : tab) {
                 if (tab_column_width.size() < row.size())
                     tab_column_width.resize(row.size());
                 for (size_t i = 0; i < row.size(); i++)
                     tab_column_width[i] = std::max(tab_column_width[i], int(row[i].size()));
             }
 
             log("\n");
             bool first = true;
             for (auto &row : tab) {
                 for (size_t i = 0; i < row.size(); i++) {
                     int k = int(i) < tab_sep_colidx ? tab_sep_colidx - i - 1 : i;
                     log(" %s%*s", k == tab_sep_colidx ? "| " : "", tab_column_width[k], row[k].c_str());
                 }
                 log("\n");
                 if (first) {
                     for (size_t i = 0; i < row.size(); i++) {
                         int k = int(i) < tab_sep_colidx ? tab_sep_colidx - i - 1 : i;
                         log(" %s", k == tab_sep_colidx ? "| " : "");
                         for (int j = 0; j < tab_column_width[k]; j++)
                             log("-");
                     }
                     log("\n");
                     first = false;
                 }
             }
 
             log("\n");
             if (undef.size() > 0) {
                 undef.sort_and_unify();
                 log("Assumend undef (x) value for the following singals: %s\n\n", log_signal(undef));
             }
         }
     }

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void Pass::extra_args	(	std::vector< std::string >	args,
		size_t	argidx,
		RTLIL::Design *	design,
		bool	select = `true`
	)

inherited

Definition at line 128 of file register.cc.

 {
     for (; argidx < args.size(); argidx++)
     {
         std::string arg = args[argidx];
 
         if (arg.substr(0, 1) == "-")
             cmd_error(args, argidx, "Unknown option or option in arguments.");
 
         if (!select)
             cmd_error(args, argidx, "Extra argument.");
 
         handle_extra_select_args(this, args, argidx, args.size(), design);
         break;
     }
     // cmd_log_args(args);
 }

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virtual void EvalPass::help ( )

inlinevirtual

Reimplemented from Pass.

Definition at line 363 of file eval.cc.

     {
         //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
         log("\n");
         log("    eval [options] [selection]\n");
         log("\n");
         log("This command evaluates the value of a signal given the value of all required\n");
         log("inputs.\n");
         log("\n");
         log("    -set <signal> <value>\n");
         log("        set the specified signal to the specified value.\n");
         log("\n");
         log("    -set-undef\n");
         log("        set all unspecified source signals to undef (x)\n");
         log("\n");
         log("    -table <signal>\n");
         log("        create a truth table using the specified input signals\n");
         log("\n");
         log("    -show <signal>\n");
         log("        show the value for the specified signal. if no -show option is passed\n");
         log("        then all output ports of the current module are used.\n");
         log("\n");
     }

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void Pass::init_register ( )

staticinherited

Definition at line 54 of file register.cc.

 {
     while (first_queued_pass) {
         first_queued_pass->run_register();
         first_queued_pass = first_queued_pass->next_queued_pass;
     }
 }

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void Pass::post_execute ( Pass::pre_post_exec_state_t state )

inherited

Definition at line 84 of file register.cc.

 {
     int64_t time_ns = PerformanceTimer::query() - state.begin_ns;
     runtime_ns += time_ns;
     current_pass = state.parent_pass;
     if (current_pass)
         current_pass->runtime_ns -= time_ns;
 }

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Pass::pre_post_exec_state_t Pass::pre_execute ( )

inherited

Definition at line 74 of file register.cc.

 {
     pre_post_exec_state_t state;
     call_counter++;
     state.begin_ns = PerformanceTimer::query();
     state.parent_pass = current_pass;
     current_pass = this;
     return state;
 }

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void Pass::run_register ( )

virtualinherited

Reimplemented in Backend, and Frontend.

Definition at line 48 of file register.cc.

 {
     log_assert(pass_register.count(pass_name) == 0);
     pass_register[pass_name] = this;
 }

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Field Documentation

int Pass::call_counter

inherited

Definition at line 36 of file register.h.

Pass* Pass::next_queued_pass

inherited

Definition at line 60 of file register.h.

std::string Pass::pass_name

inherited

Definition at line 29 of file register.h.

int64_t Pass::runtime_ns

inherited

Definition at line 37 of file register.h.

std::string Pass::short_help

inherited

Definition at line 29 of file register.h.

The documentation for this struct was generated from the following file:

eval.cc

Public Member Functions

Static Public Member Functions

Data Fields

Detailed Description

Constructor & Destructor Documentation

Member Function Documentation

Field Documentation