226 std::string global_arst;
227 bool global_arst_neg =
false;
229 log_header(
"Executing PROC_ARST pass (detect async resets in processes).\n");
232 for (argidx = 1; argidx <
args.size(); argidx++)
234 if (
args[argidx] ==
"-global_arst" && argidx+1 <
args.size()) {
235 global_arst =
args[++argidx];
236 if (!global_arst.empty() && global_arst[0] ==
'!') {
237 global_arst_neg =
true;
238 global_arst = global_arst.substr(1);
248 for (
auto mod : design->
modules())
251 for (
auto &proc_it : mod->processes) {
252 if (!design->
selected(mod, proc_it.second))
255 if (global_arst.empty() || mod->wire(global_arst) ==
nullptr)
257 std::vector<RTLIL::SigSig> arst_actions;
258 for (
auto sync : proc_it.second->syncs)
260 for (
auto &act : sync->actions) {
262 for (
auto &chunk : act.first.chunks())
263 if (chunk.wire && chunk.wire->attributes.count(
"\\init")) {
265 value.
extend(chunk.wire->width,
false);
269 if (arst_sig.
size()) {
270 log(
"Added global reset to process %s: %s <- %s\n",
275 if (!arst_actions.empty()) {
278 sync->
signal = mod->wire(global_arst);
280 proc_it.second->syncs.push_back(sync);
bool selected(T1 *module) const
void log_header(const char *format,...)
const char * log_signal(const RTLIL::SigSpec &sig, bool autoint)
static std::string escape_id(std::string str)
void proc_arst(RTLIL::Module *mod, RTLIL::Process *proc, SigMap &assign_map)
std::vector< RTLIL::SigSig > actions
RTLIL::ObjRange< RTLIL::Module * > modules()
void log(const char *format,...)
RTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other=NULL) const
void append(const RTLIL::SigSpec &signal)
void extend(int width, bool is_signed=false)
void extra_args(std::vector< std::string > args, size_t argidx, RTLIL::Design *design, bool select=true)
std::pair< SigSpec, SigSpec > SigSig