85 bool got_value =
false;
86 bool undriven_mode =
false;
90 for (argidx = 1; argidx <
args.size(); argidx++)
92 if (
args[argidx] ==
"-undriven") {
96 if (
args[argidx] ==
"-zero") {
101 if (
args[argidx] ==
"-one") {
106 if (
args[argidx] ==
"-random" && !got_value && argidx+1 <
args.size()) {
110 for (
int i = 0; i < 10; i++)
119 log_cmd_error(
"One of the options -zero, -one, or -random <seed> must be specified.\n");
121 for (
auto &mod_it : design->
modules_)
130 log_error(
"The 'setundef' command can't operate in -undriven mode on modules with processes. Run 'proc' first.\n");
135 for (
auto &it : module->
wires_)
136 if (!it.second->port_input)
137 undriven_signals.
add(sigmap(it.second));
140 for (
auto &it : module->
cells_)
141 for (
auto &conn : it.second->connections())
143 undriven_signals.
del(sigmap(conn.second));
146 for (
auto &c : sig.
chunks()) {
148 for (
int i = 0; i < c.width; i++)
bool selected(T1 *module) const
std::map< RTLIL::IdString, RTLIL::Wire * > wires_
void rewrite_sigspecs(T functor)
void log_error(const char *format,...)
bool cell_known(RTLIL::IdString type)
void connect(const RTLIL::SigSig &conn)
bool cell_output(RTLIL::IdString type, RTLIL::IdString port)
RTLIL::SigSpec export_all()
void log_cmd_error(const char *format,...)
std::map< RTLIL::IdString, RTLIL::Process * > processes
void add(RTLIL::SigSpec sig)
std::map< RTLIL::IdString, RTLIL::Module * > modules_
std::map< RTLIL::IdString, RTLIL::Cell * > cells_
void append(const RTLIL::SigSpec &signal)
void del(RTLIL::SigSpec sig)
void extra_args(std::vector< std::string > args, size_t argidx, RTLIL::Design *design, bool select=true)
std::pair< SigSpec, SigSpec > SigSig
const std::vector< RTLIL::SigChunk > & chunks() const