Inheritance diagram for IopadmapPass:

Collaboration diagram for IopadmapPass:

Public Member Functions
	IopadmapPass ()

virtual void	help ()

virtual void	execute (std::vector< std::string > args, RTLIL::Design *design)

pre_post_exec_state_t	pre_execute ()

void	post_execute (pre_post_exec_state_t state)

void	cmd_log_args (const std::vector< std::string > &args)

void	cmd_error (const std::vector< std::string > &args, size_t argidx, std::string msg)

void	extra_args (std::vector< std::string > args, size_t argidx, RTLIL::Design *design, bool select=true)

virtual void	run_register ()

Static Public Member Functions
static void	call (RTLIL::Design *design, std::string command)

static void	call (RTLIL::Design *design, std::vector< std::string > args)

static void	call_on_selection (RTLIL::Design *design, const RTLIL::Selection &selection, std::string command)

static void	call_on_selection (RTLIL::Design *design, const RTLIL::Selection &selection, std::vector< std::string > args)

static void	call_on_module (RTLIL::Design design, RTLIL::Module module, std::string command)

static void	call_on_module (RTLIL::Design design, RTLIL::Module module, std::vector< std::string > args)

static void	init_register ()

static void	done_register ()

Data Fields
std::string	pass_name

std::string	short_help

int	call_counter

int64_t	runtime_ns

Pass *	next_queued_pass

Detailed Description

Definition at line 36 of file iopadmap.cc.

Constructor & Destructor Documentation

IopadmapPass::IopadmapPass ( )

inline

Definition at line 37 of file iopadmap.cc.

37 : Pass("iopadmap", "technology mapping of i/o pads (or buffers)") { }

Pass::Pass

Pass(std::string name, std::string short_help="** document me **")

Definition: register.cc:40

Member Function Documentation

void Pass::call	(	RTLIL::Design *	design,
		std::string	command
	)

staticinherited

Definition at line 146 of file register.cc.

 {
     std::vector<std::string> args;
 
     std::string cmd_buf = command;
     std::string tok = next_token(cmd_buf, " \t\r\n");
 
     if (tok.empty() || tok[0] == '#')
         return;
 
     if (tok[0] == '!') {
         cmd_buf = command.substr(command.find('!') + 1);
         while (!cmd_buf.empty() && (cmd_buf.back() == ' ' || cmd_buf.back() == '\t' ||
                 cmd_buf.back() == '\r' || cmd_buf.back() == '\n'))
             cmd_buf.resize(cmd_buf.size()-1);
         log_header("Shell command: %s\n", cmd_buf.c_str());
         int retCode = run_command(cmd_buf);
         if (retCode != 0)
             log_cmd_error("Shell command returned error code %d.\n", retCode);
         return;
     }
 
     while (!tok.empty()) {
         if (tok == "#")
             break;
         if (tok.back() == ';') {
             int num_semikolon = 0;
             while (!tok.empty() && tok.back() == ';')
                 tok.resize(tok.size()-1), num_semikolon++;
             if (!tok.empty())
                 args.push_back(tok);
             call(design, args);
             args.clear();
             if (num_semikolon == 2)
                 call(design, "clean");
             if (num_semikolon == 3)
                 call(design, "clean -purge");
         } else
             args.push_back(tok);
         tok = next_token(cmd_buf, " \t\r\n");
     }
 
     call(design, args);
 }

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void Pass::call	(	RTLIL::Design *	design,
		std::vector< std::string >	args
	)

staticinherited

Definition at line 191 of file register.cc.

 {
     if (args.size() == 0 || args[0][0] == '#')
         return;
 
     if (echo_mode) {
         log("%s", create_prompt(design, 0));
         for (size_t i = 0; i < args.size(); i++)
             log("%s%s", i ? " " : "", args[i].c_str());
         log("\n");
     }
 
     if (pass_register.count(args[0]) == 0)
         log_cmd_error("No such command: %s (type 'help' for a command overview)\n", args[0].c_str());
 
     size_t orig_sel_stack_pos = design->selection_stack.size();
     auto state = pass_register[args[0]]->pre_execute();
     pass_register[args[0]]->execute(args, design);
     pass_register[args[0]]->post_execute(state);
     while (design->selection_stack.size() > orig_sel_stack_pos)
         design->selection_stack.pop_back();
 
     design->check();
 }

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void Pass::call_on_module	(	RTLIL::Design *	design,
		RTLIL::Module *	module,
		std::string	command
	)

staticinherited

Definition at line 240 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module = module->name.str();
     design->selection_stack.push_back(RTLIL::Selection(false));
     design->selection_stack.back().select(module);
 
     Pass::call(design, command);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

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void Pass::call_on_module	(	RTLIL::Design *	design,
		RTLIL::Module *	module,
		std::vector< std::string >	args
	)

staticinherited

Definition at line 253 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module = module->name.str();
     design->selection_stack.push_back(RTLIL::Selection(false));
     design->selection_stack.back().select(module);
 
     Pass::call(design, args);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

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void Pass::call_on_selection	(	RTLIL::Design *	design,
		const RTLIL::Selection &	selection,
		std::string	command
	)

staticinherited

Definition at line 216 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module.clear();
     design->selection_stack.push_back(selection);
 
     Pass::call(design, command);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

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void Pass::call_on_selection	(	RTLIL::Design *	design,
		const RTLIL::Selection &	selection,
		std::vector< std::string >	args
	)

staticinherited

Definition at line 228 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module.clear();
     design->selection_stack.push_back(selection);
 
     Pass::call(design, args);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

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void Pass::cmd_error	(	const std::vector< std::string > &	args,
		size_t	argidx,
		std::string	msg
	)

inherited

Definition at line 110 of file register.cc.

 {
     std::string command_text;
     int error_pos = 0;
 
     for (size_t i = 0; i < args.size(); i++) {
         if (i < argidx)
             error_pos += args[i].size() + 1;
         command_text = command_text + (command_text.empty() ? "" : " ") + args[i];
     }
 
     log("\nSyntax error in command `%s':\n", command_text.c_str());
     help();
 
     log_cmd_error("Command syntax error: %s\n> %s\n> %*s^\n",
             msg.c_str(), command_text.c_str(), error_pos, "");
 }

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void Pass::cmd_log_args ( const std::vector< std::string > & args )

inherited

Definition at line 100 of file register.cc.

 {
     if (args.size() <= 1)
         return;
     log("Full command line:");
     for (size_t i = 0; i < args.size(); i++)
         log(" %s", args[i].c_str());
     log("\n");
 }

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void Pass::done_register ( )

staticinherited

Definition at line 62 of file register.cc.

 {
     frontend_register.clear();
     pass_register.clear();
     backend_register.clear();
     log_assert(first_queued_pass == NULL);
 }

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virtual void IopadmapPass::execute	(	std::vector< std::string >	args,
		RTLIL::Design *	design
	)

inlinevirtual

Implements Pass.

Definition at line 69 of file iopadmap.cc.

     {
         log_header("Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells).\n");
 
         std::string inpad_celltype, inpad_portname, inpad_portname2;
         std::string outpad_celltype, outpad_portname, outpad_portname2;
         std::string inoutpad_celltype, inoutpad_portname, inoutpad_portname2;
         std::string widthparam, nameparam;
         bool flag_bits = false;
 
         size_t argidx;
         for (argidx = 1; argidx < args.size(); argidx++)
         {
             std::string arg = args[argidx];
             if (arg == "-inpad" && argidx+2 < args.size()) {
                 inpad_celltype = args[++argidx];
                 inpad_portname = args[++argidx];
                 split_portname_pair(inpad_portname, inpad_portname2);
                 continue;
             }
             if (arg == "-outpad" && argidx+2 < args.size()) {
                 outpad_celltype = args[++argidx];
                 outpad_portname = args[++argidx];
                 split_portname_pair(outpad_portname, outpad_portname2);
                 continue;
             }
             if (arg == "-inoutpad" && argidx+2 < args.size()) {
                 inoutpad_celltype = args[++argidx];
                 inoutpad_portname = args[++argidx];
                 split_portname_pair(inoutpad_portname, inoutpad_portname2);
                 continue;
             }
             if (arg == "-widthparam" && argidx+1 < args.size()) {
                 widthparam = args[++argidx];
                 continue;
             }
             if (arg == "-nameparam" && argidx+1 < args.size()) {
                 nameparam = args[++argidx];
                 continue;
             }
             if (arg == "-bits") {
                 flag_bits = true;
                 continue;
             }
             break;
         }
         extra_args(args, argidx, design);
 
         for (auto &it : design->modules_)
         {
             RTLIL::Module *module = it.second;
 
             if (!design->selected(module) || module->get_bool_attribute("\\blackbox"))
                 continue;
 
             for (auto &it2 : module->wires_)
             {
                 RTLIL::Wire *wire = it2.second;
 
                 if (!wire->port_id || !design->selected(module, wire))
                     continue;
 
                 std::string celltype, portname, portname2;
 
                 if (wire->port_input && !wire->port_output) {
                     if (inpad_celltype.empty()) {
                         log("Don't map input port %s.%s: Missing option -inpad.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));
                         continue;
                     }
                     celltype = inpad_celltype;
                     portname = inpad_portname;
                     portname2 = inpad_portname2;
                 } else
                 if (!wire->port_input && wire->port_output) {
                     if (outpad_celltype.empty()) {
                         log("Don't map output port %s.%s: Missing option -outpad.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));
                         continue;
                     }
                     celltype = outpad_celltype;
                     portname = outpad_portname;
                     portname2 = outpad_portname2;
                 } else
                 if (wire->port_input && wire->port_output) {
                     if (inoutpad_celltype.empty()) {
                         log("Don't map inout port %s.%s: Missing option -inoutpad.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));
                         continue;
                     }
                     celltype = inoutpad_celltype;
                     portname = inoutpad_portname;
                     portname2 = inoutpad_portname2;
                 } else
                     log_abort();
 
                 if (!flag_bits && wire->width != 1 && widthparam.empty()) {
                     log("Don't map multi-bit port %s.%s: Missing option -widthparam or -bits.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));
                     continue;
                 }
 
                 log("Mapping port %s.%s using %s.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name), celltype.c_str());
 
                 RTLIL::Wire *new_wire = NULL;
                 if (!portname2.empty()) {
                     new_wire = module->addWire(NEW_ID, wire);
                     module->swap_names(new_wire, wire);
                 }
 
                 if (flag_bits)
                 {
                     for (int i = 0; i < wire->width; i++)
                     {
                         RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
                         cell->setPort(RTLIL::escape_id(portname), RTLIL::SigSpec(wire, i));
                         if (!portname2.empty())
                             cell->setPort(RTLIL::escape_id(portname2), RTLIL::SigSpec(new_wire, i));
                         if (!widthparam.empty())
                             cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1);
                         if (!nameparam.empty())
                             cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(stringf("%s[%d]", RTLIL::id2cstr(wire->name), i));
                         cell->attributes["\\keep"] = RTLIL::Const(1);
                     }
                 }
                 else
                 {
                     RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
                     cell->setPort(RTLIL::escape_id(portname), RTLIL::SigSpec(wire));
                     if (!portname2.empty())
                         cell->setPort(RTLIL::escape_id(portname2), RTLIL::SigSpec(new_wire));
                     if (!widthparam.empty())
                         cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width);
                     if (!nameparam.empty())
                         cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(RTLIL::id2cstr(wire->name));
                     cell->attributes["\\keep"] = RTLIL::Const(1);
                 }
 
                 wire->port_id = 0;
                 wire->port_input = false;
                 wire->port_output = false;
             }
 
             module->fixup_ports();
         }
     }

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void Pass::extra_args	(	std::vector< std::string >	args,
		size_t	argidx,
		RTLIL::Design *	design,
		bool	select = `true`
	)

inherited

Definition at line 128 of file register.cc.

 {
     for (; argidx < args.size(); argidx++)
     {
         std::string arg = args[argidx];
 
         if (arg.substr(0, 1) == "-")
             cmd_error(args, argidx, "Unknown option or option in arguments.");
 
         if (!select)
             cmd_error(args, argidx, "Extra argument.");
 
         handle_extra_select_args(this, args, argidx, args.size(), design);
         break;
     }
     // cmd_log_args(args);
 }

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virtual void IopadmapPass::help ( )

inlinevirtual

Reimplemented from Pass.

Definition at line 38 of file iopadmap.cc.

     {
         log("\n");
         log("    iopadmap [options] [selection]\n");
         log("\n");
         log("Map module inputs/outputs to PAD cells from a library. This pass\n");
         log("can only map to very simple PAD cells. Use 'techmap' to further map\n");
         log("the resulting cells to more sophisticated PAD cells.\n");
         log("\n");
         log("    -inpad <celltype> <portname>[:<portname>]\n");
         log("        Map module input ports to the given cell type with\n");
         log("        the given port name. if a 2nd portname is given, the\n");
         log("        signal is passed through the pad call, using the 2nd\n");
         log("        portname as output.\n");
         log("\n");
         log("    -outpad <celltype> <portname>[:<portname>]\n");
         log("    -inoutpad <celltype> <portname>[:<portname>]\n");
         log("        Similar to -inpad, but for output and inout ports.\n");
         log("\n");
         log("    -widthparam <param_name>\n");
         log("        Use the specified parameter name to set the port width.\n");
         log("\n");
         log("    -nameparam <param_name>\n");
         log("        Use the specified parameter to set the port name.\n");
         log("\n");
         log("    -bits\n");
         log("        create individual bit-wide buffers even for ports that\n");
         log("        are wider. (the default behavio is to create word-wide\n");
         log("        buffers use -widthparam to set the word size on the cell.)\n");
         log("\n");
     }

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void Pass::init_register ( )

staticinherited

Definition at line 54 of file register.cc.

 {
     while (first_queued_pass) {
         first_queued_pass->run_register();
         first_queued_pass = first_queued_pass->next_queued_pass;
     }
 }

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void Pass::post_execute ( Pass::pre_post_exec_state_t state )

inherited

Definition at line 84 of file register.cc.

 {
     int64_t time_ns = PerformanceTimer::query() - state.begin_ns;
     runtime_ns += time_ns;
     current_pass = state.parent_pass;
     if (current_pass)
         current_pass->runtime_ns -= time_ns;
 }

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Pass::pre_post_exec_state_t Pass::pre_execute ( )

inherited

Definition at line 74 of file register.cc.

 {
     pre_post_exec_state_t state;
     call_counter++;
     state.begin_ns = PerformanceTimer::query();
     state.parent_pass = current_pass;
     current_pass = this;
     return state;
 }

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void Pass::run_register ( )

virtualinherited

Reimplemented in Backend, and Frontend.

Definition at line 48 of file register.cc.

 {
     log_assert(pass_register.count(pass_name) == 0);
     pass_register[pass_name] = this;
 }

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Field Documentation

int Pass::call_counter

inherited

Definition at line 36 of file register.h.

Pass* Pass::next_queued_pass

inherited

Definition at line 60 of file register.h.

std::string Pass::pass_name

inherited

Definition at line 29 of file register.h.

int64_t Pass::runtime_ns

inherited

Definition at line 37 of file register.h.

std::string Pass::short_help

inherited

Definition at line 29 of file register.h.

The documentation for this struct was generated from the following file:

iopadmap.cc

Public Member Functions

Static Public Member Functions

Data Fields

Detailed Description

Constructor & Destructor Documentation

Member Function Documentation

Field Documentation