45 bool flag_input =
false;
46 bool flag_output =
false;
49 for (argidx = 1; argidx <
args.size(); argidx++)
51 if (
args[argidx] ==
"-input") {
55 if (
args[argidx] ==
"-output") {
59 if (
args[argidx] ==
"-port") {
68 std::vector<RTLIL::IdString> delete_mods;
70 for (
auto &mod_it : design->
modules_)
73 delete_mods.push_back(mod_it.first);
82 if (flag_input || flag_output) {
83 for (
auto &it : module->
wires_)
84 if (design->
selected(module, it.second)) {
86 it.second->port_input =
false;
88 it.second->port_output =
false;
94 std::set<RTLIL::Wire*> delete_wires;
95 std::set<RTLIL::Cell*> delete_cells;
96 std::set<RTLIL::IdString> delete_procs;
97 std::set<RTLIL::IdString> delete_mems;
99 for (
auto &it : module->
wires_)
100 if (design->
selected(module, it.second))
101 delete_wires.insert(it.second);
104 if (design->
selected(module, it.second))
105 delete_mems.insert(it.first);
107 for (
auto &it : module->
cells_) {
108 if (design->
selected(module, it.second))
109 delete_cells.insert(it.second);
110 if ((it.second->type ==
"$memrd" || it.second->type ==
"$memwr") &&
111 delete_mems.count(it.second->parameters.at(
"\\MEMID").decode_string()) != 0)
112 delete_cells.insert(it.second);
116 if (design->
selected(module, it.second))
117 delete_procs.insert(it.first);
119 for (
auto &it : delete_mems) {
124 for (
auto &it : delete_cells)
127 for (
auto &it : delete_procs) {
132 module->
remove(delete_wires);
137 for (
auto &it : delete_mods) {
bool selected(T1 *module) const
bool selected_module(RTLIL::IdString mod_name) const
std::map< RTLIL::IdString, RTLIL::Wire * > wires_
std::map< RTLIL::IdString, RTLIL::Memory * > memories
bool selected_whole_module(RTLIL::IdString mod_name) const
std::map< RTLIL::IdString, RTLIL::Process * > processes
std::map< RTLIL::IdString, RTLIL::Module * > modules_
std::map< RTLIL::IdString, RTLIL::Cell * > cells_
void remove(const std::set< RTLIL::Wire * > &wires)
void extra_args(std::vector< std::string > args, size_t argidx, RTLIL::Design *design, bool select=true)