memory_dff.cc File Reference

#include "kernel/register.h"
#include "kernel/log.h"
#include <stdlib.h>
#include <sstream>

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Data Structures
struct	MemoryDffPass

Functions
USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN void	normalize_sig (RTLIL::Module *module, RTLIL::SigSpec &sig)
bool	find_sig_before_dff (RTLIL::Module *module, std::vector< RTLIL::Cell * > &dff_cells, RTLIL::SigSpec &sig, RTLIL::SigSpec &clk, bool &clk_polarity, bool after=false)
void	handle_wr_cell (RTLIL::Module *module, std::vector< RTLIL::Cell * > &dff_cells, RTLIL::Cell *cell)
void	disconnect_dff (RTLIL::Module *module, RTLIL::SigSpec sig)
void	handle_rd_cell (RTLIL::Module *module, std::vector< RTLIL::Cell * > &dff_cells, RTLIL::Cell *cell)
void	handle_module (RTLIL::Module *module, bool flag_wr_only)

Variables
MemoryDffPass	MemoryDffPass

Function Documentation

void disconnect_dff	(	RTLIL::Module *	module,
		RTLIL::SigSpec	sig
	)

Definition at line 111 of file memory_dff.cc.

{
    normalize_sig(module, sig);
    sig.sort_and_unify();

    std::stringstream sstr;
    sstr << "$memory_dff_disconnected$" << (autoidx++);

    RTLIL::SigSpec new_sig = module->addWire(sstr.str(), sig.size());

    for (auto cell : module->cells())
        if (cell->type == "$dff") {
            RTLIL::SigSpec new_q = cell->getPort("\\Q");
            new_q.replace(sig, new_sig);
            cell->setPort("\\Q", new_q);
        }
}

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bool find_sig_before_dff	(	RTLIL::Module *	module,
		std::vector< RTLIL::Cell * > &	dff_cells,
		RTLIL::SigSpec &	sig,
		RTLIL::SigSpec &	clk,
		bool &	clk_polarity,
		bool	after = false
	)

Definition at line 34 of file memory_dff.cc.

{
    normalize_sig(module, sig);

    for (auto &bit : sig)
    {
        if (bit.wire == NULL)
            continue;

        for (auto cell : dff_cells)
        {
            if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) {
                if (cell->getPort("\\CLK") != clk)
                    continue;
                if (cell->parameters["\\CLK_POLARITY"].as_bool() != clk_polarity)
                    continue;
            }

            RTLIL::SigSpec q_norm = cell->getPort(after ? "\\D" : "\\Q");
            normalize_sig(module, q_norm);

            RTLIL::SigSpec d = q_norm.extract(bit, &cell->getPort(after ? "\\Q" : "\\D"));
            if (d.size() != 1)
                continue;

            bit = d;
            clk = cell->getPort("\\CLK");
            clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool();
            goto replaced_this_bit;
        }

        return false;
    replaced_this_bit:;
    }

    return true;
}

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void handle_module	(	RTLIL::Module *	module,
		bool	flag_wr_only
	)

Definition at line 167 of file memory_dff.cc.

{
    std::vector<RTLIL::Cell*> dff_cells;

    for (auto cell : module->cells())
        if (cell->type == "$dff")
            dff_cells.push_back(cell);

    for (auto cell : module->selected_cells())
        if (cell->type == "$memwr" && !cell->parameters["\\CLK_ENABLE"].as_bool())
            handle_wr_cell(module, dff_cells, cell);

    if (!flag_wr_only)
        for (auto cell : module->selected_cells())
            if (cell->type == "$memrd" && !cell->parameters["\\CLK_ENABLE"].as_bool())
                handle_rd_cell(module, dff_cells, cell);
}

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void handle_rd_cell	(	RTLIL::Module *	module,
		std::vector< RTLIL::Cell * > &	dff_cells,
		RTLIL::Cell *	cell
	)

Definition at line 129 of file memory_dff.cc.

{
    log("Checking cell `%s' in module `%s': ", cell->name.c_str(), module->name.c_str());

    bool clk_polarity = 0;

    RTLIL::SigSpec clk_data = RTLIL::SigSpec(RTLIL::State::Sx);
    RTLIL::SigSpec sig_data = cell->getPort("\\DATA");
    if (find_sig_before_dff(module, dff_cells, sig_data, clk_data, clk_polarity, true) &&
            clk_data != RTLIL::SigSpec(RTLIL::State::Sx))
    {
        disconnect_dff(module, sig_data);
        cell->setPort("\\CLK", clk_data);
        cell->setPort("\\DATA", sig_data);
        cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
        cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
        cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0);
        log("merged data $dff to cell.\n");
        return;
    }

    RTLIL::SigSpec clk_addr = RTLIL::SigSpec(RTLIL::State::Sx);
    RTLIL::SigSpec sig_addr = cell->getPort("\\ADDR");
    if (find_sig_before_dff(module, dff_cells, sig_addr, clk_addr, clk_polarity) &&
            clk_addr != RTLIL::SigSpec(RTLIL::State::Sx))
    {
        cell->setPort("\\CLK", clk_addr);
        cell->setPort("\\ADDR", sig_addr);
        cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
        cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
        cell->parameters["\\TRANSPARENT"] = RTLIL::Const(1);
        log("merged address $dff to cell.\n");
        return;
    }

    log("no (compatible) $dff found.\n");
}

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void handle_wr_cell	(	RTLIL::Module *	module,
		std::vector< RTLIL::Cell * > &	dff_cells,
		RTLIL::Cell *	cell
	)

Definition at line 72 of file memory_dff.cc.

{
    log("Checking cell `%s' in module `%s': ", cell->name.c_str(), module->name.c_str());

    RTLIL::SigSpec clk = RTLIL::SigSpec(RTLIL::State::Sx);
    bool clk_polarity = 0;

    RTLIL::SigSpec sig_addr = cell->getPort("\\ADDR");
    if (!find_sig_before_dff(module, dff_cells, sig_addr, clk, clk_polarity)) {
        log("no (compatible) $dff for address input found.\n");
        return;
    }

    RTLIL::SigSpec sig_data = cell->getPort("\\DATA");
    if (!find_sig_before_dff(module, dff_cells, sig_data, clk, clk_polarity)) {
        log("no (compatible) $dff for data input found.\n");
        return;
    }

    RTLIL::SigSpec sig_en = cell->getPort("\\EN");
    if (!find_sig_before_dff(module, dff_cells, sig_en, clk, clk_polarity)) {
        log("no (compatible) $dff for enable input found.\n");
        return;
    }

    if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) {
        cell->setPort("\\CLK", clk);
        cell->setPort("\\ADDR", sig_addr);
        cell->setPort("\\DATA", sig_data);
        cell->setPort("\\EN", sig_en);
        cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
        cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
        log("merged $dff to cell.\n");
        return;
    }

    log("no (compatible) $dff found.\n");
}

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USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN void normalize_sig	(	RTLIL::Module *	module,
		RTLIL::SigSpec &	sig
	)

Definition at line 28 of file memory_dff.cc.

{
    for (auto &conn : module->connections())
        sig.replace(conn.first, conn.second);
}

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Variable Documentation

MemoryDffPass MemoryDffPass