37 if (!args[argidx].empty() && args[argidx][0] ==
'"') {
38 std::string str = args[argidx++].substr(1);
39 while (str.size() != 0 && str[str.size()-1] !=
'"' && argidx < args.size())
40 str += args[argidx++];
41 if (str.size() != 0 && str[str.size()-1] ==
'"')
42 str = str.substr(0, str.size()-1);
47 log_cmd_error(
"Can't decode value '%s'!\n", args[argidx-1].c_str());
53 static void do_setunset(std::map<RTLIL::IdString, RTLIL::Const> &attrs, std::vector<setunset_t> &list)
55 for (
auto &item : list)
57 attrs.erase(item.name);
59 attrs[item.name] = item.value;
68 log(
" setattr [ -mod ] [ -set name value | -unset name ]... [selection]\n");
70 log(
"Set/unset the given attributes on the selected objects. String values must be\n");
71 log(
"passed in double quotes (\").\n");
73 log(
"When called with -mod, this command will set and unset attributes on modules\n");
74 log(
"instead of objects within modules.\n");
79 std::vector<setunset_t> setunset_list;
80 bool flag_mod =
false;
83 for (argidx = 1; argidx < args.size(); argidx++)
85 std::string arg = args[argidx];
86 if (arg ==
"-set" && argidx+2 < args.size()) {
88 setunset_list.push_back(
setunset_t(args[argidx-1], args, argidx));
92 if (arg ==
"-unset" && argidx+1 < args.size()) {
93 setunset_list.push_back(
setunset_t(args[++argidx]));
117 for (
auto &it : module->
wires_)
118 if (design->
selected(module, it.second))
122 if (design->
selected(module, it.second))
125 for (
auto &it : module->
cells_)
126 if (design->
selected(module, it.second))
130 if (design->
selected(module, it.second))
142 log(
" setparam [ -set name value | -unset name ]... [selection]\n");
144 log(
"Set/unset the given parameters on the selected cells. String values must be\n");
145 log(
"passed in double quotes (\").\n");
150 std::vector<setunset_t> setunset_list;
153 for (argidx = 1; argidx < args.size(); argidx++)
155 std::string arg = args[argidx];
156 if (arg ==
"-set" && argidx+2 < args.size()) {
158 setunset_list.push_back(
setunset_t(args[argidx-1], args, argidx));
162 if (arg ==
"-unset" && argidx+1 < args.size()) {
163 setunset_list.push_back(
setunset_t(args[++argidx]));
177 for (
auto &it : module->
cells_)
178 if (design->
selected(module, it.second))
bool selected(T1 *module) const
RTLIL::Const as_const() const
std::map< RTLIL::IdString, RTLIL::Wire * > wires_
virtual void execute(std::vector< std::string > args, RTLIL::Design *design)
std::map< RTLIL::IdString, RTLIL::Memory * > memories
static void do_setunset(std::map< RTLIL::IdString, RTLIL::Const > &attrs, std::vector< setunset_t > &list)
static std::string escape_id(std::string str)
setunset_t(std::string unset_name)
#define PRIVATE_NAMESPACE_BEGIN
SetparamPass SetparamPass
bool selected_whole_module(RTLIL::IdString mod_name) const
#define PRIVATE_NAMESPACE_END
void log_cmd_error(const char *format,...)
std::map< RTLIL::IdString, RTLIL::Process * > processes
#define USING_YOSYS_NAMESPACE
std::map< RTLIL::IdString, RTLIL::Module * > modules_
std::map< RTLIL::IdString, RTLIL::Cell * > cells_
virtual void execute(std::vector< std::string > args, RTLIL::Design *design)
void log(const char *format,...)
setunset_t(std::string set_name, std::vector< std::string > args, size_t &argidx)
void extra_args(std::vector< std::string > args, size_t argidx, RTLIL::Design *design, bool select=true)
static bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)