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BlifDumper Struct Reference
+ Collaboration diagram for BlifDumper:

Public Member Functions

 BlifDumper (std::ostream &f, RTLIL::Module *module, RTLIL::Design *design, BlifDumperConfig *config)
 
const char * cstr (RTLIL::IdString id)
 
const char * cstr (RTLIL::SigBit sig)
 
const char * subckt_or_gate (std::string cell_type)
 
void dump ()
 

Static Public Member Functions

static void dump (std::ostream &f, RTLIL::Module *module, RTLIL::Design *design, BlifDumperConfig &config)
 

Data Fields

std::ostream & f
 
RTLIL::Module * module
 
RTLIL::Design * design
 
BlifDumperConfig * config
 
CellTypes ct
 
std::vector< std::string > cstr_buf
 

Detailed Description

Definition at line 50 of file blif.cc.

Constructor & Destructor Documentation

BlifDumper::BlifDumper ( std::ostream &  f,
RTLIL::Module *  module,
RTLIL::Design *  design,
BlifDumperConfig *  config 
)
inline

Definition at line 58 of file blif.cc.

58  :
59  f(f), module(module), design(design), config(config), ct(design)
60  {
61  }
BlifDumper::config
BlifDumperConfig * config
Definition: blif.cc:55
BlifDumper::f
std::ostream & f
Definition: blif.cc:52
BlifDumper::ct
CellTypes ct
Definition: blif.cc:56
BlifDumper::design
RTLIL::Design * design
Definition: blif.cc:54
BlifDumper::module
RTLIL::Module * module
Definition: blif.cc:53

Member Function Documentation

const char* BlifDumper::cstr ( RTLIL::IdString  id)
inline

Definition at line 65 of file blif.cc.

66  {
67  std::string str = RTLIL::unescape_id(id);
68  for (size_t i = 0; i < str.size(); i++)
69  if (str[i] == '#' || str[i] == '=')
70  str[i] = '?';
71  cstr_buf.push_back(str);
72  return cstr_buf.back().c_str();
73  }
RTLIL::unescape_id
static std::string unescape_id(std::string str)
Definition: rtlil.h:257
BlifDumper::cstr_buf
std::vector< std::string > cstr_buf
Definition: blif.cc:63

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const char* BlifDumper::cstr ( RTLIL::SigBit  sig)
inline

Definition at line 75 of file blif.cc.

76  {
77  if (sig.wire == NULL) {
78  if (sig == RTLIL::State::S0) return config->false_type == "-" ? config->false_out.c_str() : "$false";
79  if (sig == RTLIL::State::S1) return config->true_type == "-" ? config->true_out.c_str() : "$true";
80  return config->undef_type == "-" ? config->undef_out.c_str() : "$undef";
81  }
82 
83  std::string str = RTLIL::unescape_id(sig.wire->name);
84  for (size_t i = 0; i < str.size(); i++)
85  if (str[i] == '#' || str[i] == '=')
86  str[i] = '?';
87 
88  if (sig.wire->width != 1)
89  str += stringf("[%d]", sig.offset);
90 
91  cstr_buf.push_back(str);
92  return cstr_buf.back().c_str();
93  }
RTLIL::SigBit::wire
RTLIL::Wire * wire
Definition: rtlil.h:907
BlifDumperConfig::undef_out
std::string undef_out
Definition: blif.cc:45
stringf
std::string stringf(const char *fmt,...)
Definition: yosys.cc:58
BlifDumper::config
BlifDumperConfig * config
Definition: blif.cc:55
BlifDumperConfig::true_out
std::string true_out
Definition: blif.cc:45
RTLIL::unescape_id
static std::string unescape_id(std::string str)
Definition: rtlil.h:257
RTLIL::Wire::width
int width
Definition: rtlil.h:826
BlifDumper::cstr_buf
std::vector< std::string > cstr_buf
Definition: blif.cc:63
BlifDumperConfig::true_type
std::string true_type
Definition: blif.cc:45
RTLIL::SigBit::offset
int offset
Definition: rtlil.h:910
BlifDumperConfig::false_type
std::string false_type
Definition: blif.cc:45
RTLIL::Wire::name
RTLIL::IdString name
Definition: rtlil.h:825
BlifDumperConfig::false_out
std::string false_out
Definition: blif.cc:45
NULL
#define NULL
Definition: NumberlikeArray.hh:6
BlifDumperConfig::undef_type
std::string undef_type
Definition: blif.cc:45

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void BlifDumper::dump ( )
inline

Definition at line 106 of file blif.cc.

107  {
108  f << stringf("\n");
109  f << stringf(".model %s\n", cstr(module->name));
110 
111  std::map<int, RTLIL::Wire*> inputs, outputs;
112 
113  for (auto &wire_it : module->wires_) {
114  RTLIL::Wire *wire = wire_it.second;
115  if (wire->port_input)
116  inputs[wire->port_id] = wire;
117  if (wire->port_output)
118  outputs[wire->port_id] = wire;
119  }
120 
121  f << stringf(".inputs");
122  for (auto &it : inputs) {
123  RTLIL::Wire *wire = it.second;
124  for (int i = 0; i < wire->width; i++)
125  f << stringf(" %s", cstr(RTLIL::SigSpec(wire, i)));
126  }
127  f << stringf("\n");
128 
129  f << stringf(".outputs");
130  for (auto &it : outputs) {
131  RTLIL::Wire *wire = it.second;
132  for (int i = 0; i < wire->width; i++)
133  f << stringf(" %s", cstr(RTLIL::SigSpec(wire, i)));
134  }
135  f << stringf("\n");
136 
137  if (module->get_bool_attribute("\\blackbox")) {
138  f << stringf(".blackbox\n");
139  f << stringf(".end\n");
140  return;
141  }
142 
143  if (!config->impltf_mode) {
144  if (!config->false_type.empty()) {
145  if (config->false_type != "-")
146  f << stringf(".%s %s %s=$false\n", subckt_or_gate(config->false_type),
147  config->false_type.c_str(), config->false_out.c_str());
148  } else
149  f << stringf(".names $false\n");
150  if (!config->true_type.empty()) {
151  if (config->true_type != "-")
152  f << stringf(".%s %s %s=$true\n", subckt_or_gate(config->true_type),
153  config->true_type.c_str(), config->true_out.c_str());
154  } else
155  f << stringf(".names $true\n1\n");
156  if (!config->undef_type.empty()) {
157  if (config->undef_type != "-")
158  f << stringf(".%s %s %s=$undef\n", subckt_or_gate(config->undef_type),
159  config->undef_type.c_str(), config->undef_out.c_str());
160  } else
161  f << stringf(".names $undef\n");
162  }
163 
164  for (auto &cell_it : module->cells_)
165  {
166  RTLIL::Cell *cell = cell_it.second;
167 
168  if (config->unbuf_types.count(cell->type)) {
169  auto portnames = config->unbuf_types.at(cell->type);
170  f << stringf(".names %s %s\n1 1\n",
171  cstr(cell->getPort(portnames.first)), cstr(cell->getPort(portnames.second)));
172  continue;
173  }
174 
175  if (!config->icells_mode && cell->type == "$_NOT_") {
176  f << stringf(".names %s %s\n0 1\n",
177  cstr(cell->getPort("\\A")), cstr(cell->getPort("\\Y")));
178  continue;
179  }
180 
181  if (!config->icells_mode && cell->type == "$_AND_") {
182  f << stringf(".names %s %s %s\n11 1\n",
183  cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y")));
184  continue;
185  }
186 
187  if (!config->icells_mode && cell->type == "$_OR_") {
188  f << stringf(".names %s %s %s\n1- 1\n-1 1\n",
189  cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y")));
190  continue;
191  }
192 
193  if (!config->icells_mode && cell->type == "$_XOR_") {
194  f << stringf(".names %s %s %s\n10 1\n01 1\n",
195  cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y")));
196  continue;
197  }
198 
199  if (!config->icells_mode && cell->type == "$_MUX_") {
200  f << stringf(".names %s %s %s %s\n1-0 1\n-11 1\n",
201  cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")),
202  cstr(cell->getPort("\\S")), cstr(cell->getPort("\\Y")));
203  continue;
204  }
205 
206  if (!config->icells_mode && cell->type == "$_DFF_N_") {
207  f << stringf(".latch %s %s fe %s\n",
208  cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Q")), cstr(cell->getPort("\\C")));
209  continue;
210  }
211 
212  if (!config->icells_mode && cell->type == "$_DFF_P_") {
213  f << stringf(".latch %s %s re %s\n",
214  cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Q")), cstr(cell->getPort("\\C")));
215  continue;
216  }
217 
218  if (!config->icells_mode && cell->type == "$lut") {
219  f << stringf(".names");
220  auto &inputs = cell->getPort("\\A");
221  auto width = cell->parameters.at("\\WIDTH").as_int();
222  log_assert(inputs.size() == width);
223  for (int i = 0; i < inputs.size(); i++) {
224  f << stringf(" %s", cstr(inputs.extract(i, 1)));
225  }
226  auto &output = cell->getPort("\\Y");
227  log_assert(output.size() == 1);
228  f << stringf(" %s", cstr(output));
229  f << stringf("\n");
230  auto mask = cell->parameters.at("\\LUT").as_string();
231  for (int i = 0; i < (1 << width); i++) {
232  if (mask[i] == '0') continue;
233  for (int j = width-1; j >= 0; j--) {
234  f << ((i>>j)&1 ? '1' : '0');
235  }
236  f << stringf(" %c\n", mask[i]);
237  }
238  continue;
239  }
240 
241  f << stringf(".%s %s", subckt_or_gate(cell->type.str()), cstr(cell->type));
242  for (auto &conn : cell->connections())
243  for (int i = 0; i < conn.second.size(); i++) {
244  if (conn.second.size() == 1)
245  f << stringf(" %s", cstr(conn.first));
246  else
247  f << stringf(" %s[%d]", cstr(conn.first), i);
248  f << stringf("=%s", cstr(conn.second.extract(i, 1)));
249  }
250  f << stringf("\n");
251 
252  if (config->param_mode)
253  for (auto &param : cell->parameters) {
254  f << stringf(".param %s ", RTLIL::id2cstr(param.first));
255  if (param.second.flags & RTLIL::CONST_FLAG_STRING) {
256  std::string str = param.second.decode_string();
257  f << stringf("\"");
258  for (char ch : str)
259  if (ch == '"' || ch == '\\')
260  f << stringf("\\%c", ch);
261  else if (ch < 32 || ch >= 127)
262  f << stringf("\\%03o", ch);
263  else
264  f << stringf("%c", ch);
265  f << stringf("\"\n");
266  } else
267  f << stringf("%s\n", param.second.as_string().c_str());
268  }
269  }
270 
271  for (auto &conn : module->connections())
272  for (int i = 0; i < conn.first.size(); i++)
273  if (config->conn_mode)
274  f << stringf(".conn %s %s\n", cstr(conn.second.extract(i, 1)), cstr(conn.first.extract(i, 1)));
275  else if (!config->buf_type.empty())
276  f << stringf(".%s %s %s=%s %s=%s\n", subckt_or_gate(config->buf_type), config->buf_type.c_str(), config->buf_in.c_str(), cstr(conn.second.extract(i, 1)),
277  config->buf_out.c_str(), cstr(conn.first.extract(i, 1)));
278  else
279  f << stringf(".names %s %s\n1 1\n", cstr(conn.second.extract(i, 1)), cstr(conn.first.extract(i, 1)));
280 
281 
282  f << stringf(".end\n");
283  }
BlifDumperConfig::unbuf_types
std::map< RTLIL::IdString, std::pair< RTLIL::IdString, RTLIL::IdString > > unbuf_types
Definition: blif.cc:44
RTLIL::IdString::str
std::string str() const
Definition: rtlil.h:182
BlifDumperConfig::undef_out
std::string undef_out
Definition: blif.cc:45
stringf
std::string stringf(const char *fmt,...)
Definition: yosys.cc:58
BlifDumper::config
BlifDumperConfig * config
Definition: blif.cc:55
BlifDumperConfig::impltf_mode
bool impltf_mode
Definition: blif.cc:38
BlifDumperConfig::true_out
std::string true_out
Definition: blif.cc:45
BlifDumperConfig::conn_mode
bool conn_mode
Definition: blif.cc:37
RTLIL::Module::connections
const std::vector< RTLIL::SigSig > & connections() const
Definition: rtlil.cc:1307
RTLIL::Module::wires_
std::map< RTLIL::IdString, RTLIL::Wire * > wires_
Definition: rtlil.h:595
RTLIL::Wire::port_input
bool port_input
Definition: rtlil.h:827
RTLIL::Wire::width
int width
Definition: rtlil.h:826
BlifDumper::f
std::ostream & f
Definition: blif.cc:52
BlifDumperConfig::true_type
std::string true_type
Definition: blif.cc:45
RTLIL::Wire::port_id
int port_id
Definition: rtlil.h:826
RTLIL::Cell::type
RTLIL::IdString type
Definition: rtlil.h:854
RTLIL::Cell::parameters
std::map< RTLIL::IdString, RTLIL::Const > parameters
Definition: rtlil.h:856
BlifDumperConfig::param_mode
bool param_mode
Definition: blif.cc:40
RTLIL::Wire::port_output
bool port_output
Definition: rtlil.h:827
BlifDumperConfig::icells_mode
bool icells_mode
Definition: blif.cc:36
RTLIL::Cell::getPort
const RTLIL::SigSpec & getPort(RTLIL::IdString portname) const
Definition: rtlil.cc:1809
log_assert
#define log_assert(_assert_expr_)
Definition: log.h:85
RTLIL::Module::name
RTLIL::IdString name
Definition: rtlil.h:599
BlifDumperConfig::false_type
std::string false_type
Definition: blif.cc:45
BlifDumper::module
RTLIL::Module * module
Definition: blif.cc:53
RTLIL::id2cstr
static const char * id2cstr(const RTLIL::IdString &str)
Definition: rtlil.h:267
BlifDumperConfig::false_out
std::string false_out
Definition: blif.cc:45
RTLIL::Module::cells_
std::map< RTLIL::IdString, RTLIL::Cell * > cells_
Definition: rtlil.h:596
BlifDumperConfig::buf_out
std::string buf_out
Definition: blif.cc:43
BlifDumper::subckt_or_gate
const char * subckt_or_gate(std::string cell_type)
Definition: blif.cc:95
BlifDumperConfig::undef_type
std::string undef_type
Definition: blif.cc:45
BlifDumperConfig::buf_in
std::string buf_in
Definition: blif.cc:43
BlifDumper::cstr
const char * cstr(RTLIL::IdString id)
Definition: blif.cc:65
RTLIL::Cell::connections
const std::map< RTLIL::IdString, RTLIL::SigSpec > & connections() const
Definition: rtlil.cc:1814
BlifDumperConfig::buf_type
std::string buf_type
Definition: blif.cc:43

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static void BlifDumper::dump ( std::ostream &  f,
RTLIL::Module *  module,
RTLIL::Design *  design,
BlifDumperConfig &  config 
)
inlinestatic

Definition at line 285 of file blif.cc.

286  {
287  BlifDumper dumper(f, module, design, &config);
288  dumper.dump();
289  }
BlifDumper::f
std::ostream & f
Definition: blif.cc:52

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const char* BlifDumper::subckt_or_gate ( std::string  cell_type)
inline

Definition at line 95 of file blif.cc.

96  {
97  if (!config->gates_mode)
98  return "subckt";
99  if (!design->modules_.count(RTLIL::escape_id(cell_type)))
100  return "gate";
101  if (design->modules_.at(RTLIL::escape_id(cell_type))->get_bool_attribute("\\blackbox"))
102  return "gate";
103  return "subckt";
104  }
BlifDumper::config
BlifDumperConfig * config
Definition: blif.cc:55
RTLIL::escape_id
static std::string escape_id(std::string str)
Definition: rtlil.h:251
BlifDumper::design
RTLIL::Design * design
Definition: blif.cc:54
RTLIL::Design::modules_
std::map< RTLIL::IdString, RTLIL::Module * > modules_
Definition: rtlil.h:507
BlifDumperConfig::gates_mode
bool gates_mode
Definition: blif.cc:39

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Field Documentation

BlifDumperConfig* BlifDumper::config

Definition at line 55 of file blif.cc.

std::vector<std::string> BlifDumper::cstr_buf

Definition at line 63 of file blif.cc.

CellTypes BlifDumper::ct

Definition at line 56 of file blif.cc.

RTLIL::Design* BlifDumper::design

Definition at line 54 of file blif.cc.

std::ostream& BlifDumper::f

Definition at line 52 of file blif.cc.

RTLIL::Module* BlifDumper::module

Definition at line 53 of file blif.cc.

The documentation for this struct was generated from the following file: