Inheritance diagram for VerilogFrontend:

Collaboration diagram for VerilogFrontend:

Public Member Functions
	VerilogFrontend ()

virtual void	help ()

virtual void	execute (std::istream &f, std::string filename, std::vector< std::string > args, RTLIL::Design design)

virtual void	run_register ()

virtual void	execute (std::vector< std::string > args, RTLIL::Design *design) YS_OVERRIDE YS_FINAL

void	extra_args (std::istream *&f, std::string &filename, std::vector< std::string > args, size_t argidx)

void	extra_args (std::vector< std::string > args, size_t argidx, RTLIL::Design *design, bool select=true)

pre_post_exec_state_t	pre_execute ()

void	post_execute (pre_post_exec_state_t state)

void	cmd_log_args (const std::vector< std::string > &args)

void	cmd_error (const std::vector< std::string > &args, size_t argidx, std::string msg)

Static Public Member Functions
static void	frontend_call (RTLIL::Design design, std::istream f, std::string filename, std::string command)

static void	frontend_call (RTLIL::Design design, std::istream f, std::string filename, std::vector< std::string > args)

static void	call (RTLIL::Design *design, std::string command)

static void	call (RTLIL::Design *design, std::vector< std::string > args)

static void	call_on_selection (RTLIL::Design *design, const RTLIL::Selection &selection, std::string command)

static void	call_on_selection (RTLIL::Design *design, const RTLIL::Selection &selection, std::vector< std::string > args)

static void	call_on_module (RTLIL::Design design, RTLIL::Module module, std::string command)

static void	call_on_module (RTLIL::Design design, RTLIL::Module module, std::vector< std::string > args)

static void	init_register ()

static void	done_register ()

Data Fields
std::string	frontend_name

std::string	pass_name

std::string	short_help

int	call_counter

int64_t	runtime_ns

Pass *	next_queued_pass

Static Public Attributes
static FILE *	current_script_file = NULL

static std::string	last_here_document

static std::vector< std::string >	next_args

Detailed Description

Definition at line 42 of file verilog_frontend.cc.

Constructor & Destructor Documentation

VerilogFrontend::VerilogFrontend ( )

inline

Definition at line 43 of file verilog_frontend.cc.

43 : Frontend("verilog", "read modules from verilog file") { }

Frontend::Frontend

Frontend(std::string name, std::string short_help="** document me **")

Definition: register.cc:266

Member Function Documentation

void Pass::call	(	RTLIL::Design *	design,
		std::string	command
	)

staticinherited

Definition at line 146 of file register.cc.

 {
     std::vector<std::string> args;
 
     std::string cmd_buf = command;
     std::string tok = next_token(cmd_buf, " \t\r\n");
 
     if (tok.empty() || tok[0] == '#')
         return;
 
     if (tok[0] == '!') {
         cmd_buf = command.substr(command.find('!') + 1);
         while (!cmd_buf.empty() && (cmd_buf.back() == ' ' || cmd_buf.back() == '\t' ||
                 cmd_buf.back() == '\r' || cmd_buf.back() == '\n'))
             cmd_buf.resize(cmd_buf.size()-1);
         log_header("Shell command: %s\n", cmd_buf.c_str());
         int retCode = run_command(cmd_buf);
         if (retCode != 0)
             log_cmd_error("Shell command returned error code %d.\n", retCode);
         return;
     }
 
     while (!tok.empty()) {
         if (tok == "#")
             break;
         if (tok.back() == ';') {
             int num_semikolon = 0;
             while (!tok.empty() && tok.back() == ';')
                 tok.resize(tok.size()-1), num_semikolon++;
             if (!tok.empty())
                 args.push_back(tok);
             call(design, args);
             args.clear();
             if (num_semikolon == 2)
                 call(design, "clean");
             if (num_semikolon == 3)
                 call(design, "clean -purge");
         } else
             args.push_back(tok);
         tok = next_token(cmd_buf, " \t\r\n");
     }
 
     call(design, args);
 }

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void Pass::call	(	RTLIL::Design *	design,
		std::vector< std::string >	args
	)

staticinherited

Definition at line 191 of file register.cc.

 {
     if (args.size() == 0 || args[0][0] == '#')
         return;
 
     if (echo_mode) {
         log("%s", create_prompt(design, 0));
         for (size_t i = 0; i < args.size(); i++)
             log("%s%s", i ? " " : "", args[i].c_str());
         log("\n");
     }
 
     if (pass_register.count(args[0]) == 0)
         log_cmd_error("No such command: %s (type 'help' for a command overview)\n", args[0].c_str());
 
     size_t orig_sel_stack_pos = design->selection_stack.size();
     auto state = pass_register[args[0]]->pre_execute();
     pass_register[args[0]]->execute(args, design);
     pass_register[args[0]]->post_execute(state);
     while (design->selection_stack.size() > orig_sel_stack_pos)
         design->selection_stack.pop_back();
 
     design->check();
 }

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void Pass::call_on_module	(	RTLIL::Design *	design,
		RTLIL::Module *	module,
		std::string	command
	)

staticinherited

Definition at line 240 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module = module->name.str();
     design->selection_stack.push_back(RTLIL::Selection(false));
     design->selection_stack.back().select(module);
 
     Pass::call(design, command);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

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void Pass::call_on_module	(	RTLIL::Design *	design,
		RTLIL::Module *	module,
		std::vector< std::string >	args
	)

staticinherited

Definition at line 253 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module = module->name.str();
     design->selection_stack.push_back(RTLIL::Selection(false));
     design->selection_stack.back().select(module);
 
     Pass::call(design, args);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

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void Pass::call_on_selection	(	RTLIL::Design *	design,
		const RTLIL::Selection &	selection,
		std::string	command
	)

staticinherited

Definition at line 216 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module.clear();
     design->selection_stack.push_back(selection);
 
     Pass::call(design, command);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

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void Pass::call_on_selection	(	RTLIL::Design *	design,
		const RTLIL::Selection &	selection,
		std::vector< std::string >	args
	)

staticinherited

Definition at line 228 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module.clear();
     design->selection_stack.push_back(selection);
 
     Pass::call(design, args);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

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void Pass::cmd_error	(	const std::vector< std::string > &	args,
		size_t	argidx,
		std::string	msg
	)

inherited

Definition at line 110 of file register.cc.

 {
     std::string command_text;
     int error_pos = 0;
 
     for (size_t i = 0; i < args.size(); i++) {
         if (i < argidx)
             error_pos += args[i].size() + 1;
         command_text = command_text + (command_text.empty() ? "" : " ") + args[i];
     }
 
     log("\nSyntax error in command `%s':\n", command_text.c_str());
     help();
 
     log_cmd_error("Command syntax error: %s\n> %s\n> %*s^\n",
             msg.c_str(), command_text.c_str(), error_pos, "");
 }

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void Pass::cmd_log_args ( const std::vector< std::string > & args )

inherited

Definition at line 100 of file register.cc.

 {
     if (args.size() <= 1)
         return;
     log("Full command line:");
     for (size_t i = 0; i < args.size(); i++)
         log(" %s", args[i].c_str());
     log("\n");
 }

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void Pass::done_register ( )

staticinherited

Definition at line 62 of file register.cc.

 {
     frontend_register.clear();
     pass_register.clear();
     backend_register.clear();
     log_assert(first_queued_pass == NULL);
 }

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void Frontend::execute	(	std::vector< std::string >	args,
		RTLIL::Design *	design
	)

virtualinherited

Implements Pass.

Definition at line 285 of file register.cc.

 {
     log_assert(next_args.empty());
     do {
         std::istream *f = NULL;
         next_args.clear();
         auto state = pre_execute();
         execute(f, std::string(), args, design);
         post_execute(state);
         args = next_args;
         delete f;
     } while (!args.empty());
 }

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virtual void VerilogFrontend::execute	(	std::istream *&	f,
		std::string	filename,
		std::vector< std::string >	args,
		RTLIL::Design *	design
	)

inlinevirtual

Implements Frontend.

Definition at line 136 of file verilog_frontend.cc.

     {
         bool flag_dump_ast1 = false;
         bool flag_dump_ast2 = false;
         bool flag_dump_vlog = false;
         bool flag_nolatches = false;
         bool flag_nomem2reg = false;
         bool flag_mem2reg = false;
         bool flag_ppdump = false;
         bool flag_nopp = false;
         bool flag_lib = false;
         bool flag_noopt = false;
         bool flag_icells = false;
         bool flag_ignore_redef = false;
         bool flag_defer = false;
         std::map<std::string, std::string> defines_map;
         std::list<std::string> include_dirs;
         std::list<std::string> attributes;
 
         frontend_verilog_yydebug = false;
         sv_mode = false;
 
         log_header("Executing Verilog-2005 frontend.\n");
 
         args.insert(args.begin()+1, verilog_defaults.begin(), verilog_defaults.end());
 
         size_t argidx;
         for (argidx = 1; argidx < args.size(); argidx++) {
             std::string arg = args[argidx];
             if (arg == "-sv") {
                 sv_mode = true;
                 continue;
             }
             if (arg == "-dump_ast1") {
                 flag_dump_ast1 = true;
                 continue;
             }
             if (arg == "-dump_ast2") {
                 flag_dump_ast2 = true;
                 continue;
             }
             if (arg == "-dump_vlog") {
                 flag_dump_vlog = true;
                 continue;
             }
             if (arg == "-yydebug") {
                 frontend_verilog_yydebug = true;
                 continue;
             }
             if (arg == "-nolatches") {
                 flag_nolatches = true;
                 continue;
             }
             if (arg == "-nomem2reg") {
                 flag_nomem2reg = true;
                 continue;
             }
             if (arg == "-mem2reg") {
                 flag_mem2reg = true;
                 continue;
             }
             if (arg == "-ppdump") {
                 flag_ppdump = true;
                 continue;
             }
             if (arg == "-nopp") {
                 flag_nopp = true;
                 continue;
             }
             if (arg == "-lib") {
                 flag_lib = true;
                 continue;
             }
             if (arg == "-noopt") {
                 flag_noopt = true;
                 continue;
             }
             if (arg == "-icells") {
                 flag_icells = true;
                 continue;
             }
             if (arg == "-ignore_redef") {
                 flag_ignore_redef = true;
                 continue;
             }
             if (arg == "-defer") {
                 flag_defer = true;
                 continue;
             }
             if (arg == "-setattr" && argidx+1 < args.size()) {
                 attributes.push_back(RTLIL::escape_id(args[++argidx]));
                 continue;
             }
             if (arg == "-D" && argidx+1 < args.size()) {
                 std::string name = args[++argidx], value;
                 size_t equal = name.find('=', 2);
                 if (equal != std::string::npos) {
                     value = arg.substr(equal+1);
                     name = arg.substr(0, equal);
                 }
                 defines_map[name] = value;
                 continue;
             }
             if (arg.compare(0, 2, "-D") == 0) {
                 size_t equal = arg.find('=', 2);
                 std::string name = arg.substr(2, equal-2);
                 std::string value;
                 if (equal != std::string::npos)
                     value = arg.substr(equal+1);
                 defines_map[name] = value;
                 continue;
             }
             if (arg == "-I" && argidx+1 < args.size()) {
                 include_dirs.push_back(args[++argidx]);
                 continue;
             }
             if (arg.compare(0, 2, "-I") == 0) {
                 include_dirs.push_back(arg.substr(2));
                 continue;
             }
             break;
         }
         extra_args(f, filename, args, argidx);
 
         log("Parsing %s input from `%s' to AST representation.\n", sv_mode ? "SystemVerilog" : "Verilog", filename.c_str());
 
         AST::current_filename = filename;
         AST::set_line_num = &frontend_verilog_yyset_lineno;
         AST::get_line_num = &frontend_verilog_yyget_lineno;
 
         current_ast = new AST::AstNode(AST::AST_DESIGN);
         default_nettype_wire = true;
 
         lexin = f;
         std::string code_after_preproc;
 
         if (!flag_nopp) {
             code_after_preproc = frontend_verilog_preproc(*f, filename, defines_map, include_dirs);
             if (flag_ppdump)
                 log("-- Verilog code after preprocessor --\n%s-- END OF DUMP --\n", code_after_preproc.c_str());
             lexin = new std::istringstream(code_after_preproc);
         }
 
         frontend_verilog_yyset_lineno(1);
         frontend_verilog_yyrestart(NULL);
         frontend_verilog_yyparse();
         frontend_verilog_yylex_destroy();
 
         for (auto &child : current_ast->children) {
             if (child->type == AST::AST_MODULE)
                 for (auto &attr : attributes)
                     if (child->attributes.count(attr) == 0)
                         child->attributes[attr] = AST::AstNode::mkconst_int(1, false);
         }
 
         AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_ignore_redef, flag_defer, default_nettype_wire);
 
         if (!flag_nopp)
             delete lexin;
 
         delete current_ast;
         current_ast = NULL;
 
         log("Successfully finished Verilog frontend.\n");
     }

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void Pass::extra_args	(	std::vector< std::string >	args,
		size_t	argidx,
		RTLIL::Design *	design,
		bool	select = `true`
	)

inherited

Definition at line 128 of file register.cc.

 {
     for (; argidx < args.size(); argidx++)
     {
         std::string arg = args[argidx];
 
         if (arg.substr(0, 1) == "-")
             cmd_error(args, argidx, "Unknown option or option in arguments.");
 
         if (!select)
             cmd_error(args, argidx, "Extra argument.");
 
         handle_extra_select_args(this, args, argidx, args.size(), design);
         break;
     }
     // cmd_log_args(args);
 }

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void Frontend::extra_args	(	std::istream *&	f,
		std::string &	filename,
		std::vector< std::string >	args,
		size_t	argidx
	)

inherited

Definition at line 302 of file register.cc.

 {
     bool called_with_fp = f != NULL;
 
     next_args.clear();
     for (; argidx < args.size(); argidx++)
     {
         std::string arg = args[argidx];
 
         if (arg.substr(0, 1) == "-")
             cmd_error(args, argidx, "Unknown option or option in arguments.");
         if (f != NULL)
             cmd_error(args, argidx, "Extra filename argument in direct file mode.");
 
         filename = arg;
         if (filename == "<<" && argidx+1 < args.size())
             filename += args[++argidx];
         if (filename.substr(0, 2) == "<<") {
             if (Frontend::current_script_file == NULL)
                 log_error("Unexpected here document '%s' outside of script!\n", filename.c_str());
             if (filename.size() <= 2)
                 log_error("Missing EOT marker in here document!\n");
             std::string eot_marker = filename.substr(2);
             last_here_document.clear();
             while (1) {
                 std::string buffer;
                 char block[4096];
                 while (1) {
                     if (fgets(block, 4096, Frontend::current_script_file) == NULL)
                         log_error("Unexpected end of file in here document '%s'!\n", filename.c_str());
                     buffer += block;
                     if (buffer.size() > 0 && (buffer[buffer.size() - 1] == '\n' || buffer[buffer.size() - 1] == '\r'))
                         break;
                 }
                 size_t indent = buffer.find_first_not_of(" \t\r\n");
                 if (indent != std::string::npos && buffer.substr(indent, eot_marker.size()) == eot_marker)
                     break;
                 last_here_document += buffer;
             }
             f = new std::istringstream(last_here_document);
         } else {
             if (filename.substr(0, 2) == "+/")
                 filename = proc_share_dirname() + filename.substr(1);
             std::ifstream *ff = new std::ifstream;
             ff->open(filename.c_str());
             if (ff->fail())
                 delete ff;
             else
                 f = ff;
         }
         if (f == NULL)
             log_cmd_error("Can't open input file `%s' for reading: %s\n", filename.c_str(), strerror(errno));
 
         for (size_t i = argidx+1; i < args.size(); i++)
             if (args[i].substr(0, 1) == "-")
                 cmd_error(args, i, "Found option, expected arguments.");
 
         if (argidx+1 < args.size()) {
             next_args.insert(next_args.begin(), args.begin(), args.begin()+argidx);
             next_args.insert(next_args.begin()+argidx, args.begin()+argidx+1, args.end());
             args.erase(args.begin()+argidx+1, args.end());
         }
         break;
     }
     if (f == NULL)
         cmd_error(args, argidx, "No filename given.");
 
     if (called_with_fp)
         args.push_back(filename);
     args[0] = pass_name;
     // cmd_log_args(args);
 }

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void Frontend::frontend_call	(	RTLIL::Design *	design,
		std::istream *	f,
		std::string	filename,
		std::string	command
	)

staticinherited

Definition at line 375 of file register.cc.

 {
     std::vector<std::string> args;
     char *s = strdup(command.c_str());
     for (char *p = strtok(s, " \t\r\n"); p; p = strtok(NULL, " \t\r\n"))
         args.push_back(p);
     free(s);
     frontend_call(design, f, filename, args);
 }

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void Frontend::frontend_call	(	RTLIL::Design *	design,
		std::istream *	f,
		std::string	filename,
		std::vector< std::string >	args
	)

staticinherited

Definition at line 385 of file register.cc.

 {
     if (args.size() == 0)
         return;
     if (frontend_register.count(args[0]) == 0)
         log_cmd_error("No such frontend: %s\n", args[0].c_str());
 
     if (f != NULL) {
         auto state = frontend_register[args[0]]->pre_execute();
         frontend_register[args[0]]->execute(f, filename, args, design);
         frontend_register[args[0]]->post_execute(state);
     } else if (filename == "-") {
         std::istream *f_cin = &std::cin;
         auto state = frontend_register[args[0]]->pre_execute();
         frontend_register[args[0]]->execute(f_cin, "<stdin>", args, design);
         frontend_register[args[0]]->post_execute(state);
     } else {
         if (!filename.empty())
             args.push_back(filename);
         frontend_register[args[0]]->execute(args, design);
     }
 
     design->check();
 }

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virtual void VerilogFrontend::help ( )

inlinevirtual

Reimplemented from Pass.

Definition at line 44 of file verilog_frontend.cc.

     {
         //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
         log("\n");
         log("    read_verilog [options] [filename]\n");
         log("\n");
         log("Load modules from a verilog file to the current design. A large subset of\n");
         log("Verilog-2005 is supported.\n");
         log("\n");
         log("    -sv\n");
         log("        enable support for SystemVerilog features. (only a small subset\n");
         log("        of SystemVerilog is supported)\n");
         log("\n");
         log("    -dump_ast1\n");
         log("        dump abstract syntax tree (before simplification)\n");
         log("\n");
         log("    -dump_ast2\n");
         log("        dump abstract syntax tree (after simplification)\n");
         log("\n");
         log("    -dump_vlog\n");
         log("        dump ast as verilog code (after simplification)\n");
         log("\n");
         log("    -yydebug\n");
         log("        enable parser debug output\n");
         log("\n");
         log("    -nolatches\n");
         log("        usually latches are synthesized into logic loops\n");
         log("        this option prohibits this and sets the output to 'x'\n");
         log("        in what would be the latches hold condition\n");
         log("\n");
         log("        this behavior can also be achieved by setting the\n");
         log("        'nolatches' attribute on the respective module or\n");
         log("        always block.\n");
         log("\n");
         log("    -nomem2reg\n");
         log("        under certain conditions memories are converted to registers\n");
         log("        early during simplification to ensure correct handling of\n");
         log("        complex corner cases. this option disables this behavior.\n");
         log("\n");
         log("        this can also be achieved by setting the 'nomem2reg'\n");
         log("        attribute on the respective module or register.\n");
         log("\n");
         log("    -mem2reg\n");
         log("        always convert memories to registers. this can also be\n");
         log("        achieved by setting the 'mem2reg' attribute on the respective\n");
         log("        module or register.\n");
         log("\n");
         log("    -ppdump\n");
         log("        dump verilog code after pre-processor\n");
         log("\n");
         log("    -nopp\n");
         log("        do not run the pre-processor\n");
         log("\n");
         log("    -lib\n");
         log("        only create empty blackbox modules\n");
         log("\n");
         log("    -noopt\n");
         log("        don't perform basic optimizations (such as const folding) in the\n");
         log("        high-level front-end.\n");
         log("\n");
         log("    -icells\n");
         log("        interpret cell types starting with '$' as internal cell types\n");
         log("\n");
         log("    -ignore_redef\n");
         log("        ignore re-definitions of modules. (the default behavior is to\n");
         log("        create an error message.)\n");
         log("\n");
         log("    -defer\n");
         log("        only read the abstract syntax tree and defer actual compilation\n");
         log("        to a later 'hierarchy' command. Useful in cases where the default\n");
         log("        parameters of modules yield invalid or not synthesizable code.\n");
         log("\n");
         log("    -setattr <attribute_name>\n");
         log("        set the specified attribute (to the value 1) on all loaded modules\n");
         log("\n");
         log("    -Dname[=definition]\n");
         log("        define the preprocessor symbol 'name' and set its optional value\n");
         log("        'definition'\n");
         log("\n");
         log("    -Idir\n");
         log("        add 'dir' to the directories which are used when searching include\n");
         log("        files\n");
         log("\n");
         log("The command 'verilog_defaults' can be used to register default options for\n");
         log("subsequent calls to 'read_verilog'.\n");
         log("\n");
         log("Note that the Verilog frontend does a pretty good job of processing valid\n");
         log("verilog input, but has not very good error reporting. It generally is\n");
         log("recommended to use a simulator (for example icarus verilog) for checking\n");
         log("the syntax of the code, rather than to rely on read_verilog for that.\n");
         log("\n");
     }

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void Pass::init_register ( )

staticinherited

Definition at line 54 of file register.cc.

 {
     while (first_queued_pass) {
         first_queued_pass->run_register();
         first_queued_pass = first_queued_pass->next_queued_pass;
     }
 }

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void Pass::post_execute ( Pass::pre_post_exec_state_t state )

inherited

Definition at line 84 of file register.cc.

 {
     int64_t time_ns = PerformanceTimer::query() - state.begin_ns;
     runtime_ns += time_ns;
     current_pass = state.parent_pass;
     if (current_pass)
         current_pass->runtime_ns -= time_ns;
 }

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Pass::pre_post_exec_state_t Pass::pre_execute ( )

inherited

Definition at line 74 of file register.cc.

 {
     pre_post_exec_state_t state;
     call_counter++;
     state.begin_ns = PerformanceTimer::query();
     state.parent_pass = current_pass;
     current_pass = this;
     return state;
 }

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void Frontend::run_register ( )

virtualinherited

Reimplemented from Pass.

Definition at line 272 of file register.cc.

 {
     log_assert(pass_register.count(pass_name) == 0);
     pass_register[pass_name] = this;
 
     log_assert(frontend_register.count(frontend_name) == 0);
     frontend_register[frontend_name] = this;
 }

Field Documentation

int Pass::call_counter

inherited

Definition at line 36 of file register.h.

FILE * Frontend::current_script_file = NULL

staticinherited

Definition at line 69 of file register.h.

std::string Frontend::frontend_name

inherited

Definition at line 72 of file register.h.

std::string Frontend::last_here_document

staticinherited

Definition at line 70 of file register.h.

std::vector< std::string > Frontend::next_args

staticinherited

Definition at line 79 of file register.h.

Pass* Pass::next_queued_pass

inherited

Definition at line 60 of file register.h.

std::string Pass::pass_name

inherited

Definition at line 29 of file register.h.

int64_t Pass::runtime_ns

inherited

Definition at line 37 of file register.h.

std::string Pass::short_help

inherited

Definition at line 29 of file register.h.

The documentation for this struct was generated from the following file:

verilog_frontend.cc

Public Member Functions

Static Public Member Functions

Data Fields

Static Public Attributes

Detailed Description

Constructor & Destructor Documentation

Member Function Documentation

Field Documentation