Inheritance diagram for ExposePass:

Collaboration diagram for ExposePass:

Public Member Functions
	ExposePass ()

virtual void	help ()

virtual void	execute (std::vector< std::string > args, RTLIL::Design *design)

pre_post_exec_state_t	pre_execute ()

void	post_execute (pre_post_exec_state_t state)

void	cmd_log_args (const std::vector< std::string > &args)

void	cmd_error (const std::vector< std::string > &args, size_t argidx, std::string msg)

void	extra_args (std::vector< std::string > args, size_t argidx, RTLIL::Design *design, bool select=true)

virtual void	run_register ()

Static Public Member Functions
static void	call (RTLIL::Design *design, std::string command)

static void	call (RTLIL::Design *design, std::vector< std::string > args)

static void	call_on_selection (RTLIL::Design *design, const RTLIL::Selection &selection, std::string command)

static void	call_on_selection (RTLIL::Design *design, const RTLIL::Selection &selection, std::vector< std::string > args)

static void	call_on_module (RTLIL::Design design, RTLIL::Module module, std::string command)

static void	call_on_module (RTLIL::Design design, RTLIL::Module module, std::vector< std::string > args)

static void	init_register ()

static void	done_register ()

Data Fields
std::string	pass_name

std::string	short_help

int	call_counter

int64_t	runtime_ns

Pass *	next_queued_pass

Detailed Description

Definition at line 221 of file expose.cc.

Constructor & Destructor Documentation

ExposePass::ExposePass ( )

inline

Definition at line 222 of file expose.cc.

222 : Pass("expose", "convert internal signals to module ports") { }

Pass::Pass

Pass(std::string name, std::string short_help="** document me **")

Definition: register.cc:40

Member Function Documentation

void Pass::call	(	RTLIL::Design *	design,
		std::string	command
	)

staticinherited

Definition at line 146 of file register.cc.

 {
     std::vector<std::string> args;
 
     std::string cmd_buf = command;
     std::string tok = next_token(cmd_buf, " \t\r\n");
 
     if (tok.empty() || tok[0] == '#')
         return;
 
     if (tok[0] == '!') {
         cmd_buf = command.substr(command.find('!') + 1);
         while (!cmd_buf.empty() && (cmd_buf.back() == ' ' || cmd_buf.back() == '\t' ||
                 cmd_buf.back() == '\r' || cmd_buf.back() == '\n'))
             cmd_buf.resize(cmd_buf.size()-1);
         log_header("Shell command: %s\n", cmd_buf.c_str());
         int retCode = run_command(cmd_buf);
         if (retCode != 0)
             log_cmd_error("Shell command returned error code %d.\n", retCode);
         return;
     }
 
     while (!tok.empty()) {
         if (tok == "#")
             break;
         if (tok.back() == ';') {
             int num_semikolon = 0;
             while (!tok.empty() && tok.back() == ';')
                 tok.resize(tok.size()-1), num_semikolon++;
             if (!tok.empty())
                 args.push_back(tok);
             call(design, args);
             args.clear();
             if (num_semikolon == 2)
                 call(design, "clean");
             if (num_semikolon == 3)
                 call(design, "clean -purge");
         } else
             args.push_back(tok);
         tok = next_token(cmd_buf, " \t\r\n");
     }
 
     call(design, args);
 }

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void Pass::call	(	RTLIL::Design *	design,
		std::vector< std::string >	args
	)

staticinherited

Definition at line 191 of file register.cc.

 {
     if (args.size() == 0 || args[0][0] == '#')
         return;
 
     if (echo_mode) {
         log("%s", create_prompt(design, 0));
         for (size_t i = 0; i < args.size(); i++)
             log("%s%s", i ? " " : "", args[i].c_str());
         log("\n");
     }
 
     if (pass_register.count(args[0]) == 0)
         log_cmd_error("No such command: %s (type 'help' for a command overview)\n", args[0].c_str());
 
     size_t orig_sel_stack_pos = design->selection_stack.size();
     auto state = pass_register[args[0]]->pre_execute();
     pass_register[args[0]]->execute(args, design);
     pass_register[args[0]]->post_execute(state);
     while (design->selection_stack.size() > orig_sel_stack_pos)
         design->selection_stack.pop_back();
 
     design->check();
 }

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void Pass::call_on_module	(	RTLIL::Design *	design,
		RTLIL::Module *	module,
		std::string	command
	)

staticinherited

Definition at line 240 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module = module->name.str();
     design->selection_stack.push_back(RTLIL::Selection(false));
     design->selection_stack.back().select(module);
 
     Pass::call(design, command);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

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void Pass::call_on_module	(	RTLIL::Design *	design,
		RTLIL::Module *	module,
		std::vector< std::string >	args
	)

staticinherited

Definition at line 253 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module = module->name.str();
     design->selection_stack.push_back(RTLIL::Selection(false));
     design->selection_stack.back().select(module);
 
     Pass::call(design, args);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

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void Pass::call_on_selection	(	RTLIL::Design *	design,
		const RTLIL::Selection &	selection,
		std::string	command
	)

staticinherited

Definition at line 216 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module.clear();
     design->selection_stack.push_back(selection);
 
     Pass::call(design, command);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

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void Pass::call_on_selection	(	RTLIL::Design *	design,
		const RTLIL::Selection &	selection,
		std::vector< std::string >	args
	)

staticinherited

Definition at line 228 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module.clear();
     design->selection_stack.push_back(selection);
 
     Pass::call(design, args);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

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void Pass::cmd_error	(	const std::vector< std::string > &	args,
		size_t	argidx,
		std::string	msg
	)

inherited

Definition at line 110 of file register.cc.

 {
     std::string command_text;
     int error_pos = 0;
 
     for (size_t i = 0; i < args.size(); i++) {
         if (i < argidx)
             error_pos += args[i].size() + 1;
         command_text = command_text + (command_text.empty() ? "" : " ") + args[i];
     }
 
     log("\nSyntax error in command `%s':\n", command_text.c_str());
     help();
 
     log_cmd_error("Command syntax error: %s\n> %s\n> %*s^\n",
             msg.c_str(), command_text.c_str(), error_pos, "");
 }

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void Pass::cmd_log_args ( const std::vector< std::string > & args )

inherited

Definition at line 100 of file register.cc.

 {
     if (args.size() <= 1)
         return;
     log("Full command line:");
     for (size_t i = 0; i < args.size(); i++)
         log(" %s", args[i].c_str());
     log("\n");
 }

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void Pass::done_register ( )

staticinherited

Definition at line 62 of file register.cc.

 {
     frontend_register.clear();
     pass_register.clear();
     backend_register.clear();
     log_assert(first_queued_pass == NULL);
 }

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virtual void ExposePass::execute	(	std::vector< std::string >	args,
		RTLIL::Design *	design
	)

inlinevirtual

Implements Pass.

Definition at line 256 of file expose.cc.

     {
         bool flag_shared = false;
         bool flag_evert = false;
         bool flag_dff = false;
         bool flag_cut = false;
         bool flag_evert_dff = false;
         std::string sep = ".";
 
         log_header("Executing EXPOSE pass (exposing internal signals as outputs).\n");
 
         size_t argidx;
         for (argidx = 1; argidx < args.size(); argidx++)
         {
             if (args[argidx] == "-shared") {
                 flag_shared = true;
                 continue;
             }
             if (args[argidx] == "-evert") {
                 flag_evert = true;
                 continue;
             }
             if (args[argidx] == "-dff") {
                 flag_dff = true;
                 continue;
             }
             if (args[argidx] == "-cut") {
                 flag_cut = true;
                 continue;
             }
             if (args[argidx] == "-evert-dff") {
                 flag_evert_dff = true;
                 continue;
             }
             if (args[argidx] == "-sep" && argidx+1 < args.size()) {
                 sep = args[++argidx];
                 continue;
             }
             break;
         }
         extra_args(args, argidx, design);
 
         CellTypes ct(design);
 
         std::map<RTLIL::Module*, std::map<RTLIL::IdString, dff_map_info_t>> dff_dq_maps;
         std::map<RTLIL::Module*, std::set<RTLIL::IdString>> dff_cells;
 
         if (flag_evert_dff)
         {
             RTLIL::Module *first_module = NULL;
             std::set<RTLIL::IdString> shared_dff_wires;
 
             for (auto &mod_it : design->modules_)
             {
                 if (!design->selected(mod_it.second))
                     continue;
 
                 create_dff_dq_map(dff_dq_maps[mod_it.second], design, mod_it.second);
 
                 if (!flag_shared)
                     continue;
 
                 if (first_module == NULL) {
                     for (auto &it : dff_dq_maps[mod_it.second])
                         shared_dff_wires.insert(it.first);
                     first_module = mod_it.second;
                 } else {
                     std::set<RTLIL::IdString> new_shared_dff_wires;
                     for (auto &it : shared_dff_wires) {
                         if (!dff_dq_maps[mod_it.second].count(it))
                             continue;
                         if (!compare_wires(first_module->wires_.at(it), mod_it.second->wires_.at(it)))
                             continue;
                         new_shared_dff_wires.insert(it);
                     }
                     shared_dff_wires.swap(new_shared_dff_wires);
                 }
             }
 
             if (flag_shared)
                 for (auto &map_it : dff_dq_maps)
                 {
                     std::map<RTLIL::IdString, dff_map_info_t> new_map;
                     for (auto &it : map_it.second)
                         if (shared_dff_wires.count(it.first))
                             new_map[it.first] = it.second;
                     map_it.second.swap(new_map);
                 }
 
             for (auto &it1 : dff_dq_maps)
             for (auto &it2 : it1.second)
             for (auto &it3 : it2.second.cells)
                 dff_cells[it1.first].insert(it3);
         }
 
         std::set<RTLIL::IdString> shared_wires, shared_cells;
         std::set<RTLIL::IdString> used_names;
 
         if (flag_shared)
         {
             RTLIL::Module *first_module = NULL;
 
             for (auto &mod_it : design->modules_)
             {
                 RTLIL::Module *module = mod_it.second;
 
                 if (!design->selected(module))
                     continue;
 
                 std::set<RTLIL::IdString> dff_wires;
                 if (flag_dff)
                     find_dff_wires(dff_wires, module);
 
                 if (first_module == NULL)
                 {
                     for (auto &it : module->wires_)
                         if (design->selected(module, it.second) && consider_wire(it.second, dff_dq_maps[module]))
                             if (!flag_dff || dff_wires.count(it.first))
                                 shared_wires.insert(it.first);
 
                     if (flag_evert)
                         for (auto &it : module->cells_)
                             if (design->selected(module, it.second) && consider_cell(design, dff_cells[module], it.second))
                                 shared_cells.insert(it.first);
 
                     first_module = module;
                 }
                 else
                 {
                     std::vector<RTLIL::IdString> delete_shared_wires, delete_shared_cells;
 
                     for (auto &it : shared_wires)
                     {
                         RTLIL::Wire *wire;
 
                         if (module->wires_.count(it) == 0)
                             goto delete_shared_wire;
 
                         wire = module->wires_.at(it);
 
                         if (!design->selected(module, wire))
                             goto delete_shared_wire;
                         if (!consider_wire(wire, dff_dq_maps[module]))
                             goto delete_shared_wire;
                         if (!compare_wires(first_module->wires_.at(it), wire))
                             goto delete_shared_wire;
                         if (flag_dff && !dff_wires.count(it))
                             goto delete_shared_wire;
 
                         if (0)
                     delete_shared_wire:
                             delete_shared_wires.push_back(it);
                     }
 
                     if (flag_evert)
                         for (auto &it : shared_cells)
                         {
                             RTLIL::Cell *cell;
 
                             if (module->cells_.count(it) == 0)
                                 goto delete_shared_cell;
 
                             cell = module->cells_.at(it);
 
                             if (!design->selected(module, cell))
                                 goto delete_shared_cell;
                             if (!consider_cell(design, dff_cells[module], cell))
                                 goto delete_shared_cell;
                             if (!compare_cells(first_module->cells_.at(it), cell))
                                 goto delete_shared_cell;
 
                             if (0)
                         delete_shared_cell:
                                 delete_shared_cells.push_back(it);
                         }
 
                     for (auto &it : delete_shared_wires)
                         shared_wires.erase(it);
                     for (auto &it : delete_shared_cells)
                         shared_cells.erase(it);
                 }
             }
         }
 
         for (auto &mod_it : design->modules_)
         {
             RTLIL::Module *module = mod_it.second;
 
             if (!design->selected(module))
                 continue;
 
             std::set<RTLIL::IdString> dff_wires;
             if (flag_dff && !flag_shared)
                 find_dff_wires(dff_wires, module);
 
             SigMap sigmap(module);
 
             SigMap out_to_in_map;
 
             for (auto &it : module->wires_)
             {
                 if (flag_shared) {
                     if (shared_wires.count(it.first) == 0)
                         continue;
                 } else {
                     if (!design->selected(module, it.second) || !consider_wire(it.second, dff_dq_maps[module]))
                         continue;
                     if (flag_dff && !dff_wires.count(it.first))
                         continue;
                 }
 
                 if (!it.second->port_output) {
                     it.second->port_output = true;
                     log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it.second->name));
                 }
 
                 if (flag_cut) {
                     RTLIL::Wire *in_wire = add_new_wire(module, it.second->name.str() + sep + "i", it.second->width);
                     in_wire->port_input = true;
                     out_to_in_map.add(sigmap(it.second), in_wire);
                 }
             }
 
             if (flag_cut)
             {
                 for (auto &it : module->cells_) {
                     if (!ct.cell_known(it.second->type))
                         continue;
                     for (auto &conn : it.second->connections_)
                         if (ct.cell_input(it.second->type, conn.first))
                             conn.second = out_to_in_map(sigmap(conn.second));
                 }
 
                 for (auto &conn : module->connections_)
                     conn.second = out_to_in_map(sigmap(conn.second));
             }
 
             std::set<RTLIL::SigBit> set_q_bits;
 
             for (auto &dq : dff_dq_maps[module])
             {
                 if (!module->wires_.count(dq.first))
                     continue;
 
                 RTLIL::Wire *wire = module->wires_.at(dq.first);
                 std::set<RTLIL::SigBit> wire_bits_set = sigmap(wire).to_sigbit_set();
                 std::vector<RTLIL::SigBit> wire_bits_vec = sigmap(wire).to_sigbit_vector();
 
                 dff_map_info_t &info = dq.second;
 
                 RTLIL::Wire *wire_dummy_q = add_new_wire(module, NEW_ID, 0);
 
                 for (auto &cell_name : info.cells) {
                     RTLIL::Cell *cell = module->cells_.at(cell_name);
                     std::vector<RTLIL::SigBit> cell_q_bits = sigmap(cell->getPort("\\Q")).to_sigbit_vector();
                     for (auto &bit : cell_q_bits)
                         if (wire_bits_set.count(bit))
                             bit = RTLIL::SigBit(wire_dummy_q, wire_dummy_q->width++);
                     cell->setPort("\\Q", cell_q_bits);
                 }
 
                 RTLIL::Wire *wire_q = add_new_wire(module, wire->name.str() + sep + "q", wire->width);
                 wire_q->port_input = true;
                 log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_q->name));
 
                 RTLIL::SigSig connect_q;
                 for (size_t i = 0; i < wire_bits_vec.size(); i++) {
                     if (set_q_bits.count(wire_bits_vec[i]))
                         continue;
                     connect_q.first.append(wire_bits_vec[i]);
                     connect_q.second.append(RTLIL::SigBit(wire_q, i));
                     set_q_bits.insert(wire_bits_vec[i]);
                 }
                 module->connect(connect_q);
 
                 RTLIL::Wire *wire_d = add_new_wire(module, wire->name.str() + sep + "d", wire->width);
                 wire_d->port_output = true;
                 log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_d->name));
                 module->connect(RTLIL::SigSig(wire_d, info.sig_d));
 
                 RTLIL::Wire *wire_c = add_new_wire(module, wire->name.str() + sep + "c");
                 wire_c->port_output = true;
                 log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_c->name));
                 if (info.clk_polarity) {
                     module->connect(RTLIL::SigSig(wire_c, info.sig_clk));
                 } else {
                     RTLIL::Cell *c = module->addCell(NEW_ID, "$not");
                     c->parameters["\\A_SIGNED"] = 0;
                     c->parameters["\\A_WIDTH"] = 1;
                     c->parameters["\\Y_WIDTH"] = 1;
                     c->setPort("\\A", info.sig_clk);
                     c->setPort("\\Y", wire_c);
                 }
 
                 if (info.sig_arst != RTLIL::State::Sm)
                 {
                     RTLIL::Wire *wire_r = add_new_wire(module, wire->name.str() + sep + "r");
                     wire_r->port_output = true;
                     log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_r->name));
                     if (info.arst_polarity) {
                         module->connect(RTLIL::SigSig(wire_r, info.sig_arst));
                     } else {
                         RTLIL::Cell *c = module->addCell(NEW_ID, "$not");
                         c->parameters["\\A_SIGNED"] = 0;
                         c->parameters["\\A_WIDTH"] = 1;
                         c->parameters["\\Y_WIDTH"] = 1;
                         c->setPort("\\A", info.sig_arst);
                         c->setPort("\\Y", wire_r);
                     }
 
                     RTLIL::Wire *wire_v = add_new_wire(module, wire->name.str() + sep + "v", wire->width);
                     wire_v->port_output = true;
                     log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_v->name));
                     module->connect(RTLIL::SigSig(wire_v, info.arst_value));
                 }
             }
 
             if (flag_evert)
             {
                 std::vector<RTLIL::Cell*> delete_cells;
 
                 for (auto &it : module->cells_)
                 {
                     if (flag_shared) {
                         if (shared_cells.count(it.first) == 0)
                             continue;
                     } else {
                         if (!design->selected(module, it.second) || !consider_cell(design, dff_cells[module], it.second))
                             continue;
                     }
 
                     RTLIL::Cell *cell = it.second;
 
                     if (design->modules_.count(cell->type))
                     {
                         RTLIL::Module *mod = design->modules_.at(cell->type);
 
                         for (auto &it : mod->wires_)
                         {
                             RTLIL::Wire *p = it.second;
                             if (!p->port_input && !p->port_output)
                                 continue;
 
                             RTLIL::Wire *w = add_new_wire(module, cell->name.str() + sep + RTLIL::unescape_id(p->name), p->width);
                             if (p->port_input)
                                 w->port_output = true;
                             if (p->port_output)
                                 w->port_input = true;
 
                             log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type));
 
                             RTLIL::SigSpec sig;
                             if (cell->hasPort(p->name))
                                 sig = cell->getPort(p->name);
                             sig.extend(w->width);
                             if (w->port_input)
                                 module->connect(RTLIL::SigSig(sig, w));
                             else
                                 module->connect(RTLIL::SigSig(w, sig));
                         }
                     }
                     else
                     {
                         for (auto &it : cell->connections())
                         {
                             RTLIL::Wire *w = add_new_wire(module, cell->name.str() + sep + RTLIL::unescape_id(it.first), it.second.size());
                             if (ct.cell_input(cell->type, it.first))
                                 w->port_output = true;
                             if (ct.cell_output(cell->type, it.first))
                                 w->port_input = true;
 
                             log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type));
 
                             if (w->port_input)
                                 module->connect(RTLIL::SigSig(it.second, w));
                             else
                                 module->connect(RTLIL::SigSig(w, it.second));
                         }
                     }
 
                     delete_cells.push_back(cell);
                 }
 
                 for (auto cell : delete_cells) {
                     log("Removing cell: %s/%s (%s)\n", log_id(module), log_id(cell), log_id(cell->type));
                     module->remove(cell);
                 }
             }
 
             module->fixup_ports();
         }
     }

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void Pass::extra_args	(	std::vector< std::string >	args,
		size_t	argidx,
		RTLIL::Design *	design,
		bool	select = `true`
	)

inherited

Definition at line 128 of file register.cc.

 {
     for (; argidx < args.size(); argidx++)
     {
         std::string arg = args[argidx];
 
         if (arg.substr(0, 1) == "-")
             cmd_error(args, argidx, "Unknown option or option in arguments.");
 
         if (!select)
             cmd_error(args, argidx, "Extra argument.");
 
         handle_extra_select_args(this, args, argidx, args.size(), design);
         break;
     }
     // cmd_log_args(args);
 }

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virtual void ExposePass::help ( )

inlinevirtual

Reimplemented from Pass.

Definition at line 223 of file expose.cc.

     {
         //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
         log("\n");
         log("    expose [options] [selection]\n");
         log("\n");
         log("This command exposes all selected internal signals of a module as additional\n");
         log("outputs.\n");
         log("\n");
         log("    -dff\n");
         log("        only consider wires that are directly driven by register cell.\n");
         log("\n");
         log("    -cut\n");
         log("        when exposing a wire, create an input/output pair and cut the internal\n");
         log("        signal path at that wire.\n");
         log("\n");
         log("    -shared\n");
         log("        only expose those signals that are shared ammong the selected modules.\n");
         log("        this is useful for preparing modules for equivialence checking.\n");
         log("\n");
         log("    -evert\n");
         log("        also turn connections to instances of other modules to additional\n");
         log("        inputs and outputs and remove the module instances.\n");
         log("\n");
         log("    -evert-dff\n");
         log("        turn flip-flops to sets of inputs and outputs.\n");
         log("\n");
         log("    -sep <separator>\n");
         log("        when creating new wire/port names, the original object name is suffixed\n");
         log("        with this separator (default: '.') and the port name or a type\n");
         log("        designator for the exposed signal.\n");
         log("\n");
     }

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void Pass::init_register ( )

staticinherited

Definition at line 54 of file register.cc.

 {
     while (first_queued_pass) {
         first_queued_pass->run_register();
         first_queued_pass = first_queued_pass->next_queued_pass;
     }
 }

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void Pass::post_execute ( Pass::pre_post_exec_state_t state )

inherited

Definition at line 84 of file register.cc.

 {
     int64_t time_ns = PerformanceTimer::query() - state.begin_ns;
     runtime_ns += time_ns;
     current_pass = state.parent_pass;
     if (current_pass)
         current_pass->runtime_ns -= time_ns;
 }

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Pass::pre_post_exec_state_t Pass::pre_execute ( )

inherited

Definition at line 74 of file register.cc.

 {
     pre_post_exec_state_t state;
     call_counter++;
     state.begin_ns = PerformanceTimer::query();
     state.parent_pass = current_pass;
     current_pass = this;
     return state;
 }

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void Pass::run_register ( )

virtualinherited

Reimplemented in Backend, and Frontend.

Definition at line 48 of file register.cc.

 {
     log_assert(pass_register.count(pass_name) == 0);
     pass_register[pass_name] = this;
 }

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Field Documentation

int Pass::call_counter

inherited

Definition at line 36 of file register.h.

Pass* Pass::next_queued_pass

inherited

Definition at line 60 of file register.h.

std::string Pass::pass_name

inherited

Definition at line 29 of file register.h.

int64_t Pass::runtime_ns

inherited

Definition at line 37 of file register.h.

std::string Pass::short_help

inherited

Definition at line 29 of file register.h.

The documentation for this struct was generated from the following file:

expose.cc

Public Member Functions

Static Public Member Functions

Data Fields

Detailed Description

Constructor & Destructor Documentation

Member Function Documentation

Field Documentation