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expose.cc File Reference
#include "kernel/register.h"
#include "kernel/celltypes.h"
#include "kernel/sigtools.h"
#include "kernel/rtlil.h"
#include "kernel/log.h"
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Go to the source code of this file.

Data Structures

struct  dff_map_info_t
 
struct  dff_map_bit_info_t
 
struct  ExposePass
 

Functions

bool consider_wire (RTLIL::Wire *wire, std::map< RTLIL::IdString, dff_map_info_t > &dff_dq_map)
 
bool consider_cell (RTLIL::Design *design, std::set< RTLIL::IdString > &dff_cells, RTLIL::Cell *cell)
 
bool compare_wires (RTLIL::Wire *wire1, RTLIL::Wire *wire2)
 
bool compare_cells (RTLIL::Cell *cell1, RTLIL::Cell *cell2)
 
void find_dff_wires (std::set< RTLIL::IdString > &dff_wires, RTLIL::Module *module)
 
void create_dff_dq_map (std::map< RTLIL::IdString, dff_map_info_t > &map, RTLIL::Design *design, RTLIL::Module *module)
 
RTLIL::Wire * add_new_wire (RTLIL::Module *module, RTLIL::IdString name, int width=1)
 

Variables

ExposePass ExposePass
 

Function Documentation

RTLIL::Wire* add_new_wire ( RTLIL::Module *  module,
RTLIL::IdString  name,
int  width = 1 
)

Definition at line 214 of file expose.cc.

215 {
216  if (module->count_id(name))
217  log_error("Attempting to create wire %s, but a wire of this name exists already! Hint: Try another value for -sep.\n", log_id(name));
218  return module->addWire(name, width);
219 }
log_error
void log_error(const char *format,...)
Definition: log.cc:204
RTLIL::Module::addWire
RTLIL::Wire * addWire(RTLIL::IdString name, int width=1)
Definition: rtlil.cc:1331
RTLIL::Module::count_id
virtual size_t count_id(RTLIL::IdString id)
Definition: rtlil.cc:472
log_id
const char * log_id(RTLIL::IdString str)
Definition: log.cc:283

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bool compare_cells ( RTLIL::Cell *  cell1,
RTLIL::Cell *  cell2 
)

Definition at line 69 of file expose.cc.

70 {
71  log_assert(cell1->name == cell2->name);
72  if (cell1->type != cell2->type)
73  return false;
74  if (cell1->parameters != cell2->parameters)
75  return false;
76  return true;
77 }
RTLIL::Cell::name
RTLIL::IdString name
Definition: rtlil.h:853
RTLIL::Cell::type
RTLIL::IdString type
Definition: rtlil.h:854
RTLIL::Cell::parameters
std::map< RTLIL::IdString, RTLIL::Const > parameters
Definition: rtlil.h:856
log_assert
#define log_assert(_assert_expr_)
Definition: log.h:85

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bool compare_wires ( RTLIL::Wire *  wire1,
RTLIL::Wire *  wire2 
)

Definition at line 61 of file expose.cc.

62 {
63  log_assert(wire1->name == wire2->name);
64  if (wire1->width != wire2->width)
65  return false;
66  return true;
67 }
RTLIL::Wire::width
int width
Definition: rtlil.h:826
log_assert
#define log_assert(_assert_expr_)
Definition: log.h:85
RTLIL::Wire::name
RTLIL::IdString name
Definition: rtlil.h:825

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bool consider_cell ( RTLIL::Design *  design,
std::set< RTLIL::IdString > &  dff_cells,
RTLIL::Cell *  cell 
)

Definition at line 52 of file expose.cc.

53 {
54  if (cell->name[0] == '$' || dff_cells.count(cell->name))
55  return false;
56  if (cell->type[0] == '\\' && !design->modules_.count(cell->type))
57  return false;
58  return true;
59 }
RTLIL::Cell::name
RTLIL::IdString name
Definition: rtlil.h:853
RTLIL::Cell::type
RTLIL::IdString type
Definition: rtlil.h:854
RTLIL::Design::modules_
std::map< RTLIL::IdString, RTLIL::Module * > modules_
Definition: rtlil.h:507

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bool consider_wire ( RTLIL::Wire *  wire,
std::map< RTLIL::IdString, dff_map_info_t > &  dff_dq_map 
)

Definition at line 43 of file expose.cc.

44 {
45  if (wire->name[0] == '$' || dff_dq_map.count(wire->name))
46  return false;
47  if (wire->port_input)
48  return false;
49  return true;
50 }
RTLIL::Wire::port_input
bool port_input
Definition: rtlil.h:827
RTLIL::Wire::name
RTLIL::IdString name
Definition: rtlil.h:825

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void create_dff_dq_map ( std::map< RTLIL::IdString, dff_map_info_t > &  map,
RTLIL::Design *  design,
RTLIL::Module *  module 
)

Definition at line 99 of file expose.cc.

100 {
101  std::map<RTLIL::SigBit, dff_map_bit_info_t> bit_info;
102  SigMap sigmap(module);
103 
104  for (auto &it : module->cells_)
105  {
106  if (!design->selected(module, it.second))
107  continue;
108 
109  dff_map_bit_info_t info;
110  info.bit_d = RTLIL::State::Sm;
111  info.bit_clk = RTLIL::State::Sm;
112  info.bit_arst = RTLIL::State::Sm;
113  info.clk_polarity = false;
114  info.arst_polarity = false;
115  info.arst_value = RTLIL::State::Sm;
116  info.cell = it.second;
117 
118  if (info.cell->type == "$dff") {
119  info.bit_clk = sigmap(info.cell->getPort("\\CLK")).to_single_sigbit();
120  info.clk_polarity = info.cell->parameters.at("\\CLK_POLARITY").as_bool();
121  std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->getPort("\\D")).to_sigbit_vector();
122  std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->getPort("\\Q")).to_sigbit_vector();
123  for (size_t i = 0; i < sig_d.size(); i++) {
124  info.bit_d = sig_d.at(i);
125  bit_info[sig_q.at(i)] = info;
126  }
127  continue;
128  }
129 
130  if (info.cell->type == "$adff") {
131  info.bit_clk = sigmap(info.cell->getPort("\\CLK")).to_single_sigbit();
132  info.bit_arst = sigmap(info.cell->getPort("\\ARST")).to_single_sigbit();
133  info.clk_polarity = info.cell->parameters.at("\\CLK_POLARITY").as_bool();
134  info.arst_polarity = info.cell->parameters.at("\\ARST_POLARITY").as_bool();
135  std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->getPort("\\D")).to_sigbit_vector();
136  std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->getPort("\\Q")).to_sigbit_vector();
137  std::vector<RTLIL::State> arst_value = info.cell->parameters.at("\\ARST_VALUE").bits;
138  for (size_t i = 0; i < sig_d.size(); i++) {
139  info.bit_d = sig_d.at(i);
140  info.arst_value = arst_value.at(i);
141  bit_info[sig_q.at(i)] = info;
142  }
143  continue;
144  }
145 
146  if (info.cell->type == "$_DFF_N_" || info.cell->type == "$_DFF_P_") {
147  info.bit_clk = sigmap(info.cell->getPort("\\C")).to_single_sigbit();
148  info.clk_polarity = info.cell->type == "$_DFF_P_";
149  info.bit_d = sigmap(info.cell->getPort("\\D")).to_single_sigbit();
150  bit_info[sigmap(info.cell->getPort("\\Q")).to_single_sigbit()] = info;
151  continue;
152  }
153 
154  if (info.cell->type.size() == 10 && info.cell->type.substr(0, 6) == "$_DFF_") {
155  info.bit_clk = sigmap(info.cell->getPort("\\C")).to_single_sigbit();
156  info.bit_arst = sigmap(info.cell->getPort("\\R")).to_single_sigbit();
157  info.clk_polarity = info.cell->type[6] == 'P';
158  info.arst_polarity = info.cell->type[7] == 'P';
159  info.arst_value = info.cell->type[0] == '1' ? RTLIL::State::S1 : RTLIL::State::S0;
160  info.bit_d = sigmap(info.cell->getPort("\\D")).to_single_sigbit();
161  bit_info[sigmap(info.cell->getPort("\\Q")).to_single_sigbit()] = info;
162  continue;
163  }
164  }
165 
166  std::map<RTLIL::IdString, dff_map_info_t> empty_dq_map;
167  for (auto &it : module->wires_)
168  {
169  if (!consider_wire(it.second, empty_dq_map))
170  continue;
171 
172  std::vector<RTLIL::SigBit> bits_q = sigmap(it.second).to_sigbit_vector();
173  std::vector<RTLIL::SigBit> bits_d;
174  std::vector<RTLIL::State> arst_value;
175  std::set<RTLIL::Cell*> cells;
176 
177  if (bits_q.empty() || !bit_info.count(bits_q.front()))
178  continue;
179 
180  dff_map_bit_info_t ref_info = bit_info.at(bits_q.front());
181  for (auto &bit : bits_q) {
182  if (!bit_info.count(bit))
183  break;
184  dff_map_bit_info_t info = bit_info.at(bit);
185  if (info.bit_clk != ref_info.bit_clk)
186  break;
187  if (info.bit_arst != ref_info.bit_arst)
188  break;
189  if (info.clk_polarity != ref_info.clk_polarity)
190  break;
191  if (info.arst_polarity != ref_info.arst_polarity)
192  break;
193  bits_d.push_back(info.bit_d);
194  arst_value.push_back(info.arst_value);
195  cells.insert(info.cell);
196  }
197 
198  if (bits_d.size() != bits_q.size())
199  continue;
200 
201  dff_map_info_t info;
202  info.sig_d = bits_d;
203  info.sig_clk = ref_info.bit_clk;
204  info.sig_arst = ref_info.bit_arst;
205  info.clk_polarity = ref_info.clk_polarity;
206  info.arst_polarity = ref_info.arst_polarity;
207  info.arst_value = arst_value;
208  for (auto it : cells)
209  info.cells.push_back(it->name);
210  map[it.first] = info;
211  }
212 }
RTLIL::Design::selected
bool selected(T1 *module) const
Definition: rtlil.h:551
dff_map_bit_info_t::bit_clk
RTLIL::SigBit bit_clk
Definition: expose.cc:37
dff_map_info_t::sig_d
RTLIL::SigSpec sig_d
Definition: expose.cc:30
RTLIL::Module::wires_
std::map< RTLIL::IdString, RTLIL::Wire * > wires_
Definition: rtlil.h:595
dff_map_info_t::sig_clk
RTLIL::SigSpec sig_clk
Definition: expose.cc:30
dff_map_info_t::arst_polarity
bool arst_polarity
Definition: expose.cc:31
RTLIL::Cell::type
RTLIL::IdString type
Definition: rtlil.h:854
RTLIL::Cell::parameters
std::map< RTLIL::IdString, RTLIL::Const > parameters
Definition: rtlil.h:856
consider_wire
bool consider_wire(RTLIL::Wire *wire, std::map< RTLIL::IdString, dff_map_info_t > &dff_dq_map)
Definition: expose.cc:43
dff_map_bit_info_t::arst_polarity
bool arst_polarity
Definition: expose.cc:38
dff_map_bit_info_t::clk_polarity
bool clk_polarity
Definition: expose.cc:38
dff_map_bit_info_t::bit_d
RTLIL::SigBit bit_d
Definition: expose.cc:37
dff_map_bit_info_t::bit_arst
RTLIL::SigBit bit_arst
Definition: expose.cc:37
RTLIL::Cell::getPort
const RTLIL::SigSpec & getPort(RTLIL::IdString portname) const
Definition: rtlil.cc:1809
dff_map_info_t::arst_value
RTLIL::Const arst_value
Definition: expose.cc:32
dff_map_bit_info_t
Definition: expose.cc:36
dff_map_info_t::clk_polarity
bool clk_polarity
Definition: expose.cc:31
RTLIL::IdString::substr
std::string substr(size_t pos=0, size_t len=std::string::npos) const
Definition: rtlil.h:208
dff_map_bit_info_t::cell
RTLIL::Cell * cell
Definition: expose.cc:40
RTLIL::Module::cells_
std::map< RTLIL::IdString, RTLIL::Cell * > cells_
Definition: rtlil.h:596
dff_map_info_t::sig_arst
RTLIL::SigSpec sig_arst
Definition: expose.cc:30
dff_map_info_t::cells
std::vector< RTLIL::IdString > cells
Definition: expose.cc:33
dff_map_bit_info_t::arst_value
RTLIL::State arst_value
Definition: expose.cc:39
dff_map_info_t
Definition: expose.cc:29
RTLIL::IdString::size
size_t size() const
Definition: rtlil.h:215

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void find_dff_wires ( std::set< RTLIL::IdString > &  dff_wires,
RTLIL::Module *  module 
)

Definition at line 79 of file expose.cc.

80 {
81  CellTypes ct;
82  ct.setup_internals_mem();
83  ct.setup_stdcells_mem();
84 
85  SigMap sigmap(module);
86  SigPool dffsignals;
87 
88  for (auto &it : module->cells_) {
89  if (ct.cell_known(it.second->type) && it.second->hasPort("\\Q"))
90  dffsignals.add(sigmap(it.second->getPort("\\Q")));
91  }
92 
93  for (auto &it : module->wires_) {
94  if (dffsignals.check_any(it.second))
95  dff_wires.insert(it.first);
96  }
97 }
CellTypes::setup_internals_mem
void setup_internals_mem()
Definition: celltypes.h:115
ct
CellTypes ct
Definition: opt_clean.cc:33
RTLIL::Module::wires_
std::map< RTLIL::IdString, RTLIL::Wire * > wires_
Definition: rtlil.h:595
CellTypes::cell_known
bool cell_known(RTLIL::IdString type)
Definition: celltypes.h:188
SigPool::check_any
bool check_any(RTLIL::SigSpec sig)
Definition: sigtools.h:100
SigPool::add
void add(RTLIL::SigSpec sig)
Definition: sigtools.h:41
RTLIL::Module::cells_
std::map< RTLIL::IdString, RTLIL::Cell * > cells_
Definition: rtlil.h:596
CellTypes::setup_stdcells_mem
void setup_stdcells_mem()
Definition: celltypes.h:149

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Variable Documentation

ExposePass ExposePass