Inheritance diagram for ExtractPass:

Collaboration diagram for ExtractPass:

Public Member Functions
	ExtractPass ()

virtual void	help ()

virtual void	execute (std::vector< std::string > args, RTLIL::Design *design)

pre_post_exec_state_t	pre_execute ()

void	post_execute (pre_post_exec_state_t state)

void	cmd_log_args (const std::vector< std::string > &args)

void	cmd_error (const std::vector< std::string > &args, size_t argidx, std::string msg)

void	extra_args (std::vector< std::string > args, size_t argidx, RTLIL::Design *design, bool select=true)

virtual void	run_register ()

Static Public Member Functions
static void	call (RTLIL::Design *design, std::string command)

static void	call (RTLIL::Design *design, std::vector< std::string > args)

static void	call_on_selection (RTLIL::Design *design, const RTLIL::Selection &selection, std::string command)

static void	call_on_selection (RTLIL::Design *design, const RTLIL::Selection &selection, std::vector< std::string > args)

static void	call_on_module (RTLIL::Design design, RTLIL::Module module, std::string command)

static void	call_on_module (RTLIL::Design design, RTLIL::Module module, std::vector< std::string > args)

static void	init_register ()

static void	done_register ()

Data Fields
std::string	pass_name

std::string	short_help

int	call_counter

int64_t	runtime_ns

Pass *	next_queued_pass

Detailed Description

Definition at line 353 of file extract.cc.

Constructor & Destructor Documentation

ExtractPass::ExtractPass ( )

inline

Definition at line 354 of file extract.cc.

354 : Pass("extract", "find subcircuits and replace them with cells") { }

Pass::Pass

Pass(std::string name, std::string short_help="** document me **")

Definition: register.cc:40

Member Function Documentation

void Pass::call	(	RTLIL::Design *	design,
		std::string	command
	)

staticinherited

Definition at line 146 of file register.cc.

 {
     std::vector<std::string> args;
 
     std::string cmd_buf = command;
     std::string tok = next_token(cmd_buf, " \t\r\n");
 
     if (tok.empty() || tok[0] == '#')
         return;
 
     if (tok[0] == '!') {
         cmd_buf = command.substr(command.find('!') + 1);
         while (!cmd_buf.empty() && (cmd_buf.back() == ' ' || cmd_buf.back() == '\t' ||
                 cmd_buf.back() == '\r' || cmd_buf.back() == '\n'))
             cmd_buf.resize(cmd_buf.size()-1);
         log_header("Shell command: %s\n", cmd_buf.c_str());
         int retCode = run_command(cmd_buf);
         if (retCode != 0)
             log_cmd_error("Shell command returned error code %d.\n", retCode);
         return;
     }
 
     while (!tok.empty()) {
         if (tok == "#")
             break;
         if (tok.back() == ';') {
             int num_semikolon = 0;
             while (!tok.empty() && tok.back() == ';')
                 tok.resize(tok.size()-1), num_semikolon++;
             if (!tok.empty())
                 args.push_back(tok);
             call(design, args);
             args.clear();
             if (num_semikolon == 2)
                 call(design, "clean");
             if (num_semikolon == 3)
                 call(design, "clean -purge");
         } else
             args.push_back(tok);
         tok = next_token(cmd_buf, " \t\r\n");
     }
 
     call(design, args);
 }

Here is the call graph for this function:

Here is the caller graph for this function:

void Pass::call	(	RTLIL::Design *	design,
		std::vector< std::string >	args
	)

staticinherited

Definition at line 191 of file register.cc.

 {
     if (args.size() == 0 || args[0][0] == '#')
         return;
 
     if (echo_mode) {
         log("%s", create_prompt(design, 0));
         for (size_t i = 0; i < args.size(); i++)
             log("%s%s", i ? " " : "", args[i].c_str());
         log("\n");
     }
 
     if (pass_register.count(args[0]) == 0)
         log_cmd_error("No such command: %s (type 'help' for a command overview)\n", args[0].c_str());
 
     size_t orig_sel_stack_pos = design->selection_stack.size();
     auto state = pass_register[args[0]]->pre_execute();
     pass_register[args[0]]->execute(args, design);
     pass_register[args[0]]->post_execute(state);
     while (design->selection_stack.size() > orig_sel_stack_pos)
         design->selection_stack.pop_back();
 
     design->check();
 }

Here is the call graph for this function:

void Pass::call_on_module	(	RTLIL::Design *	design,
		RTLIL::Module *	module,
		std::string	command
	)

staticinherited

Definition at line 240 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module = module->name.str();
     design->selection_stack.push_back(RTLIL::Selection(false));
     design->selection_stack.back().select(module);
 
     Pass::call(design, command);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

Here is the call graph for this function:

Here is the caller graph for this function:

void Pass::call_on_module	(	RTLIL::Design *	design,
		RTLIL::Module *	module,
		std::vector< std::string >	args
	)

staticinherited

Definition at line 253 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module = module->name.str();
     design->selection_stack.push_back(RTLIL::Selection(false));
     design->selection_stack.back().select(module);
 
     Pass::call(design, args);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

Here is the call graph for this function:

void Pass::call_on_selection	(	RTLIL::Design *	design,
		const RTLIL::Selection &	selection,
		std::string	command
	)

staticinherited

Definition at line 216 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module.clear();
     design->selection_stack.push_back(selection);
 
     Pass::call(design, command);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

Here is the call graph for this function:

void Pass::call_on_selection	(	RTLIL::Design *	design,
		const RTLIL::Selection &	selection,
		std::vector< std::string >	args
	)

staticinherited

Definition at line 228 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module.clear();
     design->selection_stack.push_back(selection);
 
     Pass::call(design, args);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

Here is the call graph for this function:

void Pass::cmd_error	(	const std::vector< std::string > &	args,
		size_t	argidx,
		std::string	msg
	)

inherited

Definition at line 110 of file register.cc.

 {
     std::string command_text;
     int error_pos = 0;
 
     for (size_t i = 0; i < args.size(); i++) {
         if (i < argidx)
             error_pos += args[i].size() + 1;
         command_text = command_text + (command_text.empty() ? "" : " ") + args[i];
     }
 
     log("\nSyntax error in command `%s':\n", command_text.c_str());
     help();
 
     log_cmd_error("Command syntax error: %s\n> %s\n> %*s^\n",
             msg.c_str(), command_text.c_str(), error_pos, "");
 }

Here is the call graph for this function:

Here is the caller graph for this function:

void Pass::cmd_log_args ( const std::vector< std::string > & args )

inherited

Definition at line 100 of file register.cc.

 {
     if (args.size() <= 1)
         return;
     log("Full command line:");
     for (size_t i = 0; i < args.size(); i++)
         log(" %s", args[i].c_str());
     log("\n");
 }

Here is the call graph for this function:

void Pass::done_register ( )

staticinherited

Definition at line 62 of file register.cc.

 {
     frontend_register.clear();
     pass_register.clear();
     backend_register.clear();
     log_assert(first_queued_pass == NULL);
 }

Here is the caller graph for this function:

virtual void ExtractPass::execute	(	std::vector< std::string >	args,
		RTLIL::Design *	design
	)

inlinevirtual

Implements Pass.

Definition at line 443 of file extract.cc.

     {
         log_header("Executing EXTRACT pass (map subcircuits to cells).\n");
         log_push();
 
         SubCircuitSolver solver;
 
         std::vector<std::string> map_filenames;
         std::string mine_outfile;
         bool constports = false;
         bool nodefaultswaps = false;
 
         bool mine_mode = false;
         int mine_cells_min = 3;
         int mine_cells_max = 5;
         int mine_min_freq = 10;
         int mine_limit_mod = -1;
         int mine_max_fanout = -1;
         std::set<std::pair<RTLIL::IdString, RTLIL::IdString>> mine_split;
 
         size_t argidx;
         for (argidx = 1; argidx < args.size(); argidx++) {
             if (args[argidx] == "-map" && argidx+1 < args.size()) {
                 if (mine_mode)
                     log_cmd_error("You cannot mix -map and -mine.\n");
                 map_filenames.push_back(args[++argidx]);
                 continue;
             }
             if (args[argidx] == "-mine" && argidx+1 < args.size()) {
                 if (!map_filenames.empty())
                     log_cmd_error("You cannot mix -map and -mine.\n");
                 mine_outfile = args[++argidx];
                 mine_mode = true;
                 continue;
             }
             if (args[argidx] == "-mine_cells_span" && argidx+2 < args.size()) {
                 mine_cells_min = atoi(args[++argidx].c_str());
                 mine_cells_max = atoi(args[++argidx].c_str());
                 continue;
             }
             if (args[argidx] == "-mine_min_freq" && argidx+1 < args.size()) {
                 mine_min_freq = atoi(args[++argidx].c_str());
                 continue;
             }
             if (args[argidx] == "-mine_limit_matches_per_module" && argidx+1 < args.size()) {
                 mine_limit_mod = atoi(args[++argidx].c_str());
                 continue;
             }
             if (args[argidx] == "-mine_split" && argidx+2 < args.size()) {
                 mine_split.insert(std::pair<RTLIL::IdString, RTLIL::IdString>(RTLIL::escape_id(args[argidx+1]), RTLIL::escape_id(args[argidx+2])));
                 argidx += 2;
                 continue;
             }
             if (args[argidx] == "-mine_max_fanout" && argidx+1 < args.size()) {
                 mine_max_fanout = atoi(args[++argidx].c_str());
                 continue;
             }
             if (args[argidx] == "-verbose") {
                 solver.setVerbose();
                 continue;
             }
             if (args[argidx] == "-constports") {
                 constports = true;
                 continue;
             }
             if (args[argidx] == "-nodefaultswaps") {
                 nodefaultswaps = true;
                 continue;
             }
             if (args[argidx] == "-compat" && argidx+2 < args.size()) {
                 std::string needle_type = RTLIL::escape_id(args[++argidx]);
                 std::string haystack_type = RTLIL::escape_id(args[++argidx]);
                 solver.addCompatibleTypes(needle_type, haystack_type);
                 continue;
             }
             if (args[argidx] == "-swap" && argidx+2 < args.size()) {
                 std::string type = RTLIL::escape_id(args[++argidx]);
                 std::set<std::string> ports;
                 std::string ports_str = args[++argidx], p;
                 while (!(p = next_token(ports_str, ",\t\r\n ")).empty())
                     ports.insert(RTLIL::escape_id(p));
                 solver.addSwappablePorts(type, ports);
                 continue;
             }
             if (args[argidx] == "-perm" && argidx+3 < args.size()) {
                 std::string type = RTLIL::escape_id(args[++argidx]);
                 std::vector<std::string> map_left, map_right;
                 std::string left_str = args[++argidx];
                 std::string right_str = args[++argidx], p;
                 while (!(p = next_token(left_str, ",\t\r\n ")).empty())
                     map_left.push_back(RTLIL::escape_id(p));
                 while (!(p = next_token(right_str, ",\t\r\n ")).empty())
                     map_right.push_back(RTLIL::escape_id(p));
                 if (map_left.size() != map_right.size())
                     log_cmd_error("Arguments to -perm are not a valid permutation!\n");
                 std::map<std::string, std::string> map;
                 for (size_t i = 0; i < map_left.size(); i++)
                     map[map_left[i]] = map_right[i];
                 std::sort(map_left.begin(), map_left.end());
                 std::sort(map_right.begin(), map_right.end());
                 if (map_left != map_right)
                     log_cmd_error("Arguments to -perm are not a valid permutation!\n");
                 solver.addSwappablePortsPermutation(type, map);
                 continue;
             }
             if (args[argidx] == "-cell_attr" && argidx+1 < args.size()) {
                 solver.cell_attr.insert(RTLIL::escape_id(args[++argidx]));
                 continue;
             }
             if (args[argidx] == "-wire_attr" && argidx+1 < args.size()) {
                 solver.wire_attr.insert(RTLIL::escape_id(args[++argidx]));
                 continue;
             }
             if (args[argidx] == "-ignore_parameters") {
                 solver.ignore_parameters = true;
                 continue;
             }
             if (args[argidx] == "-ignore_param" && argidx+2 < args.size()) {
                 solver.ignored_parameters.insert(std::pair<RTLIL::IdString, RTLIL::IdString>(RTLIL::escape_id(args[argidx+1]), RTLIL::escape_id(args[argidx+2])));
                 argidx += 2;
                 continue;
             }
             break;
         }
         extra_args(args, argidx, design);
 
         if (!nodefaultswaps) {
             solver.addSwappablePorts("$and",       "\\A", "\\B");
             solver.addSwappablePorts("$or",        "\\A", "\\B");
             solver.addSwappablePorts("$xor",       "\\A", "\\B");
             solver.addSwappablePorts("$xnor",      "\\A", "\\B");
             solver.addSwappablePorts("$eq",        "\\A", "\\B");
             solver.addSwappablePorts("$ne",        "\\A", "\\B");
             solver.addSwappablePorts("$eqx",       "\\A", "\\B");
             solver.addSwappablePorts("$nex",       "\\A", "\\B");
             solver.addSwappablePorts("$add",       "\\A", "\\B");
             solver.addSwappablePorts("$mul",       "\\A", "\\B");
             solver.addSwappablePorts("$logic_and", "\\A", "\\B");
             solver.addSwappablePorts("$logic_or",  "\\A", "\\B");
             solver.addSwappablePorts("$_AND_",     "\\A", "\\B");
             solver.addSwappablePorts("$_OR_",      "\\A", "\\B");
             solver.addSwappablePorts("$_XOR_",     "\\A", "\\B");
         }
 
         if (map_filenames.empty() && mine_outfile.empty())
             log_cmd_error("Missing option -map <verilog_or_ilang_file> or -mine <output_ilang_file>.\n");
 
         RTLIL::Design *map = NULL;
 
         if (!mine_mode)
         {
             map = new RTLIL::Design;
             for (auto &filename : map_filenames)
             {
                 if (filename.substr(0, 1) == "%")
                 {
                     if (!saved_designs.count(filename.substr(1))) {
                         delete map;
                         log_cmd_error("Can't saved design `%s'.\n", filename.c_str()+1);
                     }
                     for (auto mod : saved_designs.at(filename.substr(1))->modules())
                         if (!map->has(mod->name))
                             map->add(mod->clone());
                 }
                 else
                 {
                     std::ifstream f;
                     f.open(filename.c_str());
                     if (f.fail()) {
                         delete map;
                         log_cmd_error("Can't open map file `%s'.\n", filename.c_str());
                     }
                     Frontend::frontend_call(map, &f, filename, (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") ? "ilang" : "verilog");
                     f.close();
 
                     if (filename.size() <= 3 || filename.substr(filename.size()-3) != ".il") {
                         Pass::call(map, "proc");
                         Pass::call(map, "opt_clean");
                     }
                 }
             }
         }
 
         std::map<std::string, RTLIL::Module*> needle_map, haystack_map;
         std::vector<RTLIL::Module*> needle_list;
 
         log_header("Creating graphs for SubCircuit library.\n");
 
         if (!mine_mode)
             for (auto &mod_it : map->modules_) {
                 SubCircuit::Graph mod_graph;
                 std::string graph_name = "needle_" + RTLIL::unescape_id(mod_it.first);
                 log("Creating needle graph %s.\n", graph_name.c_str());
                 if (module2graph(mod_graph, mod_it.second, constports)) {
                     solver.addGraph(graph_name, mod_graph);
                     needle_map[graph_name] = mod_it.second;
                     needle_list.push_back(mod_it.second);
                 }
             }
 
         for (auto &mod_it : design->modules_) {
             SubCircuit::Graph mod_graph;
             std::string graph_name = "haystack_" + RTLIL::unescape_id(mod_it.first);
             log("Creating haystack graph %s.\n", graph_name.c_str());
             if (module2graph(mod_graph, mod_it.second, constports, design, mine_mode ? mine_max_fanout : -1, mine_mode ? &mine_split : NULL)) {
                 solver.addGraph(graph_name, mod_graph);
                 haystack_map[graph_name] = mod_it.second;
             }
         }
         
         if (!mine_mode)
         {
             std::vector<SubCircuit::Solver::Result> results;
             log_header("Running solver from SubCircuit library.\n");
 
             std::sort(needle_list.begin(), needle_list.end(), compareSortNeedleList);
 
             for (auto needle : needle_list)
             for (auto &haystack_it : haystack_map) {
                 log("Solving for %s in %s.\n", ("needle_" + RTLIL::unescape_id(needle->name)).c_str(), haystack_it.first.c_str());
                 solver.solve(results, "needle_" + RTLIL::unescape_id(needle->name), haystack_it.first, false);
             }
             log("Found %d matches.\n", GetSize(results));
 
             if (results.size() > 0)
             {
                 log_header("Substitute SubCircuits with cells.\n");
 
                 for (int i = 0; i < int(results.size()); i++) {
                     auto &result = results[i];
                     log("\nMatch #%d: (%s in %s)\n", i, result.needleGraphId.c_str(), result.haystackGraphId.c_str());
                     for (const auto &it : result.mappings) {
                         log("  %s -> %s", it.first.c_str(), it.second.haystackNodeId.c_str());
                         for (const auto & it2 : it.second.portMapping)
                             log(" %s:%s", it2.first.c_str(), it2.second.c_str());
                         log("\n");
                     }
                     RTLIL::Cell *new_cell = replace(needle_map.at(result.needleGraphId), haystack_map.at(result.haystackGraphId), result);
                     design->select(haystack_map.at(result.haystackGraphId), new_cell);
                     log("  new cell: %s\n", id2cstr(new_cell->name));
                 }
             }
         }
         else
         {
             std::vector<SubCircuit::Solver::MineResult> results;
 
             log_header("Running miner from SubCircuit library.\n");
             solver.mine(results, mine_cells_min, mine_cells_max, mine_min_freq, mine_limit_mod);
 
             map = new RTLIL::Design;
 
             int needleCounter = 0;
             for (auto &result: results)
             {
                 log("\nFrequent SubCircuit with %d nodes and %d matches:\n", int(result.nodes.size()), result.totalMatchesAfterLimits);
                 log("  primary match in %s:", id2cstr(haystack_map.at(result.graphId)->name));
                 for (auto &node : result.nodes)
                     log(" %s", RTLIL::unescape_id(node.nodeId).c_str());
                 log("\n");
                 for (auto &it : result.matchesPerGraph)
                     log("  matches in %s: %d\n", id2cstr(haystack_map.at(it.first)->name), it.second);
 
                 RTLIL::Module *mod = haystack_map.at(result.graphId);
                 std::set<RTLIL::Cell*> cells;
                 std::set<RTLIL::Wire*> wires;
 
                 SigMap sigmap(mod);
 
                 for (auto &node : result.nodes)
                     cells.insert((RTLIL::Cell*)node.userData);
 
                 for (auto cell : cells)
                 for (auto &conn : cell->connections()) {
                     RTLIL::SigSpec sig = sigmap(conn.second);
                     for (auto &chunk : sig.chunks())
                         if (chunk.wire != NULL)
                             wires.insert(chunk.wire);
                 }
 
                 RTLIL::Module *newMod = new RTLIL::Module;
                 newMod->name = stringf("\\needle%05d_%s_%dx", needleCounter++, id2cstr(haystack_map.at(result.graphId)->name), result.totalMatchesAfterLimits);
                 map->add(newMod);
 
                 for (auto wire : wires) {
                     RTLIL::Wire *newWire = newMod->addWire(wire->name, wire->width);
                     newWire->port_input = true;
                     newWire->port_output = true;
                 }
 
                 newMod->fixup_ports();
 
                 for (auto cell : cells) {
                     RTLIL::Cell *newCell = newMod->addCell(cell->name, cell->type);
                     newCell->parameters = cell->parameters;
                     for (auto &conn : cell->connections()) {
                         std::vector<RTLIL::SigChunk> chunks = sigmap(conn.second);
                         for (auto &chunk : chunks)
                             if (chunk.wire != NULL)
                                 chunk.wire = newMod->wires_.at(chunk.wire->name);
                         newCell->setPort(conn.first, chunks);
                     }
                 }
             }
 
             std::ofstream f;
             f.open(mine_outfile.c_str(), std::ofstream::trunc);
             if (f.fail())
                 log_error("Can't open output file `%s'.\n", mine_outfile.c_str());
             Backend::backend_call(map, &f, mine_outfile, "ilang");
             f.close();
         }
 
         delete map;
         log_pop();
     }

Here is the call graph for this function:

void Pass::extra_args	(	std::vector< std::string >	args,
		size_t	argidx,
		RTLIL::Design *	design,
		bool	select = `true`
	)

inherited

Definition at line 128 of file register.cc.

 {
     for (; argidx < args.size(); argidx++)
     {
         std::string arg = args[argidx];
 
         if (arg.substr(0, 1) == "-")
             cmd_error(args, argidx, "Unknown option or option in arguments.");
 
         if (!select)
             cmd_error(args, argidx, "Extra argument.");
 
         handle_extra_select_args(this, args, argidx, args.size(), design);
         break;
     }
     // cmd_log_args(args);
 }

Here is the call graph for this function:

virtual void ExtractPass::help ( )

inlinevirtual

Reimplemented from Pass.

Definition at line 355 of file extract.cc.

     {
         //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
         log("\n");
         log("    extract -map <map_file> [options] [selection]\n");
         log("    extract -mine <out_file> [options] [selection]\n");
         log("\n");
         log("This pass looks for subcircuits that are isomorphic to any of the modules\n");
         log("in the given map file and replaces them with instances of this modules. The\n");
         log("map file can be a verilog source file (*.v) or an ilang file (*.il).\n");
         log("\n");
         log("    -map <map_file>\n");
         log("        use the modules in this file as reference. This option can be used\n");
         log("        multiple times.\n");
         log("\n");
         log("    -map %%<design-name>\n");
         log("        use the modules in this in-memory design as reference. This option can\n");
         log("        be used multiple times.\n");
         log("\n");
         log("    -verbose\n");
         log("        print debug output while analyzing\n");
         log("\n");
         log("    -constports\n");
         log("        also find instances with constant drivers. this may be much\n");
         log("        slower than the normal operation.\n");
         log("\n");
         log("    -nodefaultswaps\n");
         log("        normally builtin port swapping rules for internal cells are used per\n");
         log("        default. This turns that off, so e.g. 'a^b' does not match 'b^a'\n");
         log("        when this option is used.\n");
         log("\n");
         log("    -compat <needle_type> <haystack_type>\n");
         log("        Per default, the cells in the map file (needle) must have the\n");
         log("        type as the cells in the active design (haystack). This option\n");
         log("        can be used to register additional pairs of types that should\n");
         log("        match. This option can be used multiple times.\n");
         log("\n");
         log("    -swap <needle_type> <port1>,<port2>[,...]\n");
         log("        Register a set of swapable ports for a needle cell type.\n");
         log("        This option can be used multiple times.\n");
         log("\n");
         log("    -perm <needle_type> <port1>,<port2>[,...] <portA>,<portB>[,...]\n");
         log("        Register a valid permutation of swapable ports for a needle\n");
         log("        cell type. This option can be used multiple times.\n");
         log("\n");
         log("    -cell_attr <attribute_name>\n");
         log("        Attributes on cells with the given name must match.\n");
         log("\n");
         log("    -wire_attr <attribute_name>\n");
         log("        Attributes on wires with the given name must match.\n");
         log("\n");
         log("    -ignore_parameters\n");
         log("        Do not use parameters when matching cells.\n");
         log("\n");
         log("    -ignore_param <cell_type> <parameter_name>\n");
         log("        Do not use this parameter when matching cells.\n");
         log("\n");
         log("This pass does not operate on modules with uprocessed processes in it.\n");
         log("(I.e. the 'proc' pass should be used first to convert processes to netlists.)\n");
         log("\n");
         log("This pass can also be used for mining for frequent subcircuits. In this mode\n");
         log("the following options are to be used instead of the -map option.\n");
         log("\n");
         log("    -mine <out_file>\n");
         log("        mine for frequent subcircuits and write them to the given ilang file\n");
         log("\n");
         log("    -mine_cells_span <min> <max>\n");
         log("        only mine for subcircuits with the specified number of cells\n");
         log("        default value: 3 5\n");
         log("\n");
         log("    -mine_min_freq <num>\n");
         log("        only mine for subcircuits with at least the specified number of matches\n");
         log("        default value: 10\n");
         log("\n");
         log("    -mine_limit_matches_per_module <num>\n");
         log("        when calculating the number of matches for a subcircuit, don't count\n");
         log("        more than the specified number of matches per module\n");
         log("\n");
         log("    -mine_max_fanout <num>\n");
         log("        don't consider internal signals with more than <num> connections\n");
         log("\n");
         log("The modules in the map file may have the attribute 'extract_order' set to an\n");
         log("integer value. Then this value is used to determine the order in which the pass\n");
         log("tries to map the modules to the design (ascending, default value is 0).\n");
         log("\n");
         log("See 'help techmap' for a pass that does the opposite thing.\n");
         log("\n");
     }

Here is the call graph for this function:

void Pass::init_register ( )

staticinherited

Definition at line 54 of file register.cc.

 {
     while (first_queued_pass) {
         first_queued_pass->run_register();
         first_queued_pass = first_queued_pass->next_queued_pass;
     }
 }

Here is the call graph for this function:

Here is the caller graph for this function:

void Pass::post_execute ( Pass::pre_post_exec_state_t state )

inherited

Definition at line 84 of file register.cc.

 {
     int64_t time_ns = PerformanceTimer::query() - state.begin_ns;
     runtime_ns += time_ns;
     current_pass = state.parent_pass;
     if (current_pass)
         current_pass->runtime_ns -= time_ns;
 }

Here is the call graph for this function:

Here is the caller graph for this function:

Pass::pre_post_exec_state_t Pass::pre_execute ( )

inherited

Definition at line 74 of file register.cc.

 {
     pre_post_exec_state_t state;
     call_counter++;
     state.begin_ns = PerformanceTimer::query();
     state.parent_pass = current_pass;
     current_pass = this;
     return state;
 }

Here is the call graph for this function:

Here is the caller graph for this function:

void Pass::run_register ( )

virtualinherited

Reimplemented in Backend, and Frontend.

Definition at line 48 of file register.cc.

 {
     log_assert(pass_register.count(pass_name) == 0);
     pass_register[pass_name] = this;
 }

Here is the caller graph for this function:

Field Documentation

int Pass::call_counter

inherited

Definition at line 36 of file register.h.

Pass* Pass::next_queued_pass

inherited

Definition at line 60 of file register.h.

std::string Pass::pass_name

inherited

Definition at line 29 of file register.h.

int64_t Pass::runtime_ns

inherited

Definition at line 37 of file register.h.

std::string Pass::short_help

inherited

Definition at line 29 of file register.h.

The documentation for this struct was generated from the following file:

extract.cc

Public Member Functions

Static Public Member Functions

Data Fields

Detailed Description

Constructor & Destructor Documentation

Member Function Documentation

Field Documentation