extract.cc File Reference

#include "kernel/register.h"
#include "kernel/sigtools.h"
#include "kernel/log.h"
#include "libs/subcircuit/subcircuit.h"
#include <algorithm>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>

Include dependency graph for extract.cc:

Go to the source code of this file.

Data Structures
class	SubCircuitSolver
struct	bit_ref_t
struct	ExtractPass

Macros
#define	param_bool(_n)   if (param == _n) return value.as_bool();
#define	param_int(_n)   if (param == _n) return value.as_int();

Functions
bool	module2graph (SubCircuit::Graph &graph, RTLIL::Module *mod, bool constports, RTLIL::Design *sel=NULL, int max_fanout=-1, std::set< std::pair< RTLIL::IdString, RTLIL::IdString >> *split=NULL)
RTLIL::Cell *	replace (RTLIL::Module *needle, RTLIL::Module *haystack, SubCircuit::Solver::Result &match)
bool	compareSortNeedleList (RTLIL::Module *left, RTLIL::Module *right)

Variables
ExtractPass	ExtractPass

Macro Definition Documentation

#define param_bool

(

_n

)

if (param == _n) return value.as_bool();

#define param_int

(

_n

)

if (param == _n) return value.as_int();

Function Documentation

bool compareSortNeedleList	(	RTLIL::Module *	left,
		RTLIL::Module *	right
	)

Definition at line 341 of file extract.cc.

{
    int left_idx = 0, right_idx = 0;
    if (left->attributes.count("\\extract_order") > 0)
        left_idx = left->attributes.at("\\extract_order").as_int();
    if (right->attributes.count("\\extract_order") > 0)
        right_idx = right->attributes.at("\\extract_order").as_int();
    if (left_idx != right_idx)
        return left_idx < right_idx;
    return left->name < right->name;
}

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bool module2graph	(	SubCircuit::Graph &	graph,
		RTLIL::Module *	mod,
		bool	constports,
		RTLIL::Design *	sel = NULL,
		int	max_fanout = -1,
		std::set< std::pair< RTLIL::IdString, RTLIL::IdString >> *	split = NULL
	)

Definition at line 152 of file extract.cc.

{
    SigMap sigmap(mod);
    std::map<RTLIL::SigBit, bit_ref_t> sig_bit_ref;

    if (sel && !sel->selected(mod)) {
        log("  Skipping module %s as it is not selected.\n", id2cstr(mod->name));
        return false;
    }

    if (mod->processes.size() > 0) {
        log("  Skipping module %s as it contains unprocessed processes.\n", id2cstr(mod->name));
        return false;
    }

    if (constports) {
        graph.createNode("$const$0", "$const$0", NULL, true);
        graph.createNode("$const$1", "$const$1", NULL, true);
        graph.createNode("$const$x", "$const$x", NULL, true);
        graph.createNode("$const$z", "$const$z", NULL, true);
        graph.createPort("$const$0", "\\Y", 1);
        graph.createPort("$const$1", "\\Y", 1);
        graph.createPort("$const$x", "\\Y", 1);
        graph.createPort("$const$z", "\\Y", 1);
        graph.markExtern("$const$0", "\\Y", 0);
        graph.markExtern("$const$1", "\\Y", 0);
        graph.markExtern("$const$x", "\\Y", 0);
        graph.markExtern("$const$z", "\\Y", 0);
    }

    std::map<std::pair<RTLIL::Wire*, int>, int> sig_use_count;
    if (max_fanout > 0)
        for (auto &cell_it : mod->cells_)
        {
            RTLIL::Cell *cell = cell_it.second;
            if (!sel || sel->selected(mod, cell))
                for (auto &conn : cell->connections()) {
                    RTLIL::SigSpec conn_sig = conn.second;
                    sigmap.apply(conn_sig);
                    for (auto &bit : conn_sig)
                        if (bit.wire != NULL)
                            sig_use_count[std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset)]++;
                }
        }

    // create graph nodes from cells
    for (auto &cell_it : mod->cells_)
    {
        RTLIL::Cell *cell = cell_it.second;
        if (sel && !sel->selected(mod, cell))
            continue;

        std::string type = cell->type.str();
        if (sel == NULL && type.substr(0, 2) == "\\$")
            type = type.substr(1);
        graph.createNode(cell->name.str(), type, (void*)cell);

        for (auto &conn : cell->connections())
        {
            graph.createPort(cell->name.str(), conn.first.str(), conn.second.size());

            if (split && split->count(std::pair<RTLIL::IdString, RTLIL::IdString>(cell->type, conn.first)) > 0)
                continue;

            RTLIL::SigSpec conn_sig = conn.second;
            sigmap.apply(conn_sig);

            for (int i = 0; i < conn_sig.size(); i++)
            {
                auto &bit = conn_sig[i];

                if (bit.wire == NULL) {
                    if (constports) {
                        std::string node = "$const$x";
                        if (bit == RTLIL::State::S0) node = "$const$0";
                        if (bit == RTLIL::State::S1) node = "$const$1";
                        if (bit == RTLIL::State::Sz) node = "$const$z";
                        graph.createConnection(cell->name.str(), conn.first.str(), i, node, "\\Y", 0);
                    } else
                        graph.createConstant(cell->name.str(), conn.first.str(), i, int(bit.data));
                    continue;
                }

                if (max_fanout > 0 && sig_use_count[std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset)] > max_fanout)
                    continue;

                if (sel && !sel->selected(mod, bit.wire))
                    continue;

                if (sig_bit_ref.count(bit) == 0) {
                    bit_ref_t &bit_ref = sig_bit_ref[bit];
                    bit_ref.cell = cell->name.str();
                    bit_ref.port = conn.first.str();
                    bit_ref.bit = i;
                }

                bit_ref_t &bit_ref = sig_bit_ref[bit];
                graph.createConnection(bit_ref.cell, bit_ref.port, bit_ref.bit, cell->name.str(), conn.first.str(), i);
            }
        }
    }

    // mark external signals (used in non-selected cells)
    for (auto &cell_it : mod->cells_)
    {
        RTLIL::Cell *cell = cell_it.second;
        if (sel && !sel->selected(mod, cell))
            for (auto &conn : cell->connections())
            {
                RTLIL::SigSpec conn_sig = conn.second;
                sigmap.apply(conn_sig);

                for (auto &bit : conn_sig)
                    if (sig_bit_ref.count(bit) != 0) {
                        bit_ref_t &bit_ref = sig_bit_ref[bit];
                        graph.markExtern(bit_ref.cell, bit_ref.port, bit_ref.bit);
                    }
            }
    }

    // mark external signals (used in module ports)
    for (auto &wire_it : mod->wires_)
    {
        RTLIL::Wire *wire = wire_it.second;
        if (wire->port_id > 0)
        {
            RTLIL::SigSpec conn_sig(wire);
            sigmap.apply(conn_sig);

            for (auto &bit : conn_sig)
                if (sig_bit_ref.count(bit) != 0) {
                    bit_ref_t &bit_ref = sig_bit_ref[bit];
                    graph.markExtern(bit_ref.cell, bit_ref.port, bit_ref.bit);
                }
        }
    }

    // graph.print();
    return true;
}

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RTLIL::Cell* replace	(	RTLIL::Module *	needle,
		RTLIL::Module *	haystack,
		SubCircuit::Solver::Result &	match
	)

Definition at line 294 of file extract.cc.

{
    SigMap sigmap(needle);
    SigSet<std::pair<RTLIL::IdString, int>> sig2port;

    // create new cell
    RTLIL::Cell *cell = haystack->addCell(stringf("$extract$%s$%d", needle->name.c_str(), autoidx++), needle->name);

    // create cell ports
    for (auto &it : needle->wires_) {
        RTLIL::Wire *wire = it.second;
        if (wire->port_id > 0) {
            for (int i = 0; i < wire->width; i++)
                sig2port.insert(sigmap(RTLIL::SigSpec(wire, i)), std::pair<RTLIL::IdString, int>(wire->name, i));
            cell->setPort(wire->name, RTLIL::SigSpec(RTLIL::State::Sz, wire->width));
        }
    }

    // delete replaced cells and connect new ports
    for (auto &it : match.mappings)
    {
        auto &mapping = it.second;
        RTLIL::Cell *needle_cell = (RTLIL::Cell*)mapping.needleUserData;
        RTLIL::Cell *haystack_cell = (RTLIL::Cell*)mapping.haystackUserData;

        if (needle_cell == NULL)
            continue;

        for (auto &conn : needle_cell->connections()) {
            RTLIL::SigSpec sig = sigmap(conn.second);
            if (mapping.portMapping.count(conn.first.str()) > 0 && sig2port.has(sigmap(sig))) {
                for (int i = 0; i < sig.size(); i++)
                for (auto &port : sig2port.find(sig[i])) {
                    RTLIL::SigSpec bitsig = haystack_cell->getPort(mapping.portMapping[conn.first.str()]).extract(i, 1);
                    RTLIL::SigSpec new_sig = cell->getPort(port.first);
                    new_sig.replace(port.second, bitsig);
                    cell->setPort(port.first, new_sig);
                }
            }
        }

        haystack->remove(haystack_cell);
    }

    return cell;
}

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Variable Documentation

ExtractPass ExtractPass