torc-master
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Friends Macros Pages
Virtex7.cpp
Go to the documentation of this file.
1 // Torc - Copyright 2011-2013 University of Southern California. All Rights Reserved.
2 // $HeadURL$
3 // $Id$
4 
5 // This program is free software: you can redistribute it and/or modify it under the terms of the
6 // GNU General Public License as published by the Free Software Foundation, either version 3 of the
7 // License, or (at your option) any later version.
8 //
9 // This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
10 // without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
11 // the GNU General Public License for more details.
12 //
13 // You should have received a copy of the GNU General Public License along with this program. If
14 // not, see <http://www.gnu.org/licenses/>.
15 
16 #include "torc/bitstream/Virtex7.hpp"
17 #include <iostream>
18 
19 /// \todo Warning: this will need to be moved elsewhere.
20 #include "torc/architecture/DDB.hpp"
21 #include "torc/architecture/XilinxDatabaseTypes.hpp"
22 #include "torc/common/DirectoryTree.hpp"
23 #include <fstream>
24 #include <iomanip>
25 
26 namespace torc {
27 namespace bitstream{
28 
29  const char* Virtex7::sPacketTypeName[ePacketTypeCount] = {
30  "[UNKNOWN TYPE 0]", "TYPE1", "TYPE2", "[UNKNOWN TYPE 3]", "[UNKNOWN TYPE 4]",
31  "[UNKNOWN TYPE 5]", "[UNKNOWN TYPE 6]", "[UNKNOWN TYPE 7]"
32  };
33 
34  const char* Virtex7::sOpcodeName[eOpcodeCount] = {
35  "NOP", "READ", "WRITE", "RESERVED"
36  };
37 
38  const char* Virtex7::sRegisterName[eRegisterCount] = {
39  "CRC", "FAR", "FDRI", "FDRO", "CMD", "CTL0", "MASK", "STAT", "LOUT", "COR0",
40  "MFWR", "CBC", "IDCODE", "AXSS", "COR1", "[UNKNOWN REG 15]","WBSTAR", "TIMER",
41  "[UNKNOWN REG 18]","[UNKNOWN REG 19]", "[UNKNOWN REG 20]", "[UNKNOWN REG 21]",
42  "BOOTSTS", "[UNKNOWN REG 23]", "CTL1"
43  };
44 
45  const char* Virtex7::sCommandName[eCommandCount] = {
46  "NULL", "WCFG", "MFW", "DGHIGH/LFRM", "RCFG", "START", "RCAP", "RCRC",
47  "AGHIGH", "SWITCH", "GRESTORE", "SHUTDOWN", "GCAPTURE", "DESYNCH", "Reserved",
48  "IPROG", "CRCC", "LTIMER"
49  };
50 
51 #define VALUES (const char*[])
52 
53  ///\see Control Register 0 (CTL0): UG470, v1.1, March 28, 2011, Table 5-23
54  const Bitstream::Subfield Virtex7::sCTL0[] = {
55  {0x00000001, 0, "GTS_USER_B", "GTS_USER_B", 0,
56  // bitgen: n/a
57  // config: 0:"I/Os 3 stated, 1:"I/Os active"
58  VALUES{"IoDisabled", "IoActive", 0}},
59  {0x00000008, 3, "Persist", "PERSIST", 0,
60  // bitgen: No, Yes
61  // config: 0:"No (default)", 1:"Yes"
62  VALUES{"No", "Yes", 0}},
63  {0x00000030, 4, "Security", "SBITS", 0,
64  // bitgen: None, Level1, Level2
65  // config: 00:"Read/Write OK (default)", 01:"Readback disabled", 1x:"Both writes and
66  // read disabled."
67  VALUES{"None", "Level1", "Level2", "Level2", 0}},
68  {0x00000040, 6, "Encrypt", "DEC", 0,
69  // bitgen: No, Yes
70  // config: AES Decryptor enable bit
71  VALUES{"No", "Yes", 0}},
72  {0x00000080, 7, "FARSRC", "FARSRC", 0,
73  // bitgen: n/a
74  // config: 0: FAR, address of RBCRC, 1: EFAR, address of ECC error frame
75  VALUES{"FAR", "EFAR", 0}},
76  {0x00000100, 8, "GLUTMASK", "GLUTMASK", 0,
77  // bitgen: n/a
78  // config: 0:"Readback all 0s from SRL16 and Distributed RAM. Use with active device
79  // readback.", 1:"Readback dynamic values from SRL16 and Distributed RAM. Use with
80  // shutdown readback."
81  VALUES{"Masked", "Dynamic", 0}},
82  {0x00001000, 12, "OverTempPowerDown", "OverTempPowerDown", 0,
83  // bitgen: Disable, Enable
84  // config: Enables the System Monitor Over-Temperature power down.
85  VALUES{"Disable", "Enable", 0}},
86  {0x40000000, 30, "ICAP_sel", "ICAP_SEL", 0,
87  // bitgen: n/a
88  // config: 0:"Top ICAP Port Enabled (default)", 1:"Bottom ICAP Port Enabled"
89  VALUES{"Top", "Bottom", 0}},
90  {0x80000000, 31, "EFUSE_key", "EFUSE_KEY", 0,
91  // bitgen: n/a
92  // config: 0:"Battery-back RAM", 1:"eFUSE"
93  VALUES{"No", "Yes", 0}},
94  {0, 0, 0, 0, 0, 0}
95  };
96 
97  /// \see Control Register 0 (CTL0): UG470, v1.1, March 28, 2011, Table 5-22.
98  const Bitstream::Subfield Virtex7::sMASK0[] = {
99  {0x00000001, 0, "GTS_USER_B", "GTS_USER_B", 0, VALUES{"Protected", "Writable", 0}},
100  {0x00000008, 3, "Persist", "PERSIST", 0, VALUES{"Protected", "Writable", 0}},
101  {0x00000030, 4, "Security", "SBITS", 0,
102  VALUES{"Protected", "[UNKNOWN 1]", "[UNKNOWN 2]", "Writable", 0}},
103  {0x00000040, 6, "Encrypt", "DEC", 0, VALUES{"Protected", "Writable", 0}},
104  {0x00000080, 7, "FARSRC", "FARSRC", 0, VALUES{"Protected", "Writable", 0}},
105  {0x00000100, 8, "GLUTMASK", "GLUTMASK", 0, VALUES{"Protected", "Writable", 0}},
106  {0x00001000, 12, "OverTempPowerDown", "OverTempPowerDown", 0,
107  VALUES{"Protected", "Writable", 0}},
108  {0x40000000, 30, "ICAP_sel", "ICAP_SEL", 0, VALUES{"Protected", "Writable", 0}},
109  {0x80000000, 31, "EFUSE_key", "EFUSE_KEY", 0, VALUES{"Protected", "Writable", 0}},
110  {0, 0, 0, 0, 0, 0}
111  };
112 
113  /// \see Control Register 1 (CTL1): UG470, v1.1, March 28, 2011, Table 5-36
114  const Bitstream::Subfield Virtex7::sCTL1[] = {
115  {0, 0, 0, 0, 0, 0}
116  };
117 
118 
119  /// \see Configurations Options Register 0 (COR0): UG470, v1.1, March 28, 2011, Table 5-27.
120  const Bitstream::Subfield Virtex7::sCOR0[] = {
121  {0x00000007, 0, "GWE_cycle", "GWE_CYCLE", 5,
122  // bitgen: 6, 1, 2, 3, 4, 5, Done, Keep
123  // config: 000:"1", 001:"2", 010:"3", 011:"4", 100:"5", 101:"6", 110:"GTS tracks DONE
124  // pin. BitGen option -g GTS_cycle:Done", 111:"Keep"
125  VALUES{"1", "2", "3", "4", "5", "6", "Done", "Keep", 0}},
126  {0x00000038, 3, "GTS_cycle", "GTS_CYCLE", 4,
127  // bitgen: 5, 1, 2, 3, 4, 6, Done, Keep
128  // config: 000:"1", 001:"2", 010:"3", 011:"4", 100:"5", 101:"6", 110:"GTS tracks DONE
129  // pin. BitGen option -g GTS_cycle:Done", 001:"Keep"
130  VALUES{"1", "2", "3", "4", "5", "6", "Done", "Keep", 0}},
131  {0x000001C0, 6, "LCK_cycle", "LOCK_CYCLE", 0,
132  // bitgen: NoWait, 0, 1, 2, 3, 4, 5, 6
133  // config: 000:"0", 001:"1", 010:"2", 011:"3", 100:"4", 101:"5", 110:"6", 111:"No Wait"
134  VALUES{"0", "1", "2", "3", "4", "5", "6", "No Wait", 0}},
135  {0x00000E00, 9, "Match_cycle", "MATCH_CYCLE", 0,
136  // bitgen: Auto, NoWait, 0, 1, 2, 3, 4, 5, 6
137  // config: 000:"0", 001:"1", 010:"2", 011:"3", 100:"4", 101:"5", 110:"6", 111:"KEEP"
138  VALUES{"0", "1", "2", "3", "4", "5", "6", "NoWait", 0}},
139  {0x00007000, 12, "DONE_cycle", "DONE_CYCLE", 3,
140  // bitgen: 4, 1, 2, 3, 5, 6
141  // config: 000:"1", 001:"2", 010:"3", 011:"4", 100:"5", 101:"6", 110:"7", 111:"KEEP"
142  VALUES{"1", "2", "3", "4", "5", "6", "7", "KEEP", 0}},
143  {0x00018000, 15, "StartupClk", "SSCLKSRC", 0,
144  // bitgen: Cclk, UserClk, JtagClk
145  // config: 00:"CCLK", 01:"UserClk", 1x:"JTAGClk"
146  VALUES{"Cclk", "UserClk", "JtagClk", "JtagClk", 0}},
147  {0x007e0000, 17, "ConfigRate", "OSCFSEL", 0,
148  // bitgen: 2, 4, 6, 10, 12, 16, 22, 26, 33, 40, 50, 66
149  // config: values undefined
150  VALUES{
151  "[UNKNOWN 0]", "[UNKNOWN 1]", "[UNKNOWN 2]", "[UNKNOWN 3]",
152  "[UNKNOWN 4]", "[UNKNOWN 5]", "[UNKNOWN 6]", "[UNKNOWN 7]",
153  "[UNKNOWN 8]", "[UNKNOWN 9]", "[UNKNOWN 10]", "[UNKNOWN 11]",
154  "[UNKNOWN 12]", "[UNKNOWN 13]", "[UNKNOWN 14]", "[UNKNOWN 15]",
155  "[UNKNOWN 16]", "[UNKNOWN 17]", "[UNKNOWN 18]", "[UNKNOWN 19]",
156  "[UNKNOWN 20]", "[UNKNOWN 21]", "[UNKNOWN 22]", "[UNKNOWN 23]",
157  "[UNKNOWN 24]", "[UNKNOWN 25]", "[UNKNOWN 26]", "[UNKNOWN 27]",
158  "[UNKNOWN 28]", "[UNKNOWN 29]", "[UNKNOWN 30]", "[UNKNOWN 31]",
159  0}},
160  {0x00800000, 23, "Capture", "SINGLE", 0,
161  // bitgen: n/a -- this comes from the CAPTURE site ONESHOT setting
162  // config: 0:"Readback is not single-shot", 1:"Readback is single-shot"
163  VALUES{"Continuous", "OneShot", 0}},
164  {0x01000000, 24, "DriveDone", "DRIVE_DONE", 0,
165  // bitgen: No, Yes
166  // config: 0:"DONE pin is open drain", 1:"DONE is actively driven high"
167  VALUES{"No", "Yes", 0}},
168  {0x02000000, 25, "DonePipe", "DONE_PIPE", 0,
169  // bitgen: Yes, No
170  // config: 0:"No pipeline stage for DONEIN", 1:"Add pipeline stage for DONEIN"
171  VALUES{"No", "Yes", 0}},
172  {0x08000000, 27, "DONE_status", "PWRDWN_STAT", 0,
173  // bitgen: n/a?
174  // config: 0:"DONE pin", 1:"Powerdown pin"
175  VALUES{"DonePin", "PowerdownPin", 0}},
176  {0, 0, 0, 0, 0, 0}
177  };
178 
179  ///\see Configurations Options Register 1 (COR1): UG470 v1.1, March 28, 2011, Table 5-29 .
180  const Bitstream::Subfield Virtex7::sCOR1[] = {
181  {0x00000003, 0, "BPI_page_size", "BPI_PAGE_SIZE", 0,
182  // bitgen: 1, 4, 8
183  // config: 00:"1 byte/word", 01:"4 bytes/words", 10:"8 bytes/words", 11:"Reserved"
184  VALUES{"1", "4", "8", "Reserved", 0}},
185  {0x0000000C, 2, "BPI_1st_read_cycle", "BPI_1ST_READ_CYCLES", 0,
186  // bitgen: 1, 2, 3, 4
187  // config: 00:"1", 01:"2", 10:"3", 11:"4"
188  VALUES{"1", "2", "3", "4", 0}},
189  //VALUES{"1", "4", "8", "Reserved", 0}}, // WHY ?!
190  {0x00000100, 8, "ContinuousReadbackCRC", "RBCRC_EN", 0,
191  // bitgen: n/a?
192  // config: Continuous readback CRC enable
193  VALUES{"Enabled", "disabled", 0}},
194  //VALUES{"Disabled", "Enabled", 0}}, // WHY?!
195  {0x00000200, 9, "InitAsCRCErrorPin", "RBCRC_NO_PIN", 0,
196  // bitgen: n/a?
197  // config: Disables INIT_B as read back CRC error status output pin
198  VALUES{"Disabled", "Enabled", 0}},
199  {0x00018000, 15, "ActionReadbackCRC", "RBCRC_ACTION", 0,
200  // bitgen: n/a?
201  // config: Action for readback CRC 00:"1", 01:"2", 10:"3", 11:"4"
202  VALUES{"Continue", "Halt", "CorrectAndHalt", "CorrectAndContinue", 0}},
203  {0x00020000, 17, "PersistDeassertAtDesynch", "PERSIST_DEASSERT_AT_DESYNCH", 0,
204  // bitgen: n/a?
205  // config: Enables deassertion of PERSIST with the DESYNCH command
206  VALUES{"Disabled", "Enabled", 0}},
207  {0, 0, 0, 0, 0, 0}
208  };
209 
210  /// \see WBSTAR Register Descrption: UG470, v1.1, March 28, 2011, Table 5-31.
211  const Bitstream::Subfield Virtex7::sWBSTAR[] = {
212  {0x40000000, 30, "NextRevisionSelect", "RS[1:0]", 0,
213  // config: RS[1:0] pin value on next warm boot
214  VALUES{"00", "01", "10", "11", 0}},
215  {0x20000000, 29, "RevisionSelectTristate", "RS_TS_B", 0,
216  // config: 0:"Disabled", 1:"Enabled"
217  VALUES{"Disabled", "Enabled", 0}},
218  {0, 0, 0, 0, 0, 0}
219  };
220 
221  /// \see TIMER Register Description: UG470, v1.1, March 28, 2011, Table 5-33.
222  const Bitstream::Subfield Virtex7::sTIMER[] = {
223  {0x40000000, 30, "TimerForConfig", "TIMER_CFG_MON", 0,
224  // config: 0:"Disabled", 1:"Enabled"
225  VALUES{"Disabled", "Enabled", 0}},
226  {0x80000000, 31, "TimerForUser", "TIMER_USR_MON", 0,
227  // config: 0:"Disabled", 1:"Enabled"
228  VALUES{"Disabled", "Enabled", 0}},
229  {0, 0, 0, 0, 0, 0}
230  };
231 
232  /// \see BOOTSTS Register Description: UG470, v1.1, March 28, 2011, Table 5-35.
233  const Bitstream::Subfield Virtex7::sBOOTSTS[] = {
234  {0x00000001, 0, "RegisterStatus0", "VALID_0", 0,
235  // config: Status valid
236  VALUES{"Valid", "Invalid", 0}},
237  {0x00000002, 1, "FallbackStatus0", "FALLBACK_0", 0,
238  // config: 0:"Normal configuration", 1:"Fallback to default reconfiguration, RS[1:0]
239  // actively drives 2'b00"
240  VALUES{"Normal", "Fallback", 0}},
241  {0x00000004, 2, "InternalTrigger0", "IPROG_0", 0,
242  // config: Internal PROG triggered configuration
243  VALUES{"External", "Internal", 0}},
244  {0x00000008, 3, "WatchdogTimeout0", "WTO_ERROR_0", 0,
245  // config: Watchdog time-out error
246  VALUES{"Valid", "Invalid", 0}},
247  {0x00000010, 4, "ID_error0", "ID_ERROR_0", 0,
248  // config: ID error
249  VALUES{"NoError", "Error", 0}},
250  {0x00000020, 5, "CRC_error0", "CRC_ERROR_0", 0,
251  // config: CRC error
252  VALUES{"NoError", "Error", 0}},
253  {0x00000040, 6, "BPI_wraparound_error0", "WRAP_ERROR_0", 0,
254  // config: BPI address counter wraparound error
255  VALUES{"NoError", "Error", 0}},
256  {0x00000100, 8, "RegisterStatus1", "VALID_1", 0,
257  // config: Status valid
258  VALUES{"Valid", "Invalid", 0}},
259  {0x00000200, 9, "FallbackStatus1", "FALLBACK_1", 0,
260  // config: 0:"Normal configuration", 1:"Fallback to default reconfiguration, RS[1:0]
261  // actively drives 2'b00"
262  VALUES{"Normal", "Fallback", 0}},
263  {0x00000400, 10, "InternalTrigger1", "IPROG_1", 0,
264  // config: Internal PROG triggered configuration
265  VALUES{"External", "Internal", 0}},
266  {0x00000800, 11, "WatchdogTimeout1", "WTO_ERROR_1", 0,
267  // config: Watchdog time-out error
268  VALUES{"Valid", "Invalid", 0}},
269  {0x00001000, 12, "ID_error1", "ID_ERROR_1", 0,
270  // config: ID error
271  VALUES{"NoError", "Error", 0}},
272  {0x00002000, 13, "CRC_error1", "CRC_ERROR_1", 0,
273  // config: CRC error
274  VALUES{"NoError", "Error", 0}},
275  {0x00004000, 14, "BPI_wraparound_error1", "WRAP_ERROR_1", 0,
276  // config: BPI address counter wraparound error
277  VALUES{"NoError", "Error", 0}},
278  {0, 0, 0, 0, 0, 0}
279  };
280 
281  /// \see Status Register Description: UG470, v1.1, March 28, 2011, Table 5-25.
282  const Bitstream::Subfield Virtex7::sSTAT[] = {
283  {0x00000001, 0, "CRC_error", "CRC_ERROR", 0,
284  // bitgen: n/a
285  // config: 0:"No CRC error", 1:"CRC error"
286  VALUES{"No", "Yes", 0}},
287  {0x00000002, 1, "DecryptorSecuritySet", "PART_SECURED", 0,
288  // bitgen: n/a
289  // config: 0:"Decryptor security not set", 1:"Decryptor security set"
290  VALUES{"No", "Yes", 0}},
291  {0x00000004, 2, "MMCM_locked", "MMCM_LOCK", 0,
292  // bitgen: n/a
293  // config: 0:"MMCMs not locked", 1:"MMCMs are locked"
294  VALUES{"No", "Yes", 0}},
295  {0x00000008, 3, "DCI_matched", "DCI_MATCH", 0,
296  // bitgen: n/a
297  // config: 0:"DCI not matched", 1:"DCI matched
298  VALUES{"No", "Yes", 0}},
299  {0x00000010, 4, "StartupFinished", "EOS", 0,
300  // bitgen: n/a
301  // config: 0:"Startup sequence has not finished", 1:"Startup sequence has finished"
302  VALUES{"No", "Yes", 0}},
303  {0x00000020, 5, "GTS_CFG_B", "GTS_CFG_B", 0,
304  // bitgen: n/a
305  // config: 0:"All I/Os are placed in high-Z state", 1:"All I/Os behave as configured"
306  VALUES{"IoDisabled", "IoEnabled", 0}},
307  {0x00000040, 6, "GWE", "GWE", 0,
308  // bitgen: n/a
309  // config: 0:"FFs and block RAM are write disabled", 1:"FFs and block RAM are write
310  // enabled"
311  VALUES{"WriteDisabled", "WriteEnabled", 0}},
312  {0x00000080, 7, "GHIGH_B", "GHIGH_B", 0,
313  // bitgen: n/a
314  // config: 0:"GHIGH_B asserted", 1:"GHIGH_B deasserted"
315  VALUES{"InterconnectDisabled", "InterconnectEnabled", 0}},
316  {0x00000700, 8, "Mode", "MODE", 0,
317  // bitgen: n/a
318  // config: Status of the MODE pins (M2:M0)
319  VALUES{"MasterSerial", "MasterSPI", "MasterBPI-Up", "MasterBPI-Down",
320  "MasterSelectMap", "JTAG", "SlaveSelectMap", "SlaveSerial", 0}},
321  {0x00000800, 11, "INIT_complete", "INIT_COMPLETE", 0,
322  // bitgen: n/a
323  // config: 0:"Initializations has not finished", 1:"Initialization finished"
324  VALUES{"No", "Yes", 0}},
325  {0x00000800, 11, "INIT_complete", "INIT_COMPLETE", 0,
326  // bitgen: n/a
327  // config: 0:"Initializations has not finished", 1:"Initialization finished"
328  VALUES{"No", "Yes", 0}},
329  {0x00001000, 12, "INIT_B", "INIT_B", 0,
330  // bitgen: n/a
331  // config: Value on INIT_B pin
332  VALUES{"Deasserted", "Asserted", 0}},
333  {0x00002000, 13, "DONE_released", "RELEASE_DONE", 0,
334  // bitgen: n/a
335  // config: 0:"DONE signal not released", 1:"DONE signal released"
336  VALUES{"DrivenLow", "Released", 0}},
337  {0x00004000, 14, "DONE", "DONE", 0,
338  // bitgen: n/a
339  // config: Value on DONE pin
340  VALUES{"NotDone", "Done", 0}},
341  {0x00008000, 15, "ID_error", "ID_ERROR", 0,
342  // bitgen: n/a
343  // config: 0:"No IE_ERROR", 1:"ID_ERROR"
344  VALUES{"NoError", "Error", 0}},
345  {0x00010000, 16, "Decrypt_error", "DEC_ERROR", 0,
346  // bitgen: n/a
347  // config: 0:"No DEC_ERROR", 1:"DEC_ERROR"
348  VALUES{"NoError", "Error", 0}},
349  {0x001c0000, 18, "StartupState", "STARTUP_STATE", 0,
350  // bitgen: n/a
351  // config: 000:"0", 001:"1", 010:"3", 011:"2", 100:"7", 101:"6", 110:"4", 111:"5"
352  VALUES{"0", "1", "3", "2", "7", "6", "4", "5", 0}},
353  {0x06000000, 25, "BusWidth", "BUS_WIDTH", 0,
354  // bitgen: n/a
355  // config: 00:"x1", 01:"x8", 10:"x16", 11:"x32"
356  VALUES{"1", "8", "16", "32", 0}},
357  {0, 0, 0, 0, 0, 0}
358  };
359 
360  /// \brief Return the masked value for a subfield of the specified register.
361  uint32_t Virtex7::makeSubfield(ERegister inRegister, const std::string& inSubfield,
362  const std::string& inSetting) {
363  const Subfield* subfields;
364  switch(inRegister) {
365  case eRegisterCOR0: subfields = sCOR0; break;
366  case eRegisterCOR1: subfields = sCOR1; break;
367  case eRegisterSTAT: subfields = sSTAT; break;
368  case eRegisterCTL0: subfields = sCTL0; break;
369  case eRegisterCTL1: subfields = sCTL1; break;
370  case eRegisterMASK: subfields = sMASK0; break;
371  case eRegisterWBSTAR: subfields = sWBSTAR; break;
372  case eRegisterTIMER: subfields = sTIMER; break;
373  case eRegisterBOOTSTS: subfields = sBOOTSTS; break;
374  default: return 0;
375  }
376  for(uint32_t field = 0; subfields[field].mMask != 0; field++){
377  const Subfield& subfield = subfields[field];
378  if(inSubfield != subfield.mBitgenName && inSubfield != subfield.mConfigGuideName)
379  continue;
380  const char** ptr = subfield.mValues;
381  for(uint32_t i = 0; *ptr != 0; i++, ptr++){
382  if(inSetting == *ptr) return (i << subfield.mShift) & subfield.mMask;
383  }
384  }
385  return 0;
386  }
387 
388 //#define GENERATE_STATIC_DEVICE_INFO
389 #ifndef GENERATE_STATIC_DEVICE_INFO
390 
391  extern DeviceInfo xc7a100t;
392  extern DeviceInfo xc7a200t;
393  extern DeviceInfo xc7k70t;
394  extern DeviceInfo xc7k160t;
395  extern DeviceInfo xc7k325t;
396  extern DeviceInfo xc7k355t;
397  extern DeviceInfo xc7k410t;
398  extern DeviceInfo xc7k420t;
399  extern DeviceInfo xc7k480t;
400  extern DeviceInfo xc7v585t;
401  extern DeviceInfo xc7v2000t;
402  extern DeviceInfo xc7vh580t;
403  extern DeviceInfo xc7vh870t;
404  extern DeviceInfo xc7vx330t;
405  extern DeviceInfo xc7vx415t;
406  extern DeviceInfo xc7vx485t;
407  extern DeviceInfo xc7vx550t;
408  extern DeviceInfo xc7vx690t;
409  extern DeviceInfo xc7vx980t;
410  extern DeviceInfo xc7vx1140t;
411  extern DeviceInfo xc7z010;
412  extern DeviceInfo xc7z020;
413  extern DeviceInfo xc7z030;
414  extern DeviceInfo xc7z045;
415 
416  void Virtex7::initializeDeviceInfo(const std::string& inDeviceName) {
417  using namespace torc::common;
418  switch(mDevice) {
419  case eXC7A100T: setDeviceInfo(xc7a100t); break;
420  case eXC7A200T: setDeviceInfo(xc7a200t); break;
421  case eXC7K70T: setDeviceInfo(xc7k70t); break;
422  case eXC7K160T: setDeviceInfo(xc7k160t); break;
423  case eXC7K325T: setDeviceInfo(xc7k325t); break;
424  case eXC7K355T: setDeviceInfo(xc7k355t); break;
425  case eXC7K410T: setDeviceInfo(xc7k410t); break;
426  case eXC7K420T: setDeviceInfo(xc7k420t); break;
427  case eXC7K480T: setDeviceInfo(xc7k480t); break;
428  case eXC7V585T: setDeviceInfo(xc7v585t); break;
429  case eXC7V2000T: setDeviceInfo(xc7v2000t); break;
430  case eXC7VH580T: setDeviceInfo(xc7vh580t); break;
431  case eXC7VH870T: setDeviceInfo(xc7vh870t); break;
432  case eXC7VX330T: setDeviceInfo(xc7vx330t); break;
433  case eXC7VX415T: setDeviceInfo(xc7vx415t); break;
434  case eXC7VX485T: setDeviceInfo(xc7vx485t); break;
435  case eXC7VX550T: setDeviceInfo(xc7vx550t); break;
436  case eXC7VX690T: setDeviceInfo(xc7vx690t); break;
437  case eXC7VX980T: setDeviceInfo(xc7vx980t); break;
438  case eXC7VX1140T: setDeviceInfo(xc7vx1140t); break;
439  case eXC7Z010: setDeviceInfo(xc7z010); break;
440  case eXC7Z020: setDeviceInfo(xc7z020); break;
441  case eXC7Z030: setDeviceInfo(xc7z030); break;
442  case eXC7Z045: setDeviceInfo(xc7z045); break;
443  default: break;
444  }
445 
446  // update the top and bottom bitstream row counts as appropriate for the device
447  setRowCounts(inDeviceName);
448  }
449 
450 #else
451 
452  void Virtex7::initializeDeviceInfo(const std::string& inDeviceName) {
453 
454  typedef torc::architecture::xilinx::TileCount TileCount;
455  typedef torc::architecture::xilinx::TileRow TileRow;
456  typedef torc::architecture::xilinx::TileCol TileCol;
457  typedef torc::architecture::xilinx::TileTypeIndex TileTypeIndex;
458  typedef torc::architecture::xilinx::TileTypeCount TileTypeCount;
459 
460 // ColumnDefVector::iterator p = mColumnDefs.begin();
461 // ColumnDefVector::iterator e = mColumnDefs.end();
462 // std::cerr << "========== ColumnDefs ==========" << std::endl;
463 // while(p < e) {
464 // ColumnDef& columnDef = *p++;
465 // std::cerr << columnDef.getName() << ": "
466 // << columnDef[0] << ", " << columnDef[1] << ", " << columnDef[2] << ", "
467 // << columnDef[3] << ", " << columnDef[4] << ", " << columnDef[5] << ", "
468 // << columnDef[6] << ", " << columnDef[7] << std::endl;
469 // }
470 // std::cerr << "================================" << std::endl;
471 
472  // clear variables before starting
473  // this is in part important because the various 7-Series families do not share the same
474  // family databases, and consequently may have different mTileTypeIndexToColumnType mappings
475  mFrameRowCount = mTopRowCount = mBottomRowCount = 0;
476  mFrameIndexToAddress.clear();
477  mFrameAddressToIndex.clear();
478  for(int i = 0; i < eBlockTypeCount; i++) {
479  mBitColumnIndexes[i].clear();
480  mXdlColumnIndexes[i].clear();
481  mBlockFrameIndexBounds[i] = 0;
482  }
483  mBitColumnToXdlColumn.clear();
484  mXdlRowToFrameRowDesignator.clear();
485  mTileTypeIndexToColumnType.clear();
486 
487  // look up the device tile map
488  torc::architecture::DDB ddb(inDeviceName);
489  const torc::architecture::Tiles& tiles = ddb.getTiles();
490  uint32_t tileCount = tiles.getTileCount();
491  uint16_t rowCount = tiles.getRowCount();
492  uint16_t colCount = tiles.getColCount();
493  ColumnTypeVector columnTypes;
494 //std::cerr << "tile count: " << tileCount << ", row count: " << rowCount << ", col count " << colCount << std::endl;
495 
496  // set up the tile index and name mappings, and the index to column def mapping
497  typedef std::map<TileTypeIndex, std::string> TileTypeIndexToName;
498  typedef std::map<std::string, TileTypeIndex> TileTypeNameToIndex;
499  TileTypeIndexToName tileTypeIndexToName;
500  TileTypeNameToIndex tileTypeNameToIndex;
501  TileTypeCount tileTypeCount = tiles.getTileTypeCount();
502  for(TileTypeIndex tileTypeIndex(0); tileTypeIndex < tileTypeCount; tileTypeIndex++) {
503  const std::string tileTypeName = tiles.getTileTypeName(tileTypeIndex);
504  tileTypeIndexToName[tileTypeIndex] = tileTypeName;
505  tileTypeNameToIndex[tileTypeName] = tileTypeIndex;
506  TileTypeNameToColumnType::iterator ttwp = mTileTypeNameToColumnType.find(tileTypeName);
507  TileTypeNameToColumnType::iterator ttwe = mTileTypeNameToColumnType.end();
508  if(ttwp != ttwe) mTileTypeIndexToColumnType[tileTypeIndex] = EColumnType(ttwp->second);
509 //if(ttwp != ttwe) {
510 // std::cout << "Tile type index " << tileTypeIndex << "\tmapped " << tileTypeName
511 // << " to " << ttwp->second << std::endl;
512 //}
513  }
514 
515  // map XDL tiles to top/bottom halves and frame rows
516  setRowCounts(inDeviceName);
517  mFrameRowCount = mBottomRowCount + mTopRowCount;
518  columnTypes.resize(colCount * mFrameRowCount);
519  bool isArtix200t = mDevice == common::eXC7A200T;
520  bool isZynq010 = mDevice == common::eXC7Z010;
521 
522  // initialize the XDL rows and columns
523  uint32_t xdlCenterRow = mTopRowCount * eClockRegionRows;
524  uint32_t baseCol = 0;
525  // iterate over both halves of the device
526  for(uint8_t half = 0; half < 2; half++) {
527  EFarTopBottom topBottom(half == eFarTop ? eFarTop : eFarBottom);
528  // determine the row count and XDL row offset
529  uint32_t farRowCount = topBottom == eFarTop ? mTopRowCount : mBottomRowCount;
530  // iterate over the frame rows
531  for(uint32_t farRow = 0; farRow < farRowCount; farRow++) {
532  // determine the XDL base row for this frame row
533  TileRow xdlBaseRow(topBottom == eFarTop
534  ? (xdlCenterRow - (farRow + 1) * eClockRegionRows)
535  : (xdlCenterRow + (farRow + 0) * eClockRegionRows)
536  );
537  // iterate over the XDL columns
538  uint32_t bitCol = 0;
539  for(TileCol xdlCol(0); xdlCol < colCount; xdlCol++) {
540  // special case for the xc7a200t: we make all rows like bottom row 0
541  TileRow xdlRow(isArtix200t ? xdlCenterRow : xdlBaseRow);
542  // try to identify the column type
543  columnTypes[baseCol + xdlCol] = eColumnTypeEmpty;
544  TileTypeIndexToColumnType::iterator ttwe = mTileTypeIndexToColumnType.end();
545  TileTypeIndexToColumnType::iterator ttwp = ttwe;
546  // iterate over the XDL rows within the frame row
547  for(int rowOffset = 0; rowOffset < eClockRegionRows; rowOffset++, xdlRow++) {
548  // look up the tile info
549  const torc::architecture::TileInfo& tileInfo
550  = tiles.getTileInfo(tiles.getTileIndex(xdlRow, xdlCol));
551  TileTypeIndex tileTypeIndex = tileInfo.getTypeIndex();
552  // determine whether the tile type widths are defined
553  ttwp = mTileTypeIndexToColumnType.find(tileTypeIndex);
554  if(ttwp != ttwe) {
555  // what an ugly way to handle the PSS macro-column
556  if(EColumnType(ttwp->second) == eColumnTypePss) {
557  // this is for the xc7z010
558  if(isZynq010) {
559  // the density of this layout is purely conjectural
560  // column types match frame addresses and other Zynq devices
561  columnTypes[baseCol + xdlCol - 12] = eColumnTypeIoi;
562  columnTypes[baseCol + xdlCol - 11] = eColumnTypeCmt;
563  columnTypes[baseCol + xdlCol - 10] = eColumnTypeClb;
564  columnTypes[baseCol + xdlCol - 9] = eColumnTypeClb;
565  columnTypes[baseCol + xdlCol - 8] = eColumnTypeClb;
566  columnTypes[baseCol + xdlCol - 7] = eColumnTypeClb;
567  columnTypes[baseCol + xdlCol - 6] = eColumnTypeBram;
568  columnTypes[baseCol + xdlCol - 5] = eColumnTypeClb;
569  columnTypes[baseCol + xdlCol - 4] = eColumnTypeClb;
570  columnTypes[baseCol + xdlCol - 3] = eColumnTypeDsp;
571  columnTypes[baseCol + xdlCol - 2] = eColumnTypeClb;
572  columnTypes[baseCol + xdlCol - 1] = eColumnTypeClb;
573  columnTypes[baseCol + xdlCol + 0] = eColumnTypeClb;
574  columnTypes[baseCol + xdlCol + 1] = eColumnTypeClb;
575  columnTypes[baseCol + xdlCol + 2] = eColumnTypeDsp;
576  columnTypes[baseCol + xdlCol + 3] = eColumnTypeClb;
577  columnTypes[baseCol + xdlCol + 4] = eColumnTypeClb;
578  columnTypes[baseCol + xdlCol + 5] = eColumnTypeBram;
579  columnTypes[baseCol + xdlCol + 6] = eColumnTypeClb;
580  xdlCol += 6;
581  bitCol += 19;
582  break;
583  // this is for all other Zynq devices
584  } else {
585  // this layout is based on bottom row 1 of xc7z020 and others
586  columnTypes[baseCol + xdlCol - 31] = eColumnTypeIoi;
587  columnTypes[baseCol + xdlCol - 27] = eColumnTypeInt;
588  columnTypes[baseCol + xdlCol - 28] = eColumnTypeInt;
589  columnTypes[baseCol + xdlCol - 25] = eColumnTypeCmt;
590  columnTypes[baseCol + xdlCol - 22] = eColumnTypeClb;
591  columnTypes[baseCol + xdlCol - 21] = eColumnTypeInt;
592  columnTypes[baseCol + xdlCol - 20] = eColumnTypeInt;
593  columnTypes[baseCol + xdlCol - 19] = eColumnTypeClb;
594  columnTypes[baseCol + xdlCol - 18] = eColumnTypeClb;
595  columnTypes[baseCol + xdlCol - 17] = eColumnTypeInt;
596  columnTypes[baseCol + xdlCol - 16] = eColumnTypeInt;
597  columnTypes[baseCol + xdlCol - 15] = eColumnTypeClb;
598  columnTypes[baseCol + xdlCol - 13] = eColumnTypeBram;
599  columnTypes[baseCol + xdlCol - 11] = eColumnTypeInt;
600  columnTypes[baseCol + xdlCol - 10] = eColumnTypeInt;
601  columnTypes[baseCol + xdlCol - 9] = eColumnTypeClb;
602  columnTypes[baseCol + xdlCol - 8] = eColumnTypeClb;
603  columnTypes[baseCol + xdlCol - 7] = eColumnTypeInt;
604  columnTypes[baseCol + xdlCol - 6] = eColumnTypeInt;
605  columnTypes[baseCol + xdlCol - 4] = eColumnTypeDsp;
606  columnTypes[baseCol + xdlCol - 2] = eColumnTypeClb;
607  columnTypes[baseCol + xdlCol - 1] = eColumnTypeInt;
608  columnTypes[baseCol + xdlCol + 0] = eColumnTypeInt;
609  columnTypes[baseCol + xdlCol + 1] = eColumnTypeClb;
610  columnTypes[baseCol + xdlCol + 2] = eColumnTypeClb;
611  columnTypes[baseCol + xdlCol + 3] = eColumnTypeInt;
612  columnTypes[baseCol + xdlCol + 4] = eColumnTypeInt;
613  columnTypes[baseCol + xdlCol + 5] = eColumnTypeClb;
614  columnTypes[baseCol + xdlCol + 7] = eColumnTypeDsp;
615  columnTypes[baseCol + xdlCol + 9] = eColumnTypeInt;
616  columnTypes[baseCol + xdlCol + 10] = eColumnTypeInt;
617  columnTypes[baseCol + xdlCol + 11] = eColumnTypeClb;
618  columnTypes[baseCol + xdlCol + 12] = eColumnTypeClb;
619  columnTypes[baseCol + xdlCol + 13] = eColumnTypeInt;
620  columnTypes[baseCol + xdlCol + 14] = eColumnTypeInt;
621  columnTypes[baseCol + xdlCol + 16] = eColumnTypeBram;
622  columnTypes[baseCol + xdlCol + 18] = eColumnTypeClb;
623  xdlCol += 18;
624  bitCol += 37;
625  break;
626  }
627  }
628 //std::cout << "" << (topBottom == eFarTop ? "top" : "bottom") << ", far row: " << farRow
629 // << ", xdl column: " << xdlCol << " (" << baseCol + xdlCol << "), bit column: "
630 // << bitCol << ", xdl base row: " << xdlBaseRow;
631  //std::cout << " " << tiles.getTileTypeName(tileInfo.getTypeIndex())
632  // << std::endl;
633  columnTypes[baseCol + xdlCol] = static_cast<EColumnType>(ttwp->second);
634  bitCol++;
635  break;
636  }
637  }
638  }
639  baseCol += colCount;
640  }
641  }
642 
643  // write out the tile map as a spreadsheet
644  boost::filesystem::path workingPath = torc::common::DirectoryTree::getWorkingPath();
645  boost::filesystem::path generatedMap = workingPath / (inDeviceName + ".map.csv");
646  std::fstream tilemapStream(generatedMap.string().c_str(), std::ios::out);
647  for(TileRow row; row < rowCount; row++) {
648  for(TileCol col; col < colCount; col++) {
649  const torc::architecture::TileInfo& tileInfo
650  = tiles.getTileInfo(tiles.getTileIndex(row, col));
651  TileTypeIndex tileTypeIndex = tileInfo.getTypeIndex();
652  tilemapStream << tiles.getTileTypeName(tileTypeIndex);
653  if(col + 1 < colCount) tilemapStream << ",";
654  }
655  tilemapStream << std::endl;
656  }
657  tilemapStream.close();
658 
659  // update bitstream device information
660 //std::cerr << "tile count: " << tileCount << ", row count: " << rowCount << ", col count " << colCount << std::endl;
661 //std::cout << "invoking setDeviceInfo()" << std::endl;
662  setDeviceInfo(DeviceInfo(tileCount, rowCount, colCount, columnTypes));
663 //std::cout << "finished setDeviceInfo()" << std::endl;
664 // setRowCounts(inDeviceName);
665 
666  }
667 
668 #endif
669 
670  void Virtex7::setRowCounts(const string& inDeviceName) {
671  // The division between top and bottom rows can be determined by the locations of the
672  // CLK_HROW_TOP_R and CLK_HROW_BOT_R tiles in the clock column. The number of clock
673  // regions above and including the CLK_HROW_TOP_R tile determine the number of top rows in
674  // the bitstream. The number of clock regions below and including the CLK_HROW_BOT_R tile
675  // determine the number of bottom rows in the bitstream.
676  using namespace torc::common;
677  switch(mDevice) {
678  // Artix
679  case eXC7A100T: mTopRowCount = 2; mBottomRowCount = 2; break;
680  case eXC7A200T: mTopRowCount = 2; mBottomRowCount = 3; break;
681  // Kintex
682  case eXC7K70T: mTopRowCount = 2; mBottomRowCount = 2; break;
683  case eXC7K160T: mTopRowCount = 2; mBottomRowCount = 3; break;
684  case eXC7K325T: mTopRowCount = 4; mBottomRowCount = 3; break;
685  case eXC7K355T: mTopRowCount = 3; mBottomRowCount = 3; break;
686  case eXC7K410T: mTopRowCount = 4; mBottomRowCount = 3; break;
687  case eXC7K420T: mTopRowCount = 4; mBottomRowCount = 4; break;
688  case eXC7K480T: mTopRowCount = 4; mBottomRowCount = 4; break;
689  // Virtex
690  case eXC7V585T: mTopRowCount = 5; mBottomRowCount = 4; break;
691  case eXC7VX330T: mTopRowCount = 5; mBottomRowCount = 2; break;
692  case eXC7VX415T: mTopRowCount = 5; mBottomRowCount = 1; break;
693  case eXC7VX485T: mTopRowCount = 5; mBottomRowCount = 2; break;
694  case eXC7VX550T: mTopRowCount = 5; mBottomRowCount = 5; break;
695  case eXC7VX690T: mTopRowCount = 5; mBottomRowCount = 5; break;
696  case eXC7VX980T: mTopRowCount = 4; mBottomRowCount = 5; break;
697  // Zynq
698  case eXC7Z010: mTopRowCount = 1; mBottomRowCount = 1; break;
699  case eXC7Z020: mTopRowCount = 1; mBottomRowCount = 2; break;
700  case eXC7Z030: mTopRowCount = 1; mBottomRowCount = 3; break;
701  case eXC7Z045: mTopRowCount = 1; mBottomRowCount = 6; break;
702  default:
703  std::cerr << "Bitstream row dimensions are undefined for " << mDevice << "."
704  << std::endl;
705  mTopRowCount = 0; mBottomRowCount = 0;
706  break;
707  }
708  }
709 
710  void Virtex7::initializeFrameMaps(void) {
711 
712  bool debug = false;
713  setRowCounts(mDeviceName);
714  mFrameRowCount = mTopRowCount + mBottomRowCount;
715  if(mFrameRowCount == 0) return;
716  uint32_t frameCount = 0;
717 
718 //std::cerr << "row count: " << mDeviceInfo.getRowCount() << ", far row count: " << mFrameRowCount
719 // << std::endl;
720 
721  // map XDL tiles to top/bottom halves and frame rows
722  mXdlRowToFrameRowDesignator.resize(mDeviceInfo.getRowCount());
723  uint32_t xdlRow = 0;
724  uint32_t xdlBaseRow = xdlRow;
725  uint32_t baseCol = 0;
726  uint32_t serialFrame = mTopRowCount - 1;
727  baseCol = serialFrame * mDeviceInfo.getColCount();
728  for(uint32_t frameRow = mTopRowCount - 1; ; frameRow--) {
729  for(int i = 0; i < eClockRegionRows; i++, xdlRow++) {
730 //std::cout << "mapping XDL row " << xdlRow << " to top frame row " << frameRow << " (serial "
731 // << serialFrame << ")" << " (base " << xdlBaseRow << ") from " << baseCol << std::endl;
732  mXdlRowToFrameRowDesignator[xdlRow]
733  = FrameRowDesignator(eFarTop, serialFrame, xdlBaseRow, baseCol);
734  }
735  xdlBaseRow += eClockRegionRows;
736  baseCol -= mDeviceInfo.getColCount();
737  serialFrame--;
738  if(frameRow == 0) break;
739  }
740  // bottom half rows
741  serialFrame = mTopRowCount;
742  baseCol = serialFrame * mDeviceInfo.getColCount();
743  for(uint32_t frameRow = 0; frameRow < mBottomRowCount; frameRow++) {
744  for(int i = 0; i < eClockRegionRows; i++, xdlRow++) {
745 //std::cout << "mapping XDL row " << xdlRow << " to bottom frame row " << frameRow << " (serial "
746 // << serialFrame << ")" << " (base " << xdlBaseRow << ") from " << baseCol << std::endl;
747  mXdlRowToFrameRowDesignator[xdlRow]
748  = FrameRowDesignator(eFarBottom, serialFrame, xdlBaseRow, baseCol);
749  }
750  xdlBaseRow += eClockRegionRows;
751  baseCol += mDeviceInfo.getColCount();
752  serialFrame++;
753  }
754 
755  // generate the columns and mappings
756  uint32_t frameIndex = 0;
757  for(uint32_t i = 0; i < eFarBlockTypeCount; i++) {
758  EFarBlockType blockType = EFarBlockType(i);
759  uint32_t blockFrameIndexBounds = 0;
760  // set first frame index to 0
761  uint32_t bitIndex = 0;
762  uint32_t xdlIndex = 0;
763  mBitColumnIndexes[i].push_back(bitIndex);
764  mXdlColumnIndexes[i].push_back(xdlIndex);
765  bool blockUsed = false;
766  uint32_t baseCol = 0;
767  for(uint32_t half = 0; half < 2; half++) {
768  EFarTopBottom topBottom(half == eFarTop ? eFarTop : eFarBottom);
769  uint32_t farRowCount = (topBottom == eFarTop) ? mTopRowCount : mBottomRowCount;
770  for(uint32_t farRow = 0; farRow < farRowCount; farRow++) {
771  // build the columns
772  uint32_t farMajor = 0;
773  typedef torc::common::EncapsulatedInteger<uint16_t> ColumnIndex;
774  uint16_t finalColumn = mDeviceInfo.getColCount() - 1;
775  uint32_t xdlColumnCount = 0;
776  uint32_t bitColumnCount = 0;
777  for(ColumnIndex col; col < mDeviceInfo.getColCount(); col++) {
778  uint32_t realCol = col + baseCol;
779  uint32_t width
780  = mColumnDefs[mDeviceInfo.getColumnTypes()[col + baseCol]][i];
781 //std::cerr << "block: " << i << ", xdl col: " << col << " => " << realCol << ": "
782 // << mDeviceInfo.getColumnTypes()[realCol] << std::endl;
783  // allocate the frame maps
784  for(uint32_t farMinor = 0; farMinor < width; farMinor++) {
785  FrameAddress far(EFarTopBottom(topBottom),
786  blockType, farRow, farMajor, farMinor);
787  mFrameIndexToAddress[frameIndex] = far;
788  mFrameAddressToIndex[far] = frameIndex;
789  frameIndex++;
790  blockFrameIndexBounds++;
791  }
792 //if(width) std::cerr << "CALCULATED: " << (topBottom ? "B" : "T") << blockType << "(" << farRow
793 // << "," << farMajor << "." << (width - 1) << "): "
794 // << mColumnDefs[mDeviceInfo.getColumnTypes()[col + baseCol]].getName() << std::endl;
795  if(width > 0) {
796  farMajor++;
797  blockUsed = true;
798  }
799  frameCount += width;
800  // indexes for Bitstream Columns, only stores non-empty tile types
801  if(mDeviceInfo.getColumnTypes()[realCol] != eColumnTypeEmpty &&
802  mDeviceInfo.getColumnTypes()[realCol] != eColumnTypeInt) {
803  mBitColumnToXdlColumn[bitColumnCount] = xdlColumnCount;
804  bitColumnCount++;
805  bitIndex += width;
806  mBitColumnIndexes[i].push_back(bitIndex);
807  if(blockUsed && col == finalColumn) {
808  bitIndex += getRowPadFrames();
809  }
810  }
811  // indexes for XDL Columns
812  xdlIndex += width;
813  mXdlColumnIndexes[i].push_back(xdlIndex);
814  xdlColumnCount++;
815  if(blockUsed && col == finalColumn) {
816  xdlIndex += getRowPadFrames();
817  }
818  }
819  baseCol += mDeviceInfo.getColCount();
820  // account for two pad frames after each frame row
821  if(blockUsed) {
822  frameIndex += getRowPadFrames();
823  blockFrameIndexBounds += getRowPadFrames();
824  }
825  if(debug) std::cout << "Last frame index: [" << i << ", " << frameIndex
826  << "]" << std::endl;
827  }
828  }
829  // stores frame index bounds for each block type
830  mBlockFrameIndexBounds[i] = blockFrameIndexBounds;
831  if(debug) std::cout << "***Block frame index bounds: " << mBlockFrameIndexBounds[i]
832  << std::endl;
833  }
834  // test to check proper indexing
835  if(debug) {
836  for(uint32_t i = 0; i < eFarBlockTypeCount; i++) {
837  for(uint32_t j = 0; j < mBitColumnIndexes[i].size(); j++)
838  std::cout << "Bit Value at index: (" << i << ", " << j << ") : "
839  << mBitColumnIndexes[i][j] << std::endl;
840  for(uint32_t k = 0; k < mXdlColumnIndexes[i].size(); k++)
841  std::cout << "Xdl Value at index: (" << i << ", " << k << ") : "
842  << mXdlColumnIndexes[i][k] << std::endl;
843  }
844  }
845  }
846 
847  VirtexPacketVector Virtex7::generateFullBitstreamPrefix(void) {
848  // 0000005d: DUMMY
849  // 00000061: DUMMY
850  // 00000065: DUMMY
851  // 00000069: DUMMY
852  // 0000006d: DUMMY
853  // 00000071: DUMMY
854  // 00000075: DUMMY
855  // 00000079: DUMMY
856  // 0000007d: BUS WIDTH SYNC
857  // 00000081: BUS WIDTH DETECT
858  // 00000085: DUMMY
859  // 00000089: DUMMY
860  // 0000008d: SYNC
861  // 00000091: NOP x 1
862  // 00000095: TYPE1 WRITE TIMER: 00000000 (TimerForUser:Disabled, TimerForConfig:Disabled)
863  // 0000009d: TYPE1 WRITE WBSTAR: 00000000 (RevisionSelectTristate:Disabled,
864  // NextRevisionSelect:00)
865  // 000000a5: TYPE1 WRITE CMD NULL
866  // 000000ad: NOP x 1
867  // 000000b1: TYPE1 WRITE CMD RCRC
868  // 000000b9: NOP x 2
869  // 000000c1: TYPE1 WRITE [UNKNOWN REG 19]: 00000000
870  // 000000c9: TYPE1 WRITE COR0: 02003fe5 (DONE_status:DonePin, DonePipe:Yes, DriveDone:No,
871  // Capture:Continuous, ConfigRate:[UNKNOWN 0], StartupClk:Cclk, DONE_cycle:4,
872  // Match_cycle:NoWait, LCK_cycle:No Wait, GTS_cycle:5, GWE_cycle:6)
873  // 000000d1: TYPE1 WRITE COR1: 00000000 (PersistDeassertAtDesynch:Disabled,
874  // ActionReadbackCRC:Continue, InitAsCRCErrorPin:Disabled,
875  // ContinuousReadbackCRC:Enabled, BPI_1st_read_cycle:1, BPI_page_size:1)
876  // 000000d9: TYPE1 WRITE IDCODE: 03651093
877  // 000000e1: TYPE1 WRITE CMD SWITCH
878  // 000000e9: NOP x 1
879  // 000000ed: TYPE1 WRITE MASK: 00000401 (EFUSE_key:Protected, ICAP_sel:Protected,
880  // OverTempPowerDown:Protected, GLUTMASK:Protected, FARSRC:Protected,
881  // Encrypt:Protected, Security:Protected, Persist:Protected,
882  // GTS_USER_B:Writable)
883  // 000000f5: TYPE1 WRITE CTL0: 00000501 (EFUSE_key:No, ICAP_sel:Top,
884  // OverTempPowerDown:Disable, GLUTMASK:Dynamic, FARSRC:FAR, Encrypt:No,
885  // Security:None, Persist:No, GTS_USER_B:IoActive)
886  // 000000fd: TYPE1 WRITE MASK: 00000000 ()
887  // 00000105: TYPE1 WRITE CTL1: 00000000 ()
888  // 0000010d: NOP x 8
889 
890  // declare the packet vector and define a NOP packet
891  typedef VirtexFrame::word_t word_t;
892  VirtexPacketVector packets;
893  VirtexPacket nop(VirtexPacket::makeHeader(ePacketType1, eOpcodeNOP, 0, 0));
894  VirtexPacket dummy(eSynchronizationDummy);
895  // dummy words
896  packets.insert(packets.end(), 8, dummy);
897  // bus width detect
898  packets.push_back(VirtexPacket(eSynchronizationBusWidthSync));
899  packets.push_back(VirtexPacket(eSynchronizationBusWidthDetect));
900  packets.push_back(dummy);
901  packets.push_back(dummy);
902  // sync
903  packets.push_back(VirtexPacket(eSynchronizationSync));
904  packets.push_back(nop);
905  // watchdog timer
906  packets.push_back(VirtexPacket::makeType1Write(eRegisterTIMER, 0));
907  // warm boot register
908  packets.push_back(VirtexPacket::makeType1Write(eRegisterWBSTAR, 0));
909  // NULL command
910  packets.push_back(VirtexPacket::makeType1Write(eRegisterCMD, eCommandNULL));
911  packets.push_back(nop);
912  // reset CRC command
913  packets.push_back(VirtexPacket::makeType1Write(eRegisterCMD, eCommandRCRC));
914  packets.push_back(nop);
915  packets.push_back(nop);
916  // undocumented register 19
917  packets.push_back(VirtexPacket::makeType1Write(19, 0));
918  // configuration options register 0
919  packets.push_back(VirtexPacket::makeType1Write(eRegisterCOR0,
920  makeSubfield(eRegisterCOR0, "DONE_status", "DonePin") |
921  makeSubfield(eRegisterCOR0, "DonePipe", "Yes") |
922  makeSubfield(eRegisterCOR0, "DriveDone", "No") |
923  makeSubfield(eRegisterCOR0, "Capture", "Continuous") |
924  makeSubfield(eRegisterCOR0, "ConfigRate", "[UNKNOWN 0]") |
925  makeSubfield(eRegisterCOR0, "StartupClk", "Cclk") |
926  makeSubfield(eRegisterCOR0, "DONE_cycle", "4") |
927  makeSubfield(eRegisterCOR0, "Match_cycle", "NoWait") |
928  makeSubfield(eRegisterCOR0, "LCK_cycle", "NoWait") |
929  makeSubfield(eRegisterCOR0, "GTS_cycle", "5") |
930  makeSubfield(eRegisterCOR0, "GWE_cycle", "6") |
931  0));
932  // configuration options register 1
933  packets.push_back(VirtexPacket::makeType1Write(eRegisterCOR1,
934  makeSubfield(eRegisterCOR1, "PersistDeassertAtDesynch", "Disabled") |
935  makeSubfield(eRegisterCOR1, "ActionReadbackCRC", "Continue") |
936  makeSubfield(eRegisterCOR1, "InitAsCRCErrorPin", "Disabled") |
937  makeSubfield(eRegisterCOR1, "ContinuousReadbackCRC", "Enabled") |
938  makeSubfield(eRegisterCOR1, "BPI_1st_read_cycle", "1") |
939  makeSubfield(eRegisterCOR1, "BPI_page_size", "1") |
940  0));
941  // write the ID code
942  packets.push_back(VirtexPacket::makeType1Write(eRegisterIDCODE, 0x00000000));
943  // clock and rate switch command
944  packets.push_back(VirtexPacket::makeType1Write(eRegisterCMD, eCommandSWITCH));
945  packets.push_back(nop);
946  // control register 0 mask
947  packets.push_back(VirtexPacket::makeType1Write(eRegisterMASK,
948  makeSubfield(eRegisterMASK, "EFUSE_key", "Protected") |
949  makeSubfield(eRegisterMASK, "ICAP_sel", "Protected") |
950  makeSubfield(eRegisterMASK, "OverTempPowerDown", "Protected") |
951  makeSubfield(eRegisterMASK, "GLUTMASK", "Protected") |
952  makeSubfield(eRegisterMASK, "FARSRC", "Protected") |
953  makeSubfield(eRegisterMASK, "Encrypt", "Protected") |
954  makeSubfield(eRegisterMASK, "Security", "Protected") |
955  makeSubfield(eRegisterMASK, "Persist", "Protected") |
956  makeSubfield(eRegisterMASK, "GTS_USER_B", "Writable") |
957  0));
958  // control register 0
959  packets.push_back(VirtexPacket::makeType1Write(eRegisterCTL0,
960  makeSubfield(eRegisterCTL0, "EFUSE_key", "NO") |
961  makeSubfield(eRegisterCTL0, "ICAP_sel", "Top") |
962  makeSubfield(eRegisterCTL0, "OverTempPowerDown", "Disable") |
963  makeSubfield(eRegisterCTL0, "GLUTMASK", "Dynamic") |
964  makeSubfield(eRegisterCTL0, "FARSRC", "FAR") |
965  makeSubfield(eRegisterCTL0, "Encrypt", "No") |
966  makeSubfield(eRegisterCTL0, "Security", "None") |
967  makeSubfield(eRegisterCTL0, "Persist", "No") |
968  makeSubfield(eRegisterCTL0, "GTS_USER_B", "IoActive") |
969  0));
970  // control register 1 mask
971  packets.push_back(VirtexPacket::makeType1Write(eRegisterMASK, 0));
972  // control register 1
973  packets.push_back(VirtexPacket::makeType1Write(eRegisterCTL1, 0));
974  // more NOPs
975  packets.insert(packets.end(), 8, nop);
976  // return the packet vector
977  return packets;
978  }
979 
980  VirtexPacketVector Virtex7::generateFullBitstreamSuffix(void) {
981  // 00ae95cd: TYPE1 WRITE CRC: 9f18b580
982  // 00ae95d1: NOP x 2
983  // 00ae95d9: TYPE1 WRITE CMD GRESTORE
984  // 00ae95e1: NOP x 1
985  // 00ae95e5: TYPE1 WRITE CMD DGHIGH/LFRM
986  // 00ae95ed: NOP x 100
987  // 00ae977d: TYPE1 WRITE CMD START
988  // 00ae9785: NOP x 1
989  // 00ae9789: TYPE1 WRITE FAR: 03be0000
990  // 00ae9791: TYPE1 WRITE MASK: 00000501 (EFUSE_key:Protected, ICAP_sel:Protected,
991  // OverTempPowerDown:Protected, GLUTMASK:Writable, FARSRC:Protected,
992  // Encrypt:Protected, Security:Protected, Persist:Protected,
993  // GTS_USER_B:Writable)
994  // 00ae9799: TYPE1 WRITE CTL0: 00000501 (EFUSE_key:No, ICAP_sel:Top,
995  // OverTempPowerDown:Disable, GLUTMASK:Dynamic, FARSRC:FAR, Encrypt:No,
996  // Security:None, Persist:No, GTS_USER_B:IoActive)
997  // 00ae97a1: TYPE1 WRITE CRC: e3ad7ea5
998  // 00ae97a9: NOP x 2
999  // 00ae97b1: TYPE1 WRITE CMD DESYNCH
1000  // 00ae97b9: NOP x 400
1001 
1002  // declare the packet vector and define a NOP packet
1003  typedef VirtexFrame::word_t word_t;
1004  VirtexPacketVector packets;
1005  VirtexPacket nop(VirtexPacket::makeHeader(ePacketType1, eOpcodeNOP, 0, 0));
1006  // write a placeholder CRC value
1007  packets.push_back(VirtexPacket::makeType1Write(eRegisterCRC, 0));
1008  packets.push_back(nop);
1009  packets.push_back(nop);
1010  // restore command
1011  packets.push_back(VirtexPacket::makeType1Write(eRegisterCMD, eCommandGRESTORE));
1012  packets.push_back(nop);
1013  // last frame command
1014  packets.push_back(VirtexPacket::makeType1Write(eRegisterCMD, eCommandLFRM));
1015  packets.insert(packets.end(), 100, nop);
1016  // start command
1017  packets.push_back(VirtexPacket::makeType1Write(eRegisterCMD, eCommandSTART));
1018  packets.push_back(nop);
1019  // frame address register
1020  packets.push_back(VirtexPacket::makeType1Write(eRegisterFAR,
1021  eFarMaskBlockType | eFarMaskRow)); // is this what the configuration controller wants?
1022  // control register 0 mask
1023  packets.push_back(VirtexPacket::makeType1Write(eRegisterMASK,
1024  makeSubfield(eRegisterMASK, "EFUSE_key", "Protected") |
1025  makeSubfield(eRegisterMASK, "ICAP_sel", "Protected") |
1026  makeSubfield(eRegisterMASK, "OverTempPowerDown", "Protected") |
1027  makeSubfield(eRegisterMASK, "GLUTMASK", "Protected") |
1028  makeSubfield(eRegisterMASK, "FARSRC", "Protected") |
1029  makeSubfield(eRegisterMASK, "Encrypt", "Protected") |
1030  makeSubfield(eRegisterMASK, "Security", "Protected") |
1031  makeSubfield(eRegisterMASK, "Persist", "Protected") |
1032  makeSubfield(eRegisterMASK, "GTS_USER_B", "Writable") |
1033  0));
1034  // control register 0
1035  packets.push_back(VirtexPacket::makeType1Write(eRegisterCTL0,
1036  makeSubfield(eRegisterCTL0, "EFUSE_key", "NO") |
1037  makeSubfield(eRegisterCTL0, "ICAP_sel", "Top") |
1038  makeSubfield(eRegisterCTL0, "OverTempPowerDown", "Disable") |
1039  makeSubfield(eRegisterCTL0, "GLUTMASK", "Dynamic") |
1040  makeSubfield(eRegisterCTL0, "FARSRC", "FAR") |
1041  makeSubfield(eRegisterCTL0, "Encrypt", "No") |
1042  makeSubfield(eRegisterCTL0, "Security", "None") |
1043  makeSubfield(eRegisterCTL0, "Persist", "No") |
1044  makeSubfield(eRegisterCTL0, "GTS_USER_B", "IoActive") |
1045  0));
1046  // write the CRC value
1047  packets.push_back(VirtexPacket::makeType1Write(eRegisterCRC, 0x00000000));
1048  packets.push_back(nop);
1049  packets.push_back(nop);
1050  // desynch command
1051  packets.push_back(VirtexPacket::makeType1Write(eRegisterCMD, eCommandDESYNCH));
1052  packets.insert(packets.end(), 400, nop);
1053  // return the packet vector
1054  return packets;
1055  }
1056 
1057  VirtexPacketVector Virtex7::generatePartialBitstreamPrefix(EBitstreamType inBitstreamType) {
1058  // Packets marked S pertain to shutdown bitstreams only
1059  // 0000005d: DUMMY
1060  // 00000061: DUMMY
1061  // 00000065: DUMMY
1062  // 00000069: DUMMY
1063  // 0000006d: DUMMY
1064  // 00000071: DUMMY
1065  // 00000075: DUMMY
1066  // 00000079: DUMMY
1067  // 0000007d: BUS WIDTH SYNC
1068  // 00000081: BUS WIDTH DETECT
1069  // 00000085: DUMMY
1070  // 00000089: DUMMY
1071  // 0000008d: SYNC
1072  // 00000091: NOP x 1
1073  // 00000095: TYPE1 WRITE CMD RCRC
1074  // 0000009d: NOP x 2
1075  // 000000a5: TYPE1 WRITE IDCODE: 03651093
1076  // S 000000ad: TYPE1 WRITE COR0: 02003fe5 (DONE_status:DonePin, DonePipe:Yes,
1077  // DriveDone:No, Capture:Continuous, ConfigRate:[UNKNOWN 0],
1078  // StartupClk:Cclk, DONE_cycle:4, Match_cycle:NoWait, LCK_cycle:No Wait,
1079  // GTS_cycle:5, GWE_cycle:6)
1080  // S 000000b5: TYPE1 WRITE CMD SHUTDOWN
1081  // S 000000bd: NOP x 1
1082  // S 000000c1: TYPE1 WRITE CRC: 6f322c8f
1083  // S 000000c9: NOP x 4
1084  // S 000000d9: TYPE1 WRITE CMD AGHIGH
1085  // S 000000e1: NOP x 1
1086  // 000000e5: TYPE1 WRITE CMD NULL
1087 
1088  // declare the packet vector and define a NOP packet
1089  typedef VirtexFrame::word_t word_t;
1090  VirtexPacketVector packets;
1091  VirtexPacket nop(VirtexPacket::makeHeader(ePacketType1, eOpcodeNOP, 0, 0));
1092  VirtexPacket dummy(eSynchronizationDummy);
1093  // dummy words
1094  packets.insert(packets.end(), 8, dummy);
1095  // bus width detect
1096  packets.push_back(VirtexPacket(eSynchronizationBusWidthSync));
1097  packets.push_back(VirtexPacket(eSynchronizationBusWidthDetect));
1098  packets.push_back(dummy);
1099  packets.push_back(dummy);
1100  // sync
1101  packets.push_back(VirtexPacket(eSynchronizationSync));
1102  packets.push_back(nop);
1103  // reset CRC command
1104  packets.push_back(VirtexPacket::makeType1Write(eRegisterCMD, eCommandRCRC));
1105  packets.push_back(nop);
1106  packets.push_back(nop);
1107  // write the ID code
1108  packets.push_back(VirtexPacket::makeType1Write(eRegisterIDCODE, 0x00000000));
1109  // extra for shutdown bitstreams
1110  if(inBitstreamType == eBitstreamTypePartialShutdown) {
1111  // configuration options register 0
1112  packets.push_back(VirtexPacket::makeType1Write(eRegisterCOR0,
1113  makeSubfield(eRegisterCOR0, "DONE_status", "DonePin") |
1114  makeSubfield(eRegisterCOR0, "DonePipe", "Yes") |
1115  makeSubfield(eRegisterCOR0, "DriveDone", "No") |
1116  makeSubfield(eRegisterCOR0, "Capture", "Continuous") |
1117  makeSubfield(eRegisterCOR0, "ConfigRate", "[UNKNOWN 0]") |
1118  makeSubfield(eRegisterCOR0, "StartupClk", "Cclk") |
1119  makeSubfield(eRegisterCOR0, "DONE_cycle", "4") |
1120  makeSubfield(eRegisterCOR0, "Match_cycle", "NoWait") |
1121  makeSubfield(eRegisterCOR0, "LCK_cycle", "NoWait") |
1122  makeSubfield(eRegisterCOR0, "GTS_cycle", "5") |
1123  makeSubfield(eRegisterCOR0, "GWE_cycle", "6") |
1124  0));
1125  // shutdown command
1126  packets.push_back(VirtexPacket::makeType1Write(eRegisterCMD, eCommandSHUTDOWN));
1127  packets.push_back(nop);
1128  // write the CRC value
1129  packets.push_back(VirtexPacket::makeType1Write(eRegisterCRC, 0x00000000));
1130  packets.insert(packets.end(), 4, nop);
1131  // aghigh command
1132  packets.push_back(VirtexPacket::makeType1Write(eRegisterCMD, eCommandAGHIGH));
1133  packets.push_back(nop);
1134  }
1135  // null command
1136  packets.push_back(VirtexPacket::makeType1Write(eRegisterCMD, eCommandNULL));
1137  // return the packet vector
1138  return packets;
1139  }
1140 
1141  VirtexPacketVector Virtex7::generatePartialBitstreamSuffix(EBitstreamType inBitstreamType) {
1142  // Packets marked S pertain to shutdown bitstreams only
1143  // S 000008ed: TYPE1 WRITE CMD GRESTORE
1144  // S 000008f5: NOP x 1
1145  // 000008f9: TYPE1 WRITE CMD DGHIGH/LFRM
1146  // 00000901: NOP x 100
1147  // S 00000a91: TYPE1 WRITE CMD GRESTORE
1148  // S 00000a99: NOP x 1
1149  // S 00000a9d: TYPE1 WRITE CMD START
1150  // S 00000aa5: NOP x 1
1151  // 00000aa9: TYPE1 WRITE FAR: 03be0000
1152  // 00000ab1: TYPE1 WRITE CRC: a658dd48
1153  // 00000ab9: TYPE1 WRITE CMD DESYNCH
1154  // 00000ac1: NOP x 16
1155 
1156  // declare the packet vector and define a NOP packet
1157  typedef VirtexFrame::word_t word_t;
1158  VirtexPacketVector packets;
1159  VirtexPacket nop(VirtexPacket::makeHeader(ePacketType1, eOpcodeNOP, 0, 0));
1160  // extra for shutdown bitstreams
1161  if(inBitstreamType == eBitstreamTypePartialShutdown) {
1162  // restore command
1163  packets.push_back(VirtexPacket::makeType1Write(eRegisterCMD, eCommandGRESTORE));
1164  packets.push_back(nop);
1165  }
1166  // last frame command
1167  packets.push_back(VirtexPacket::makeType1Write(eRegisterCMD, eCommandLFRM));
1168  packets.insert(packets.end(), 100, nop);
1169  // extra for shutdown bitstreams
1170  if(inBitstreamType == eBitstreamTypePartialShutdown) {
1171  // restore command
1172  packets.push_back(VirtexPacket::makeType1Write(eRegisterCMD, eCommandGRESTORE));
1173  packets.push_back(nop);
1174  // start command
1175  packets.push_back(VirtexPacket::makeType1Write(eRegisterCMD, eCommandSTART));
1176  packets.push_back(nop);
1177  }
1178  // frame address register
1179  packets.push_back(VirtexPacket::makeType1Write(eRegisterFAR,
1180  eFarMaskBlockType | eFarMaskRow)); // is this what the configuration controller wants?
1181  // write the CRC value
1182  packets.push_back(VirtexPacket::makeType1Write(eRegisterCRC, 0x00000000));
1183  // desynch command
1184  packets.push_back(VirtexPacket::makeType1Write(eRegisterCMD, eCommandDESYNCH));
1185  packets.insert(packets.end(), 16, nop);
1186  // return the packet vector
1187  return packets;
1188  }
1189 
1190  void Virtex7::initializeFullFrameBlocks(void) {
1191  boost::shared_array<uint32_t> frameWords;
1192  // walk the bitstream and extract all frames
1193  Virtex7::iterator p = begin();
1194  Virtex7::iterator e = end();
1195  while(p < e) {
1196  const VirtexPacket& packet = *p++;
1197  if(packet.isType2() && packet.isWrite())
1198  frameWords = packet.getWords();
1199  }
1200  uint32_t index = 0;
1201  for(uint32_t i = 0; i < Bitstream::eBlockTypeCount; i++) {
1202  // all frames of block type are extracted
1203  for(uint32_t j = 0; j < mBlockFrameIndexBounds[i]; j++) {
1204  mFrameBlocks.mBlock[i].push_back(VirtexFrameSet::FrameSharedPtr
1205  (new VirtexFrame(getFrameLength(), &frameWords[index])));
1206  index += getFrameLength();
1207  }
1208  }
1209  }
1210 
1211  void Virtex7::updateFullFrameBlocks(void) {
1212  /// \todo If the packet size differs from the frame data size, we need to replace the
1213  /// entire packet.
1214  uint32_t frameLength = getFrameLength();
1215  typedef boost::shared_array<uint32_t> WordSharedArray;
1216  // walk the bitstream and find the (full) FDRI write packet
1217  Virtex7::iterator p = begin();
1218  Virtex7::iterator e = end();
1219  while(p < e) {
1220  const VirtexPacket& packet = *p++;
1221  if(packet.isType2() && packet.isWrite()) {
1222  WordSharedArray words = packet.getWords();
1223  uint32_t* ptr = words.get();
1224  for(uint32_t block = 0; block < 8; block++) {
1225  for(uint32_t frame = 0; frame < mBlockFrameIndexBounds[block]; frame++) {
1226  const VirtexFrameBlocks::word_t* words
1227  = mFrameBlocks.mBlock[block][frame]->getWords();
1228  for(uint32_t index = 0; index < frameLength; index++) *ptr++ = *words++;
1229  }
1230  }
1231  }
1232  }
1233  }
1234 
1235  VirtexFrameBlocks Virtex7::getBitstreamFrames(EFarTopBottom inTopBottom, uint32_t inFrameRow,
1236  uint32_t inBitCol, uint32_t inBlockCount) {
1237  return getXdlFrames(inFrameRow + (inTopBottom == eFarBottom ? (mTopRowCount) : 0),
1238  mBitColumnToXdlColumn[inBitCol], inBlockCount);
1239  }
1240 
1241  VirtexFrameBlocks Virtex7::getBitstreamFrames(uint32_t inBitRow, uint32_t inBitCol,
1242  uint32_t& outBeginBit, uint32_t& outEndBit, uint32_t inBlockCount) {
1243  return getXdlFrames(inBitRow, mBitColumnToXdlColumn[inBitCol], outBeginBit, outEndBit,
1244  inBlockCount);
1245  }
1246 
1247  VirtexFrameBlocks Virtex7::getBitstreamFrames(uint32_t inSerialFrameRow, uint32_t inBitCol,
1248  uint32_t inBlockCount) {
1249  return getXdlFrames(inSerialFrameRow, mBitColumnToXdlColumn[inBitCol], inBlockCount);
1250  }
1251 
1252  VirtexFrameBlocks Virtex7::getXdlFrames(uint32_t inXdlRow, uint32_t inXdlCol,
1253  uint32_t& outBeginBit, uint32_t& outEndBit, uint32_t inBlockCount) {
1254 
1255  // look up the frame row designator for this XDL row
1256  FrameRowDesignator designator = mXdlRowToFrameRowDesignator[inXdlRow];
1257 
1258  // by default we have no bit position information
1259  outBeginBit = outEndBit = 0;
1260 
1261  // look up the relative XDL row
1262  uint32_t relativeXdlRow = inXdlRow - designator.mXdlBaseRow;
1263  //std::cout << "inXdlRow: " << inXdlRow << std::endl;
1264  //std::cout << "inXdlCol: " << inXdlCol << std::endl;
1265  //std::cout << " designator.mTopBottom: " << designator.mTopBottom << std::endl;
1266  //std::cout << " designator.mFrameRow: " << designator.mFrameRow << std::endl;
1267  //std::cout << " designator.mXdlBaseRow: " << designator.mXdlBaseRow << std::endl;
1268  //std::cout << " designator.mColumnVectorBase: " << designator.mColumnVectorBase
1269  // << std::endl;
1270 
1271  // provide bit information for the columns that we know
1272  uint32_t index = relativeXdlRow;
1273  uint32_t columnVectorBase = designator.mColumnVectorBase;
1274  //std::cout << " relativeXdlRow: " << relativeXdlRow << std::endl;
1275  //std::cout << " mDeviceInfo.getColumnTypes()[inXdlCol]: "
1276  // << mDeviceInfo.getColumnTypes()[inXdlCol + columnVectorBase] << std::endl;
1277  switch(mDeviceInfo.getColumnTypes()[inXdlCol + columnVectorBase]) {
1278  case eColumnTypeClb:
1279  case eColumnTypeInt:
1280  if(index == 0 || index == 26) break; // these tiles have no bits
1281  index--; // tile 0 has no bits
1282  outBeginBit = index * 64; // regular tiles are 64 bits long
1283  outEndBit = outBeginBit + 64;
1284  if(index > 26) {
1285  outBeginBit -= 32; // the clock word is 32 bits long
1286  outEndBit -= 32; // the clock word is 32 bits long
1287  }
1288  break;
1289  case eColumnTypeDsp:
1290  case eColumnTypeBram:
1291  if(index != 5 && index != 10 && index != 15 && index != 20 && index != 25
1292  && index != 31 && index != 36 && index != 41 && index != 46 && index != 51) break;
1293  index -= 5;
1294  outBeginBit = index * 64; // regular tiles are 64 bits long
1295  outEndBit = outBeginBit + 320;
1296  if(index > 25) {
1297  outBeginBit -= 32; // the clock word is 32 bits long
1298  outEndBit -= 32; // the clock word is 32 bits long
1299  }
1300  break;
1301  default:
1302  break;
1303  }
1304 
1305  // invoke the function that really does the work
1306  return getXdlFrames(designator.mFrameRow, designator.mColumnVectorBase, inXdlCol);
1307  }
1308 
1309  VirtexFrameBlocks Virtex7::getXdlFrames(uint32_t inSerialFrameRow,
1310  uint32_t inColumnVectorBase, uint32_t inXdlCol, uint32_t inBlockCount) {
1311  if(inSerialFrameRow > getFrameRowCount()) return VirtexFrameBlocks();
1312 
1313  // index and extract frames
1314  int32_t xdlColumnIndex[inBlockCount];
1315  int32_t xdlColumnBound[inBlockCount];
1316  for(uint32_t i = 0; i < inBlockCount; i++) {
1317  // column index of given frame index
1318  xdlColumnIndex[i] = mXdlColumnIndexes[i][inColumnVectorBase + inXdlCol];
1319  // frame bounds for given column type
1320  uint32_t col = inColumnVectorBase + inXdlCol;
1321  xdlColumnBound[i] = mColumnDefs[mDeviceInfo.getColumnTypes()[col]][i];
1322  //std::cout << " i: " << i << std::endl;
1323  //std::cout << " length: " << mXdlColumnIndexes[i].size() << std::endl;
1324  //std::cout << " xdlColumnBound[i]: " << xdlColumnBound[i] << std::endl;
1325  //std::cout << " xdlColumnIndex[i]: " << xdlColumnIndex[i] << std::endl;
1326  //std::cout << " col: " << col << std::endl;
1327  }
1328  // extract the tile frames for the specified FAR
1329  VirtexFrameBlocks frameBlocks;
1330  for(uint32_t i = 0; i < inBlockCount; i++) {
1331  int startIndex = xdlColumnIndex[i];
1332  for(int j = 0; j < xdlColumnBound[i]; j++) {
1333  frameBlocks.mBlock[i].push_back(mFrameBlocks.mBlock[i][startIndex+j]);
1334  if(!xdlColumnBound[i]) continue;
1335  int offset = i > 0 ? mXdlColumnIndexes[i-1].back() + 2 : 0;
1336  std::cout << "Virtex7::getXdlFrames(): pushing mBlock[" << i << "]["
1337  << (startIndex + offset + j) << "]: "
1338  << mFrameIndexToAddress[startIndex + offset + j] << std::endl;
1339  //std::cout << " pushing mBlock[" << i << "][" << (startIndex + offset) << "]-["
1340  // << (startIndex + offset + xdlColumnBound[i] - 1) << "]" << ": "
1341  // << mFrameIndexToAddress[startIndex + offset] << " - "
1342  // << mFrameIndexToAddress[startIndex + offset + xdlColumnBound[i] - 1]
1343  // << std::endl;
1344  }
1345  }
1346  return frameBlocks;
1347  }
1348 
1349  uint32_t Virtex7::getPrimaryXdlColumn(uint32_t inXdlRow, uint32_t inXdlCol) {
1350  // INT columns "belong" with their corresponding primary column in the bitstream, so if the
1351  // caller hands us an INT column, we look for the next primary column;
1352  // if the caller passes in a primary column, we return it as is
1353  const ColumnTypeVector& columns = mDeviceInfo.getColumnTypes();
1354  // look up the column vector base index for this XDL row
1355  uint32_t columnVectorBase = mXdlRowToFrameRowDesignator[inXdlRow].mColumnVectorBase;
1356  // determine the bounds for the current column
1357  uint32_t col = inXdlCol;
1358  ColumnTypeVector::const_iterator b = columnVectorBase + columns.begin();
1359  ColumnTypeVector::const_iterator p = columnVectorBase + columns.begin() + col;
1360  ColumnTypeVector::const_iterator e = columnVectorBase + columns.end();
1361  // if this is anything other than an INT_L or INT_R column, we return it unchanged
1362  if(*p != eColumnTypeInt) return inXdlCol;
1363  // if column to the left is also INT, then this is an INT_R, otherwise it's an INT_L
1364  if(p > b && *(p-1) == eColumnTypeInt) {
1365  // this is an INT_R
1366  while(p < e) {
1367  col++; p++; if(p == e) break;
1368  if(*p != eColumnTypeEmpty && *p != eColumnTypeVframe && *p != eColumnTypeCfg
1369  && *p != eColumnTypeClock) return col;
1370  }
1371  } else {
1372  // this is an INT_L
1373  while(p > b) {
1374  col--; p--;
1375  if(*p != eColumnTypeEmpty && *p != eColumnTypeVframe && *p != eColumnTypeCfg
1376  && *p != eColumnTypeClock) return col;
1377  }
1378  }
1379  // we shouldn't get here, but if we do, the best thing is to return the original column
1380  return inXdlCol;
1381  }
1382 
1383 }// namespace bitstream
1384 }// namespace torc
1385 
1386 #if 0
1387  void Virtex7::readFramePackets(void) {
1388  boost::shared_array<uint32_t> frameWords;
1389  // precalculate the start indexes of all blocks, and create all possible frames
1390  uint32_t frameStart[eBlockTypeCount + 1];
1391  frameStart[0] = 0;
1392  VirtexFrame frame(eFrameLength);
1393  for(int i = 0; i < eBlockTypeCount; i++) {
1394  frameStart[i + 1] = frameStart[i] + mBlockFrameIndexBounds[i];
1395  // clear any existing frames
1396  mFrameBlocks.mBlock[i].clear();
1397  // populate the block with the correct number of empty frames
1398  for(uint32_t j = 0; j < mBlockFrameIndexBounds[i]; j++) {
1399  mFrameBlocks.mBlock[i].push_back(VirtexFrameSet::FrameSharedPtr
1400  (new VirtexFrame(getFrameLength())));
1401  mFrameBlocks.mBlock[i].back()->setUsed(false);
1402  }
1403  }
1404  // walk the bitstream and extract all frames
1405  const uint32_t frameLength = getFrameLength();
1406  uint32_t frameIndex = 0;
1407  FrameAddress frameAddress;
1408  ERegister lastAddress = ERegister();
1409  Virtex7::iterator p = begin();
1410  Virtex7::iterator e = end();
1411  while(p < e) {
1412  const VirtexPacket& packet = *p++;
1413  // process FAR write packets
1414  if(packet.isWrite() && packet.getAddress() == eRegisterFAR) {
1415  // extract the new frame address
1416  frameAddress = FrameAddress(packet[1]);
1417  // convert the frame address to the corresponding frame index
1418  FrameAddressToIndex::iterator ip = mFrameAddressToIndex.find(frameAddress);
1419  if(ip != mFrameAddressToIndex.end()) frameIndex = ip->second;
1420  }
1421  // process FDRI write packets
1422  else if(packet.isWrite()
1423  && (
1424  // this is a Type 2 packet and the prior Type 1 address was FDRI
1425  (packet.isType2() && lastAddress == eRegisterFDRI)
1426  ||
1427  // this is a non-empty Type 1 packet and its address is FDRI
1428  (packet.isType1() && packet.getAddress() == eRegisterFDRI
1429  && packet.getWordCount() > 0)
1430  )) {
1431  // determine the number of frames in the packet and look up the frame words
1432  const uint32_t numWords = packet.getWordCount();
1433  boost::shared_array<uint32_t> frameWords(packet.getWords());
1434  uint32_t position = 0;
1435  // iterate over every frame in the packet
1436  while(position + frameLength <= numWords) {
1437  // look up the current block type and the frame index into that block type
1438  EFarBlockType blockType = frameAddress.mBlockType;
1439  uint32_t index = frameIndex - frameStart[blockType];
1440  mFrameBlocks.mBlock[blockType][index] = VirtexFrameSet::FrameSharedPtr
1441  (new VirtexFrame(frameLength, &frameWords[position]));
1442  mFrameBlocks.mBlock[blockType][index]->setUsed();
1443  position += frameLength;
1444  frameIndex++;
1445  FrameIndexToAddress::iterator ap = mFrameIndexToAddress.find(frameIndex);
1446  if(ap != mFrameIndexToAddress.end()) frameAddress = ap->second;
1447  // sanity escape exit (which also breaks out of the higher level loop)
1448  if(position > numWords) {
1449  std::cerr << "Overflowed expected frame counts for device." << std::endl;
1450  break;
1451  }
1452  }
1453  if(frameIndex != frameStart[frameAddress.mBlockType + 1]) {
1454  // if we ended on a pad frame, where the current index has no corresponding
1455  // frame address, we need to advance to the next valid frame address
1456  if(mFrameIndexToAddress.find(frameIndex) == mFrameIndexToAddress.end())
1457  frameIndex++;
1458  if(mFrameIndexToAddress.find(frameIndex) == mFrameIndexToAddress.end())
1459  frameIndex++;
1460  // at this point we should again be on a valid frame
1461  FrameIndexToAddress::iterator ap = mFrameIndexToAddress.find(frameIndex);
1462  if(ap != mFrameIndexToAddress.end()) frameAddress = ap->second;
1463  else if(frameIndex == frameStart[frameAddress.mBlockType + 1]) /* at end */;
1464  else {
1465  std::cerr << "Failed to find the next valid frame address at the end of a "
1466  "packet." << std::endl;
1467  }
1468  }
1469  }
1470  // remember the last register address for Type 2 packets
1471  if(packet.isType1()) lastAddress = ERegister(packet.getAddress());
1472  // process MFWR write packets
1473  /// \todo
1474  }
1475  }
1476 
1477  VirtexPacketVector::iterator Virtex7::deleteFramePackets(void) {
1478  // walk the bitstream and look for frame packet boundaries
1479  // we begin with the first FAR write, and end before the first CRC write after an FDRI write
1480  Virtex7::iterator b = begin();
1481  Virtex7::iterator p = b;
1482  Virtex7::iterator e = end();
1483  Virtex7::iterator start = e;
1484  Virtex7::iterator stop = b;
1485  Virtex7::iterator fdri = b;
1486  while(p < e) {
1487  // look up the current packet
1488  const VirtexPacket& packet = *p;
1489  // start from the first FAR write
1490  if(start == e && packet.isWrite() && packet.getAddress() == eRegisterFAR) {
1491  start = p;
1492  }
1493  // remember the last FDRI write (including a trailing Type 2 write if present)
1494  if(packet.isWrite() && packet.getAddress() == eRegisterFDRI) {
1495  fdri = p;
1496  if((p+1)->isWrite() && (p+1)->isType2()) fdri++;
1497  }
1498  // stop on the first CRC after the last FDRI write
1499  // (Beware: the zero "address" of a Type 2 packet looks like the CRC register)
1500  if(stop < fdri && packet.isWrite() && packet.isType1()
1501  && packet.getAddress() == eRegisterCRC) {
1502  stop = p;
1503  }
1504  p++;
1505  }
1506  // look for anything unexpected
1507  p = start;
1508  while(p < stop) {
1509  // look up the current packet
1510  const VirtexPacket& packet = *p++;
1511  // abort if we find anything unexpected
1512  if(start < e && stop > b && !(
1513  packet.isNop() || (
1514  packet.isWrite() && (
1515  packet.getAddress() == eRegisterFAR ||
1516  packet.getAddress() == eRegisterLOUT ||
1517  packet.getAddress() == eRegisterFDRI ||
1518  packet.getAddress() == eRegisterCRC ||
1519  (packet.getAddress() == eRegisterCMD && packet[1] == eCommandWCFG)
1520  )))) {
1521  /// \todo Throw some meaningful exception
1522  std::cerr << "Unable to safely distinguish frame packets." << std::endl;
1523  return e;
1524  }
1525  }
1526  // if we found the expected FAR -> FDRI -> CRC structure, delete the frame packets
1527  if(start < stop && b < stop) {
1528  erase(start, stop);
1529  return start;
1530  }
1531  // if we didn't find frame packets or delete anything, return the end iterator
1532  return e;
1533  }
1534 
1535  VirtexPacketVector Virtex7::generateFullBitstreamPackets(void) {
1536 
1537  // declare the packet vector and define a NOP packet
1538  typedef VirtexFrame::word_t word_t;
1539  VirtexPacketVector packets;
1540  VirtexPacket nop(VirtexPacket::makeHeader(ePacketType1, eOpcodeNOP, 0, 0));
1541 
1542  // determine the total size of the frames to write
1543  size_t size = 0;
1544  for(int i = 0; i < eBlockTypeCount; i++)
1545  size += mBlockFrameIndexBounds[i] * getFrameLength();
1546  word_t* frameContents = new VirtexFrameSet::word_t[size];
1547  word_t* pos = frameContents;
1548  // gather the frames to write
1549  for(int i = 0; i < eBlockTypeCount; i++) {
1550  // look up the frame set for this block type
1551  VirtexFrameSet& frameSet = mFrameBlocks.mBlock[i];
1552  // iterate through the frames in the set and collect the frame words
1553  VirtexFrameSet::iterator p = frameSet.begin();
1554  VirtexFrameSet::iterator e = frameSet.end();
1555  while(p < e) {
1556  // look up the current frame
1557  VirtexFrameSharedPtr framePtr = *p++;
1558  // set up the pointers
1559  const word_t* wp = framePtr->getWords();
1560  const word_t* we = wp + framePtr->getLength();
1561  // and copy the frame words into the new memory
1562  if(wp) do { *pos++ = *wp++; } while(wp < we); // frames with words allocated
1563  else do { *pos++ = 0; wp++; } while(wp < we); // frames with no words allocated
1564  }
1565  }
1566  // write the starting frame address
1567  packets.push_back(VirtexPacket::makeType1Write(eRegisterFAR, 0));
1568  // write the write configuration register command
1569  packets.push_back(VirtexPacket::makeType1Write(eRegisterCMD, eCommandWCFG));
1570  packets.push_back(nop);
1571  // write 0 bytes to FDRI (in preparation for type 2 write packet)
1572  packets.push_back(VirtexPacket::makeNullType1Write(eRegisterFDRI));
1573  // write all frames to FDRI
1574  packets.push_back(VirtexPacket::makeType2Write(size, frameContents));
1575 
1576  // return the packet vector
1577  return packets;
1578  }
1579 
1580  VirtexPacketVector Virtex7::generatePartialBitstreamPackets(EFrameInclude inFrameInclusion) {
1581 
1582  // declare the packet vector and define a NOP packet
1583  typedef VirtexFrame::word_t word_t;
1584  VirtexPacketVector packets;
1585  VirtexPacket nop(VirtexPacket::makeHeader(ePacketType1, eOpcodeNOP, 0, 0));
1586 
1587  // write the starting frame address
1588  packets.push_back(VirtexPacket::makeType1Write(eRegisterFAR, 0));
1589  // write the write configuration register command
1590  packets.push_back(VirtexPacket::makeType1Write(eRegisterCMD, eCommandWCFG));
1591  packets.push_back(nop);
1592 
1593  // iterate through the frame blocks looking for groups of contiguous frames that are in use
1594  bool empty = true;
1595  uint32_t index = 0;
1596  uint32_t blockStart = 0;
1597  for(int i = 0; i < eBlockTypeCount; i++) {
1598  blockStart += index;
1599  index = 0;
1600  bool started = false;
1601  uint32_t startIndex = 0;
1602  // look up the frame set for this block type
1603  VirtexFrameSet& frameSet = mFrameBlocks.mBlock[i];
1604  // iterate through the frames in the set and add up their lengths
1605  VirtexFrameSet::iterator p = frameSet.begin();
1606  VirtexFrameSet::iterator e = frameSet.end();
1607  while(p < e) {
1608  // look up the current frame
1609  VirtexFrameSharedPtr framePtr = *p++;
1610  // determine whether the frame fits inclusion criteria
1611  // we include dirty frames, we include clean frames if permitted by the caller,
1612  // and if we are collecting frames and we encounter pad frames, we include them,
1613  // but we stop collecting if we reach the last frame in the set
1614  /// \todo mFrameIndexToAddress.size() is too short because excludes pad frames
1615  bool include = p < e
1616  && (
1617  framePtr->isDirty()
1618  || (inFrameInclusion == eFrameIncludeAllUsedFrames && framePtr->isUsed())
1619  || (started && blockStart + index < mFrameIndexToAddress.size() &&
1620  mFrameIndexToAddress.find(blockStart + index)
1621  == mFrameIndexToAddress.end())
1622  );
1623  // if we are accumulating frames and this frame doesn't meet the criteria, process
1624  // the collection of frames and stop collecting
1625  if((started && !include)) {
1626  started = false;
1627  uint32_t stopIndex = index + (p == e ? 1 : 0);
1628  uint32_t currentIndex = startIndex;
1629  // std::cerr << " stopped at: " << stopIndex << std::endl;
1630  // include two trailing pad frames if appropriate
1631  if(mFrameIndexToAddress.find(blockStart + stopIndex + 1)
1632  == mFrameIndexToAddress.end()) {
1633  stopIndex++;
1634  if(mFrameIndexToAddress.find(blockStart + stopIndex + 1)
1635  == mFrameIndexToAddress.end())
1636  stopIndex++;
1637  }
1638  // determine the length of the contiguous block
1639  size_t size = (stopIndex - startIndex) * getFrameLength();
1640  // allocate a word array
1641  word_t* frameContents = new VirtexFrameSet::word_t[size];
1642  word_t* pos = frameContents;
1643  while(currentIndex < stopIndex) {
1644  // look up the current frame
1645  VirtexFrameSharedPtr framePtr = mFrameBlocks.mBlock[i][currentIndex];
1646  // set up the pointers
1647  const word_t* wp = framePtr->getWords();
1648  const word_t* we = wp + framePtr->getLength();
1649  // and copy the frame words into the new memory
1650  if(wp) do { *pos++ = *wp++; } while(wp < we); // frames with words
1651  else do { *pos++ = 0; wp++; } while(wp < we); // frames with no words
1652  currentIndex++;
1653  }
1654  // write the starting frame address
1655  packets.push_back(VirtexPacket::makeType1Write(eRegisterFAR,
1656  mFrameIndexToAddress[blockStart + startIndex]));
1657  packets.push_back(nop);
1658  // if the size is more than 2048 words, we have to use a Type 2 write
1659  if(size > 2048) {
1660  // write 0 bytes to FDRI (in preparation for type 2 write packet)
1661  packets.push_back(VirtexPacket::makeNullType1Write(eRegisterFDRI));
1662  // write all frames to FDRI
1663  packets.push_back(VirtexPacket::makeType2Write(size, frameContents));
1664  } else {
1665  // write all frames to FDRI
1666  packets.push_back(VirtexPacket::makeType1Write(eRegisterFDRI, size,
1667  frameContents));
1668  }
1669  if(size) empty = false;
1670  // if we are not collecting, but we encounter a frame to include, begin collecting
1671  } else if(!started && include) {
1672  // std::cerr << " started at: " << index << std::endl;
1673  startIndex = index;
1674  started = true;
1675  }
1676  // increment the frame index
1677  index++;
1678  }
1679  }
1680 
1681  // if we generated no frame contents, discard the wrapper packets
1682  if(empty) packets.clear();
1683  // return the packet vector
1684  return packets;
1685  }
1686 #endif
torc::bitstream::Bitstream::mColumnDefs
ColumnDefVector mColumnDefs
Column type widths.
Definition: bitstream/Bitstream.hpp:249
torc::bitstream::xc7vx485t
DeviceInfo xc7vx485t
torc::bitstream::xc7v2000t
DeviceInfo xc7v2000t
torc::architecture::xilinx::TileRow
Encapsulation of a tile row in an unsigned 16-bit integer.
Definition: XilinxDatabaseTypes.hpp:87
torc::bitstream::xc7k420t
DeviceInfo xc7k420t
torc::bitstream::xc7vx415t
DeviceInfo xc7vx415t
torc::bitstream::Bitstream::mTileTypeNameToColumnType
TileTypeNameToColumnType mTileTypeNameToColumnType
Definition: bitstream/Bitstream.hpp:252
torc::bitstream::Virtex7::generatePartialBitstreamSuffix
virtual VirtexPacketVector generatePartialBitstreamSuffix(EBitstreamType inBitstreamType)
Return a packet vector with the partial bitstream suffix.
Definition: Virtex7.cpp:1141
torc::bitstream::xc7vx330t
DeviceInfo xc7vx330t
torc::bitstream::Virtex7::generateFullBitstreamSuffix
virtual VirtexPacketVector generateFullBitstreamSuffix(void)
Return a packet vector with the full bitstream suffix.
Definition: Virtex7.cpp:980
torc::bitstream::Virtex7::mBitColumnToXdlColumn
BitColumnToXdlColumn mBitColumnToXdlColumn
Map of bitstream column indexes to XDL column indexes.
Definition: Virtex7.hpp:423
torc::architecture::xilinx::TileCol
Encapsulation of a tile column in an unsigned 16-bit integer.
Definition: XilinxDatabaseTypes.hpp:94
torc::architecture::DDB
Device database, including complete wiring and logic support.
Definition: DDB.hpp:42
torc::architecture::Tiles::getTileTypeCount
TileTypeCount getTileTypeCount(void) const
Returns the tile type count for this device.
Definition: Tiles.hpp:151
torc::architecture::Tiles::getRowCount
TileRow getRowCount(void) const
Returns the row count for this device.
Definition: Tiles.hpp:153
torc::bitstream::xc7z010
DeviceInfo xc7z010
torc::bitstream::Virtex7::mXdlRowToFrameRowDesignator
FrameRowDesignatorVector mXdlRowToFrameRowDesignator
Vector of FrameRowDesignator entries for each XDL row.
Definition: Virtex7.hpp:427
torc::bitstream::xc7vh870t
DeviceInfo xc7vh870t
DirectoryTree.hpp
Header for the DirectoryTree class.
torc::bitstream::Virtex7::FrameRowDesignator
Frame row designator: top/bottom flag and row index.
Definition: Virtex7.hpp:364
torc::bitstream::Virtex7::readFramePackets
virtual void readFramePackets(void)
Read frame data into the frame blocks structure.
Definition: Virtex7.hpp:208
torc::bitstream::VirtexBitstream::mFrameBlocks
VirtexFrameBlocks mFrameBlocks
Input Frame blocks.
Definition: VirtexBitstream.hpp:65
torc::bitstream::Virtex7::initializeFrameMaps
virtual void initializeFrameMaps(void)
Initialize the maps between frame indexes and frame addresses. This is generally useful only for int...
Definition: Virtex7.cpp:710
torc::bitstream::VirtexPacket::makeNullType1Write
static VirtexPacket makeNullType1Write(uint32_t inAddress)
Construct a null type 1 write packet.
Definition: VirtexPacket.hpp:188
torc::bitstream::xc7k355t
DeviceInfo xc7k355t
torc::bitstream::Virtex7::generateFullBitstreamPrefix
virtual VirtexPacketVector generateFullBitstreamPrefix(void)
Return a packet vector with the full bitstream prefix.
Definition: Virtex7.cpp:847
torc::bitstream::DeviceInfo::getRowCount
uint16_t getRowCount(void) const
Returns the row count.
Definition: DeviceInfo.hpp:112
torc::bitstream::VirtexFrame
Frame< uint32_t > VirtexFrame
Virtex frame type.
Definition: Frame.hpp:104
torc::architecture::Tiles::getTileInfo
const TileInfo & getTileInfo(TileIndex inTileIndex) const
Returns the TileInfo object for the specified tile.
Definition: Tiles.hpp:137
torc::bitstream::xc7k410t
DeviceInfo xc7k410t
torc::bitstream::xc7z045
DeviceInfo xc7z045
torc::bitstream::Bitstream::mTileTypeIndexToColumnType
TileTypeIndexToColumnType mTileTypeIndexToColumnType
Definition: bitstream/Bitstream.hpp:255
torc::bitstream::DeviceInfo
Static device information class for Xilinx bitstreams. This class facilitates the creation of frame ...
Definition: DeviceInfo.hpp:75
torc::bitstream::Virtex7::getPrimaryXdlColumn
uint32_t getPrimaryXdlColumn(uint32_t inXdlRow, uint32_t inXdlCol)
Returns the primary column corresponding to the given tile. If the specified tile falls in an INT_L ...
Definition: Virtex7.cpp:1349
torc::bitstream::xc7z020
DeviceInfo xc7z020
torc::bitstream::Virtex7::uint32_t
boost::uint32_t uint32_t
Imported type name.
Definition: Virtex7.hpp:49
torc::bitstream::Virtex7::deleteFramePackets
virtual VirtexPacketVector::iterator deleteFramePackets(void)
Discard the existing frame packets and return an iterator to the start position.
Definition: Virtex7.hpp:229
torc::bitstream::VirtexFrameSet
FrameSet< VirtexFrame > VirtexFrameSet
Virtex frame set type.
Definition: FrameSet.hpp:73
torc::bitstream::Virtex7::getFrameLength
virtual uint32_t getFrameLength(void) const
Return the frame length for the current device.
Definition: Virtex7.hpp:304
torc::bitstream::DeviceInfo::getColCount
uint16_t getColCount(void) const
Returns the column count.
Definition: DeviceInfo.hpp:114
torc::bitstream::VirtexPacket::makeType2Write
static VirtexPacket makeType2Write(uint32_t inCount, uint32_t *inWords)
Construct a type 2 write packet.
Definition: VirtexPacket.hpp:202
torc::bitstream::Virtex7::generatePartialBitstreamPackets
virtual VirtexPacketVector generatePartialBitstreamPackets(EFrameInclude inFrameInclusion)
Return a packet vector with partial frame data.
Definition: Virtex7.hpp:242
VALUES
#define VALUES
Definition: Virtex7.cpp:51
torc::bitstream::Virtex7::sMASK0
static const Subfield sMASK0[]
Control Mask Register (MASK) subfields.
Definition: Virtex7.hpp:132
torc::architecture::Tiles::getTileCount
TileCount getTileCount(void) const
Returns the tile count for this device.
Definition: Tiles.hpp:149
torc::bitstream::Bitstream::mDevice
EDevice mDevice
Bitstream device enumeration.
Definition: bitstream/Bitstream.hpp:230
torc::bitstream::Virtex7::sSTAT
static const Subfield sSTAT[]
Status Register (STAT) subfields.
Definition: Virtex7.hpp:126
torc::bitstream::Virtex7::sBOOTSTS
static const Subfield sBOOTSTS[]
Boot History Status Register (BOOTSTS) subfields.
Definition: Virtex7.hpp:138
torc::bitstream::Virtex7::EFarBlockType
EFarBlockType
Frame Address Register block type constants.
Definition: Virtex7.hpp:84
torc::bitstream::Bitstream::uint8_t
boost::uint8_t uint8_t
Imported type name.
Definition: bitstream/Bitstream.hpp:61
torc::bitstream::xc7k160t
DeviceInfo xc7k160t
torc::bitstream::string
std::string string
Definition: LibGenFactory.hpp:35
torc::bitstream::Virtex7::ERegister
ERegister
Configuration register enumeration.
Definition: Virtex7.hpp:55
torc::bitstream::Virtex7::sTIMER
static const Subfield sTIMER[]
Watchdog Timer Register (TIMER) subfields.
Definition: Virtex7.hpp:136
torc::bitstream::Bitstream::uint32_t
boost::uint32_t uint32_t
Imported type name.
Definition: bitstream/Bitstream.hpp:63
torc::bitstream::Virtex7::getXdlFrames
VirtexFrameBlocks getXdlFrames(uint32_t inXdlRow, uint32_t inXdlCol, uint32_t &outBeginBit, uint32_t &outEndBit, uint32_t inBlockCount=eBlockTypeCount)
Returns frames for specified XDL tile coordinates. inXldRow The XDL row coordinate. inXdlCol The XDL column coordinate. outBeginBit The bit index of the beginning of the requested tile. outEndBit The bit index of the end of the requested tile. inBlockCount The highest block type requested (8 for Xilinx architectures).
Definition: Virtex7.cpp:1252
torc::bitstream::Virtex7::makeSubfield
static uint32_t makeSubfield(ERegister inRegister, const std::string &inSubfield, const std::string &inSetting)
Return the masked value for a subfield of the specified register.
Definition: Virtex7.cpp:361
torc::bitstream::Virtex7::updateFullFrameBlocks
DEPRECATED void updateFullFrameBlocks(void)
Transfers frame block data into the full bitstream frame packet.
Definition: Virtex7.cpp:1211
torc::bitstream::Virtex7::initializeFullFrameBlocks
DEPRECATED void initializeFullFrameBlocks(void)
Loads full bitstream frames into block data structure.
Definition: Virtex7.cpp:1190
torc::bitstream::FrameBlocks< VirtexFrame >::word_t
VirtexFrame::word_t word_t
FrameSet word type.
Definition: FrameSet.hpp:85
torc::bitstream::Virtex7::sWBSTAR
static const Subfield sWBSTAR[]
Warm Boot Start Address Register (WBSTAR) subfields.
Definition: Virtex7.hpp:134
torc::bitstream::Virtex7::mTopRowCount
uint32_t mTopRowCount
The number of top bitstream rows.
Definition: Virtex7.hpp:140
torc::bitstream::Bitstream::mDeviceName
string mDeviceName
Header device name.
Definition: bitstream/Bitstream.hpp:234
torc::bitstream::Virtex7::mFrameIndexToAddress
FrameIndexToAddress mFrameIndexToAddress
Map of frame indexes to frame addresses.
Definition: Virtex7.hpp:413
torc::bitstream::Virtex7::sCOR1
static const Subfield sCOR1[]
Configurations Options Register 1 (COR) subfields.
Definition: Virtex7.hpp:124
torc::bitstream::Virtex7::FrameRowDesignator::mColumnVectorBase
uint32_t mColumnVectorBase
Offset for this row into the column type vector.
Definition: Virtex7.hpp:372
torc::bitstream::Bitstream::mDeviceInfo
DeviceInfo mDeviceInfo
Device information.
Definition: bitstream/Bitstream.hpp:257
torc::architecture::Tiles
Tile map, tile type, and wire information for the family and device.
Definition: Tiles.hpp:36
torc::bitstream::xc7k70t
DeviceInfo xc7k70t
torc::bitstream::FrameBlocks::mBlock
FrameSet< FRAME_TYPE > mBlock[Bitstream::eBlockTypeCount]
FrameSets for each of the eight block types.
Definition: FrameSet.hpp:88
torc::architecture::xilinx::TileCount
Encapsulation of a tile count in an unsigned 32-bit integer.
Definition: XilinxDatabaseTypes.hpp:61
torc::bitstream::Virtex7::EFarTopBottom
EFarTopBottom
Frame Address Register top and bottom constants.
Definition: Virtex7.hpp:81
torc::architecture::TileInfo
Encapsulation of a tile within a device tile map.
Definition: TileInfo.hpp:33
torc::bitstream::Bitstream::EBitstreamType
EBitstreamType
The bitstream type to generate. Use eBitstreamFull to fully reconfigure a device, eBitstreamTypePartialActive to partially reconfigure it while it continues to run, or eBitstreamTypePartialShutdown to partially recongifure it after shutting it down.
Definition: bitstream/Bitstream.hpp:49
torc::bitstream::Virtex7::sPacketTypeName
static const char * sPacketTypeName[ePacketTypeCount]
Configuration controller registers.
Definition: Virtex7.hpp:114
torc::bitstream::Virtex7::sCommandName
static const char * sCommandName[eCommandCount]
Configuration Command names.
Definition: Virtex7.hpp:120
torc::architecture::Tiles::getTileTypeName
const char * getTileTypeName(TileTypeIndex inTileTypeIndex) const
Returns the tile type name for the given tile type index.
Definition: Tiles.hpp:164
torc::bitstream::DeviceInfo::getColumnTypes
const ColumnTypeVector & getColumnTypes(void) const
Returns the column type vector.
Definition: DeviceInfo.hpp:116
torc::bitstream::Virtex7::mXdlColumnIndexes
IndexVector mXdlColumnIndexes[Virtex7::eFarBlockTypeCount]
Vector to store frame indexes of Bitstream columns.
Definition: Virtex7.hpp:419
torc::bitstream::xc7vx1140t
DeviceInfo xc7vx1140t
torc::bitstream::path
boost::filesystem::path path
Definition: LibGenFactory.hpp:36
torc::architecture::TileInfo::getTypeIndex
const TileTypeIndex & getTypeIndex(void) const
Returns the tile type index for this tile.
Definition: TileInfo.hpp:92
torc::bitstream::Virtex7::mFrameRowCount
uint32_t mFrameRowCount
Number of frame rows.
Definition: Virtex7.hpp:425
torc::bitstream::xc7z030
DeviceInfo xc7z030
torc::bitstream::FrameSet< VirtexFrame >::FrameSharedPtr
boost::shared_ptr< VirtexFrame > FrameSharedPtr
Shared pointer encapsulation of a Frame.
Definition: FrameSet.hpp:44
torc::bitstream::Virtex7::setRowCounts
void setRowCounts(const string &inDeviceName)
Set the number of top and bottom bitstream rows.
Definition: Virtex7.cpp:670
torc::bitstream::VirtexPacketVector
std::vector< VirtexPacket > VirtexPacketVector
Vector of Virtex packets.
Definition: VirtexPacket.hpp:265
torc::bitstream::Virtex7::sCTL1
static const Subfield sCTL1[]
Control Register 1 (CTL) subfields.
Definition: Virtex7.hpp:130
torc::bitstream::xc7vx980t
DeviceInfo xc7vx980t
torc::bitstream::Virtex7::getFrameRowCount
virtual uint32_t getFrameRowCount(void) const
Return the number of frame rows for the current device.
Definition: Virtex7.hpp:302
torc::bitstream::VirtexPacket::makeType1Write
static VirtexPacket makeType1Write(uint32_t inAddress, uint32_t inWord)
Construct a type 1 write packet.
Definition: VirtexPacket.hpp:192
torc::common::DirectoryTree::getWorkingPath
static const boost::filesystem::path & getWorkingPath(void)
Returns the absolute path to the working directory.
Definition: DirectoryTree.hpp:56
torc::architecture::xilinx::TileTypeCount
Encapsulation of a tile type count in an unsigned 16-bit integer.
Definition: XilinxDatabaseTypes.hpp:106
torc::bitstream::VirtexPacket::getWords
const WordSharedArray getWords(void) const
brief Returns the raw packet words, including the header word.
Definition: VirtexPacket.hpp:250
torc::bitstream::xc7k325t
DeviceInfo xc7k325t
torc::bitstream::xc7k480t
DeviceInfo xc7k480t
torc::architecture::Tiles::getColCount
TileCol getColCount(void) const
Returns the column count for this device.
Definition: Tiles.hpp:155
torc::bitstream::VirtexFrameSharedPtr
boost::shared_ptr< VirtexFrame > VirtexFrameSharedPtr
Virtex frame type.
Definition: Frame.hpp:108
torc::bitstream::FrameSet< VirtexFrame >::word_t
VirtexFrame::word_t word_t
FrameSet word type.
Definition: FrameSet.hpp:42
torc::bitstream::Virtex7::getRowPadFrames
virtual uint32_t getRowPadFrames(void) const
Return the number of pad frames after each row.
Definition: Virtex7.hpp:306
torc::bitstream::Virtex7::mBottomRowCount
uint32_t mBottomRowCount
The number of bottom bitstream rows.
Definition: Virtex7.hpp:142
torc::architecture::xilinx::TileTypeIndex
Encapsulation of a tile type index in an unsigned 16-bit integer.
Definition: XilinxDatabaseTypes.hpp:113
torc::bitstream::Virtex7::sRegisterName
static const char * sRegisterName[eRegisterCount]
Configuration Register names.
Definition: Virtex7.hpp:118
torc::bitstream::Bitstream::uint16_t
boost::uint16_t uint16_t
Imported type name.
Definition: bitstream/Bitstream.hpp:62
torc::bitstream::Virtex7::generatePartialBitstreamPrefix
virtual VirtexPacketVector generatePartialBitstreamPrefix(EBitstreamType inBitstreamType)
Return a packet vector with the partial bitstream prefix.
Definition: Virtex7.cpp:1057
DDB.hpp
Header for the DDB class.
torc::bitstream::Virtex7::mBlockFrameIndexBounds
uint32_t mBlockFrameIndexBounds[Virtex7::eFarBlockTypeCount]
Array to hold frame index boundaries for blocks.
Definition: Virtex7.hpp:421
torc::bitstream::Virtex7::sCTL0
static const Subfield sCTL0[]
Control Register 0 (CTL) subfields.
Definition: Virtex7.hpp:128
torc::bitstream::VirtexFrameBlocks
FrameBlocks< VirtexFrame > VirtexFrameBlocks
Virtex frame blocks type.
Definition: FrameSet.hpp:91
torc::bitstream::Virtex7::EColumnType
EColumnType
Major Column Types.
Definition: Virtex7.hpp:97
torc::bitstream::Virtex7::sOpcodeName
static const char * sOpcodeName[eOpcodeCount]
Packet Opcode names.
Definition: Virtex7.hpp:116
torc::common::EncapsulatedInteger
Template base for encapsulated integers, to enforce strong typing.
Definition: EncapsulatedInteger.hpp:28
torc::bitstream::xc7a100t
DeviceInfo xc7a100t
torc::bitstream::xc7vh580t
DeviceInfo xc7vh580t
torc::bitstream::xc7a200t
DeviceInfo xc7a200t
torc::bitstream::Bitstream::setDeviceInfo
void setDeviceInfo(const DeviceInfo &rhs)
Assign static device information for the current bitstream.
Definition: bitstream/Bitstream.hpp:223
torc::bitstream::VirtexPacket
Bitstream packet for Virtex class architectures.
Definition: VirtexPacket.hpp:76
torc::bitstream::VirtexPacket::makeHeader
static uint32_t makeHeader(EPacketType inType, EOpcode inOpcode, uint32_t inAddress, uint32_t inCount)
Construct a packet header.
Definition: VirtexPacket.hpp:215
torc::bitstream::Bitstream::Subfield::mValues
const char ** mValues
The allowable subfield values.
Definition: bitstream/Bitstream.hpp:203
torc::bitstream::xc7v585t
DeviceInfo xc7v585t
torc::bitstream::Virtex7::mBitColumnIndexes
IndexVector mBitColumnIndexes[Virtex7::eFarBlockTypeCount]
Vector to store frame indexes of XDL columns.
Definition: Virtex7.hpp:417
torc::bitstream::xc7vx550t
DeviceInfo xc7vx550t
torc::bitstream::Virtex7::sCOR0
static const Subfield sCOR0[]
Configurations Options Register 0 (COR) subfields.
Definition: Virtex7.hpp:122
torc::architecture::Tiles::getTileIndex
TileIndex getTileIndex(TileRow inRow, TileCol inCol) const
Returns the tile index for the given [row,column] pair.
Definition: Tiles.hpp:161
torc::bitstream::xc7vx690t
DeviceInfo xc7vx690t
torc::bitstream::Virtex7::mFrameAddressToIndex
FrameAddressToIndex mFrameAddressToIndex
Map of frame addresses to frame indexes.
Definition: Virtex7.hpp:415
torc::bitstream::Frame::word_t
WORD_TYPE word_t
Frame word type.
Definition: Frame.hpp:48
Virtex7.hpp
Header for the Virtex7 class.
torc::bitstream::Virtex7::getBitstreamFrames
VirtexFrameBlocks getBitstreamFrames(EFarTopBottom inTopBottom, uint32_t inFrameRow, uint32_t inBitCol, uint32_t inBlockCount=eBlockTypeCount)
Returns frames for specified bitstream tile column. inTopBottom The top or bottom half of the device...
Definition: Virtex7.cpp:1235
torc::bitstream::Virtex7::initializeDeviceInfo
virtual void initializeDeviceInfo(const std::string &inDeviceName)
Initialize the Device Information.
Definition: Virtex7.cpp:416
torc::bitstream::Virtex7::generateFullBitstreamPackets
virtual VirtexPacketVector generateFullBitstreamPackets(void)
Return a packet vector with full frame data.
Definition: Virtex7.hpp:233
XilinxDatabaseTypes.hpp
Device database types for Xilinx architectures.