  std | |
   basic_istream | Forward declaration of template basic_istream |
 basic_ostream | Forward declaration of template basic_ostream |
| torc | Implementation of class to encapsulate micro-bitstream library generation code |
 architecture | Namespace for the Torc architecture support, providing device logic and wiring information, and design usage tracking |
| architecture | |
| xilinx | Namespace for Xilinx architecture support |
| WireCount | Encapsulation of a wire count in an unsigned 16-bit integer |
| WireIndex | Encapsulation of a wire index in an unsigned 16-bit integer |
| WireFlags | Encapsulation of wire attribute flags in an unsigned 16-bit integer |
| TileCount | Encapsulation of a tile count in an unsigned 32-bit integer |
| TileIndex | Encapsulation of a tile index in an unsigned 32-bit integer |
| TileOffset | Encapsulation of a tile offset in an unsigned 32-bit integer |
| TileRow | Encapsulation of a tile row in an unsigned 16-bit integer |
| TileCol | Encapsulation of a tile column in an unsigned 16-bit integer |
| TileTypeCount | Encapsulation of a tile type count in an unsigned 16-bit integer |
| TileTypeIndex | Encapsulation of a tile type index in an unsigned 16-bit integer |
| CompactSegmentCount | Encapsulation of a compact segment count in an unsigned 32-bit integer |
| CompactSegmentIndex | Encapsulation of a compact segment index in an unsigned 32-bit integer |
| SiteCount | Encapsulation of a site count in an unsigned 32-bit integer |
| SiteIndex | Encapsulation of a site index in an unsigned 32-bit integer |
| SiteFlags | Encapsulation of site attribute flags in an unsigned 16-bit integer |
| SiteTypeCount | Encapsulation of a site type count in an unsigned 16-bit integer |
| SiteTypeIndex | Encapsulation of a site type index in an unsigned 16-bit integer |
| PinCount | Encapsulation of a pin count in an unsigned 32-bit integer |
| PinIndex | Encapsulation of a pin index in an unsigned 32-bit integer |
| PinFlags | Encapsulation of pin attribute flags in an unsigned 16-bit integer |
| PackageCount | Encapsulation of a package count in an unsigned 16-bit integer |
| PackageIndex | Encapsulation of a package index in an unsigned 16-bit integer |
| PadCount | Encapsulation of a pad count in an unsigned 32-bit integer |
| PadIndex | Encapsulation of a pad index in an unsigned 32-bit integer |
| Arc | Encapsulation of an arc between two tilewires |
| InvalidArcException | |
| ArcUsage | Encapsulation the design arc usage |
| Array | Encapsulation of a static array |
| Array2D | Encapsulation of a 2D static array |
| DDB | Device database, including complete wiring and logic support |
| DDBConsoleStreams | Device database console streams class |
| DDBStreamHelper | Device database stream helper class |
| DigestStream | Encapsulation of a device or family digest stream |
| ExtendedWireInfo | Verbose encapsulation of a wire's information |
| InstancePin | Physical design instance-pin pair, suitable for specifying a net endpoint |
| Package | Encapsulation of a physical device package and its pins |
| Pad | Encapsulation of the site index, pin name, and pin flags for a package |
| PrimitiveConn | Encapsulation of a PrimitiveDef internal connection. This class is analogous to a permanent net with one and only source pin. All PrimitiveConn objects are initialized from a family database by the Sites class |
| PrimitiveDef | Encapsulation of primitive site definition, with associated connections, elements, and pins |
| PrimitiveElement | Encapsulation of a primitive site element. Primitive elements are subcomponents of logic primitive sites |
| PrimitiveElementPin | Encapsulation of a primitive element pin's name, flags, and element pointer. Primitive element pins are sub-site inputs or outputs |
| PinDirection | |
| PrimitivePin | Encapsulation of a primitive pin's name and flags. Primitive pins are logic site inputs or outputs |
| Segments | Segment and irregular arc data for the device |
| CompactSegmentTilewire | Encapsulation of a wire belonging to a compact segment |
| IrregularArc | Encapsulation of an irregular arc |
| SegmentReference | Encapsulation of compact segment index and an anchoring tile index |
| segments_regression_test_helper | Regression test class for segments consistency across all devices |
| segments_unit_test_helper | |
| Site | Encapsulation of a device logic site |
| Sites | Site type and population data for the family and the device |
| TileInfo | Encapsulation of a tile within a device tile map |
| Tiles | Tile map, tile type, and wire information for the family and device |
| CharStringWrapper | Wrapper around char* for use with the Array template |
| Tilewire | Encapsulation of a device tile and wire pair |
| Versions | Encapsulation of database version information |
| VprExporter | Device database exporter for the University of Toronto's VPR |
| Node | VPR node temporary class |
| WireArray | Array of wire indexes |
| WireInfo | Encapsulation of a wire within a tile type |
| WireUsage | Encapsulation the design wire usage |
| XdlImporter | Architecture aware importer from XDL format into a physical design |
| bitstream | Namespace for the Torc bitstream frame-level support, including packet parsing and writing |
| bitstream | |
| Assembler | Base class for bitstream assembly |
| AssemblerFactory | Helper class for bitstreams |
| AssemblerLibGen | |
| LibGenFactory | Helper class for bitstreams |
| Virtex5LibGen | |
| Virtex7LibGen | |
| Virtex5Assembler | |
| Virtex7Assembler | |
| VirtexAssembler | Base Virtex class to implement functions common across all/some Virtex architectures |
| Bitstream | Xilinx bitstream base class |
| Subfield | |
| DeviceInfoHelper | Xilinx bitstream base class |
| Spartan6BuildHelper | Xilinx bitstream base class |
| ColumnDef | Bitstream column definition for Xilinx bitstreams. For every block type 0 through 8, this class provides the width of the specified column in minor frames. Note that in most families, block types beyond 3 or 4 are unused, and hence of zero width |
| ColumnDefVector | Column definition vector |
| ColumnTypeVector | Column type vector |
| DeviceInfo | Static device information class for Xilinx bitstreams. This class facilitates the creation of frame address maps without dependence upon torc::architecture |
| Factory | Helper class for bitstreams |
| Frame | Bitstream frame |
| FrameSet | Set of contiguous frames |
| FrameBlocks | Set of contiguous frames for each of the eight possible block types |
| Hex16 | |
| Hex32 | |
| Spartan3E | Spartan3E bitstream |
| FrameAddress | |
| Spartan6 | Spartan6 bitstream |
| FrameMajorAddress | |
| FrameMinorAddress | |
| Spartan6Bitstream | Spartan-class bitstream |
| CRC | CRC class for the Spartan6 architecture |
| Spartan6PacketConstants | Bitstream packet constants for Spartan 16 bit class architectures |
| Spartan6Packet | Bitstream packet for Spartan 16 bit class architectures |
| SpartanBitstream | Spartan-class bitstream |
| SpartanPacketConstants | Bitstream packet constants for Spartan class architectures |
| SpartanPacket | Bitstream packet for Spartan class architectures |
| Virtex | Virtex bitstream |
| FrameAddress | |
| Virtex2 | Virtex2 bitstream |
| FrameAddress | |
| Virtex2P | Virtex2P bitstream inherited from Virtex2 bitstream |
| Virtex4 | Virtex4 bitstream |
| FrameAddress | |
| Virtex5 | Virtex5 bitstream |
| FrameAddress | |
| FrameRowDesignator | Frame row designator: top/bottom flag and row index |
| Virtex6 | Virtex6 bitstream |
| FrameAddress | |
| Virtex7 | Virtex7 bitstream |
| FrameAddress | |
| FrameRowDesignator | Frame row designator: top/bottom flag and row index |
| VirtexBitstream | Virtex-class bitstream |
| VirtexE | VirtexE bitstream inherited from Virtex bitstream |
| VirtexFrameAddress | Virtex Frame Address base-class |
| VirtexPacketConstants | Bitstream packet constants for Virtex class architectures |
| VirtexPacket | Bitstream packet for Virtex class architectures |
| common | |
| Annotated | Concept for any object that can be annotated |
| DeviceDesignator | Encapsulation of a device designator and its constituent elements |
| DeviceFamilyHelper | Helper class to initialize device map and list information |
| Devices | Encapsulation of filesystem paths that are used by the library |
| DirectoryTree | Encapsulation of filesystem paths that are used by the library |
| DottedVersion | Encapsulation of dotted decimal DottedVersion numbers |
| EncapsulatedInteger | Template base for encapsulated integers, to enforce strong typing |
| NullStreamBuffer | Null stream buffer used by NullOutputStream |
| NullOutputStream | Output stream that discards everything it receives |
| generic | Namespace for the Torc generic netlist, including EDIF and BLIF importers and exporters |
| _impl | |
| Copier | |
| Copier< class Root > | |
| Copier< class Design > | |
| Copier< class Library > | |
| Copier< class Cell > | |
| Copier< class Status > | |
| Copier< class SimulationInfo > | |
| Copier< class LogicValue > | |
| Copier< class View > | |
| Copier< class ScalarPort > | |
| Copier< class ScalarPortReference > | |
| Copier< class VectorPort > | |
| Copier< class VectorPortReference > | |
| Copier< class PortBundle > | |
| Copier< class PortBundleReference > | |
| Copier< class SingleInstance > | |
| Copier< class ScalarNet > | |
| Copier< class NetBundle > | |
| Copier< class VectorNet > | |
| Copier< class InstanceArray > | |
| Copier< class SingleParameter > | |
| Copier< class ParameterArray > | |
| Copier< class Property > | |
| Copier< class Port > | |
| Copier< class PortReference > | |
| Copier< class Net > | |
| Copier< class Instance > | |
| Copier< class Parameter > | |
| Copier< class Permutable > | |
| Copier< class InterfaceJoinedInfo > | |
| Copier< class PortList > | |
| Copier< class Simulate > | |
| Copier< class LogicalResponse > | |
| Copier< class Timing > | |
| Copier< class ForbiddenEvent > | |
| Copier< class Event > | |
| Copier< class LogicElement > | |
| generic | |
| Apply | This class is used within simulate to describe input stimuli and expected responces over a certain time interval |
| Factory | |
| Bundle | Represents a "bundle" in the EDIF sense |
| BundleFlattener | Flatten a bundle to bits |
| Cell | Represents an EDIF cell |
| Factory | |
| Cloneable | Represents all EOM classes that can be cloned(copied) |
| Commentable | Represents all classes that can hold user comments |
| Composite | Interface for objects that can be composed within each other |
| Connectable | An object that is connectable to a Net |
| ConnectionHandler | |
| Design | |
| Factory | |
| Decompiler | |
| Driver | |
| EdifContext | |
| EdifParser | The Top level parser for parsing EDIF files |
| Linker | Represents a repository of unresolved usage references |
| NameSpec | |
| UnresolvedInstances | |
| location | Abstract a location |
| ObjectVisitor | |
| Parser | A Bison parser |
| semantic_type | Symbol semantic values |
| token | Tokens |
| NameData | |
| ArrayData | |
| ViewRefData | |
| CellRefData | |
| LogicRefData | |
| InstanceRefData | |
| PortRefData | |
| NetRefData | |
| PortInstData | |
| PortListData | |
| VersionData | |
| ValueData | |
| PairData | |
| PairStrData | |
| ParamAssignInfo | |
| InstanceInfo | |
| LogicListData | |
| ParserOptions | |
| position | Abstract a position |
| Scanner | |
| stack | |
| slice | Present a slice of the top of a stack |
| EdifVersion | |
| Error | The Error object thrown by different methods of EdifOM |
| StackFrameInfo | |
| Event | Event is used to describe an event on a port or a net using logic state transitions. Events can also be described for unordered groups of ports or nets using portGroup or netGroup. An ordered list of ports may also be used using a portList |
| Factory | |
| Extern | Used to implement external object referencing |
| FactoryType | A placeholder for a factory method |
| ForbiddenEvent | ForbiddenEvent class lists events which are forbidden during a period of times which is specified by time interval. Time interval is used to describe an interval between two times. Times can be described by events or offset events |
| Factory | |
| Instance | Represents an instantiation of a cell view in the view of another cell |
| MasterData | |
| InstanceArray | Represents an array of instances |
| Factory | |
| InstanceArrayMember | Represents a member of an instance array |
| InterfaceAttributes | Represents attributes of a view interface |
| InterfaceJoinedInfo | Represents the Interface joining information |
| Factory | |
| IndexFinder | |
| Library | An EDIF cell library |
| Factory | |
| LogicalResponse | This class is used to model logicInput/logicOutput construct. This class holds information of logical response to be expected from a ports during simulation |
| Factory | |
| LogicElement | Represents different logic elements which holds array of logic values |
| Factory | |
| LogicValue | This class is used within simulationInfo construct to define a logic value to use for modeling in the logicModel view |
| Factory | |
| LogicValueAttributes | This class is used within simulationInfo construct to define a logic value to use for modeling |
| LogicMap | This structure is for logicRef and libraryRef used in logicMapInput/logicMapOutput |
| Message | |
| MessageTable | |
| Nameable | An object that has a name |
| Net | Represents an EDIF Net |
| NetAttributes | Represents attributes of a Net object |
| NetBundle | Represents a bundle of nets |
| Factory | |
| NetDelay | Represents the netDelay attribute of Net |
| ObjectFactory | |
| VisitNet | |
| Parameter | Represents a parameter object in EDIF |
| ParameterArray | Represents a parameter array |
| Factory | |
| ParameterArrayElement | |
| ParameterMap | |
| ParamData | |
| ParentedObject | An object that has a parent |
| PathDelay | This class associates a delay with a specified chain of events. Delay contains the time from first event to final event |
| Factory | |
| Permutable | Permutable is used to describe a relationship in which ports are interchangeable |
| Factory | |
| Port | Interface for an EDIF port object |
| PortAttributes | Represents attributes of a Port or PortReference object |
| PortBundle | Represents a bundle of ports |
| Factory | |
| PortBundleReference | Represents a reference to a bundle of ports |
| Factory | |
| PortDelay | Represents the portDelay attribute on Port or PortReference |
| PortElement | Represents port element like port or port reference |
| PortList | Represents an ordered list of port references |
| Factory | |
| PortListAlias | Represents an ordered list of port references with a name aliased |
| Factory | |
| PortRefCreator | Create port reference |
| PortReference | Represents the usable instance of a port of a cell in another cell |
| Property | |
| Factory | |
| PropertyContainer | Represents objects that have properties |
| Renamable | Represents objects that can be renamed |
| Root | Root of the EDIF Object Model |
| Factory | |
| Scalar | A single object with no child objects |
| ScalarNet | Represents a standalone net |
| Factory | |
| ScalarPort | Represents a standalone port |
| Factory | |
| ScalarPortReference | Represents areference to a standalone port |
| Factory | |
| ScaleFactor | |
| SelfReferencing | |
| Simulate | This class is to model simulate construct which is a named collection of simulation stimulus and responses statements and is used in the interface and contents of views |
| Factory | |
| SimulationInfo | This class is used to hold all information about the logic values used within a library |
| Factory | |
| SingleInstance | Represents a single instance of the view of a cell |
| Factory | |
| SingleParameter | |
| Factory | |
| Status | Represents EDIF status construct |
| Factory | |
| StatusContainer | Represents objects that have status |
| SymTab | A symbol table |
| Data | |
| TimeStamp | Represents the time in Universal Time Coordinate (year, month, day, hour, minute, second) |
| Timing | This class is used to provide a set of path delays or timing constrains (forbidden events) |
| Factory | |
| UserDataContainer | Represents class that can hold userData |
| Value | |
| MiNoMax | |
| Number | |
| Point | |
| Vector | An array of objects |
| VectorBit | Represents a single element of a vector composition |
| VectorNet | Represents a net array |
| Factory | |
| VectorNetBit | Represents a bit of a net array |
| VectorPort | Represents a port array |
| Factory | |
| VectorPortBit | Represents a bit of a port |
| VectorPortBitReference | Represents a reference to a bit of a port |
| VectorPortReference | Represents a reference to a port array |
| Factory | |
| TemporaryAssignment | Template class that stores the current value of a variable and restores that value when this object goes out of scope |
| VerilogExporter | Exporter from a generic netlist into structural verilog |
| VerilogExporterVisitor | Generic netlist object visitor for output as structural Verilog |
| VerilogImporter | Importer from structural verilog format into a generic design |
| VerilogImporterVisitor | AST visitor to convert structural Verilog into a generic design |
| VerilogNames | Encapsulation of library names used for Verilog importing and exporting |
| View | Represents and EDIF View |
| Factory | |
| Visitable | An object that receives an inoutVisitor |
| VisitorApplier | |
| BaseVisitor | A base class for Visitor |
| VisitorType | An acyclic inoutVisitor implementation |
| WaveValue | This class is used within simulate to describe input stimuli and expected responces over a certain time interval |
| Factory | |
| Written | Represents an information container relating to the writer of the EDIF file |
| Factory | |
| EdifImporter | |
| EdifExporter | |
| packer | |
| architecture | |
| packer | |
| PrimitiveStructure | Encapsulation of the site index, pin name, and pin flags for a package |
| Unpacker | |
| Virtex2PrimitiveStructure | Subclass of PrimitiveStructure for Virtex2 and Virtex2P |
| Virtex5PrimitiveStructure | Subclass of PrimitiveStructure for Virtex5 |
| Virtex7PrimitiveStructure | Subclass of PrimitiveStructure for Virtex7 |
| physical | Namespace for the Torc physical netlist, including the XDL importer, exporter, placer, router, unpacker, and packer |
| physical | |
| CombinationalPath | Routing net |
| Component | Hierarchical componenet |
| Connection | Hierarchical componenet |
| ConnectionPin | Physical design connection-pin pair, suitable for specifying a net endpoint |
| Element | Element composed of connections and pins |
| ParsePrimitive | Pare Primitives |
| Primitive | Primitive |
| PrimitivePin | Physical design primitive-pin |
| PrimitiveSet | PrimitiveSet |
| RcFactory | RcFactory class for physical netlist elements |
| RoutingNet | Routing net |
| WritePrimitive | Pare Primitives |
| XdlUnpack | |
| Circuit | Circuit composed of instances and nets |
| RenamableInstance | |
| Config | Configuration. A {name:value} pair |
| ConfigMap | Configuration setting map |
| Design | Physical netlist design |
| Factory | Factory class for physical netlist elements |
| Instance | Physical design instance |
| InstancePinBase | Physical design instance-pin pair, suitable for specifying a net endpoint |
| InstancePin | Physical design instance-pin pair, suitable for specifying a net endpoint |
| InstanceReference | Instantiation of a module instance |
| Module | Hierarchical module |
| ModuleTransformer | Utility class to modularize/flatten designs |
| Named | Concept for any object that can be named |
| NameComparator | Comparator class to serve as a predicate when searching for names |
| Net | Physical design net |
| Pip | Physical design programmable interconnect point |
| Port | Module input or output port |
| PortTemp | Temporary module port |
| Progenitor | Concept for any object that may have children |
| Progeny | Concept for any object that may have a parent |
| Renamable | Concept for any object that can be renamed |
| Routethrough | Pip routethrough |
| TilewirePlaceholder | Drop-in placeholder for a Tilewire with no torc::architecture dependencies |
| XdlExporter | Physical design exporter for XDL |
| XdlImporter | Importer from XDL format into a physical design |
| WireName | Encapsulation of a wire name |
| TileName | Encapsulation of a tile name |
| TileTypeName | Encapsulation of a tile type name |
| InstanceName | Encapsulation of an instance name |
| SiteName | Encapsulation of a site name |
| SiteTypeName | Encapsulation of a site type name |
| PinName | Encapsulation of a site pin name |
| placer | |
| DeviceSite | |
| DeviceSitePin | |
| DeviceSiteType | |
| DeviceSiteTypePin | |
| DeviceWrapper | Wrapper of the device database for placing the design |
| NetlistInstance | |
| NetlistNet | |
| NetlistPin | |
| Placement | Wrapper of the Design for placing the design |
| PlacementSiteTypeMapping | Placement mapping for legal instance types to site types |
| MappingSiteType | |
| PlacementSiteTypeMappingVirtex5 | Placement mapping for legal instance types to site types |
| Placer | Simulated annealing algorithm class |
| PlacerHeuristicBase | Simulated annealing algorithm class |
| PlacerHeuristicVirtex5 | Simulated annealing algorithm class |
| PlacerNetlist | |
| router | |
| NetRouter | Provides net routing based on the Nilsson graphsearch algorithm |
| NetRouterBase | Abstract class for a net router |
| NetRouterHeuristic | Provides net routing based on the Nillson graphsearch algorithm |
| NetRouterHeuristicBase | Provides the interface for net routers |
| NetVectorRouterBase | Abstract class for a net router |
| NetVectorRouterHeuristicBase | Provides net routing based on the Nillson graphsearch algorithm |
| TilewireData | Pathfinder annotations for Tilewires |
| PathFinder | |
| PathFinderHeuristic | Provides net routing based on the Nillson graphsearch algorithm |
| PathFinderNetRouterHeuristic | Provides net routing based on the Nillson graphsearch algorithm |
| RouteNet | Router net |
| RouteNode | An object that holds an arc and path information for routing |
| RouteNodePtrCostCompare | Binary predicate for comparing RouteNode pointers based on cost |
| RouterHeuristicBase | Provides the interface for net routers |
| RouterStatistics | Router Statistics net |
| RouteTreeNode | An object that holds more complete path information for routing and tracing |
| RouteUtilities | Router net |
| Trace | Provides path extraction from usage information in a DDB instance. |
| TraceNode | An object that holds more complete path information for routing and tracing |
| TraceVirtex5TestFixture | |
| TraceVirtexTristateTestFixture | |
| TraceUnitTestFixture | |
| Unrouter | Unroutes connected resources in a DDB instance |
| TracerTestFixture | |
| utils | |
| location | Abstract a location |
| LutParser | A Bison parser |
| token | Tokens |
| LutScanner | |
| position | Abstract a position |
| stack | Bison stack class |
| slice | Present a slice of the top of a stack |
| XdlParser | A Bison parser |
| token | Tokens |
| XdlScanner | |
| ArchitectureBrowser | Utility class for exploring database contents |
| MarkExtracter | Diff utility class for comparing physical netlists |
| PhysicalDiff | Diff utility class for comparing physical netlists |
| DebugFilter | Test suite visitor to disable tests for debugging |
| FlexLexer | |
| RegressionFilter | Test suite visitor to disable regression tests |
| s_rr_node | |
| TestFixture | Convenience test fixture struct to request desired logging level from Boost.Test |
| yy_buffer_state | Bison parser internals |
| yy_trans_info | Bison parser internals |
| yyFlexLexer | |
1.8.6 
