- r -

• reduce_counter : freduce.cc
• reduce_stop_at : freduce.cc
• reg_ct : verilog_backend.cc
• reg_wires : verilog_backend.cc
• RenamePass : rename.cc
• rtlil_frontend_ilang_yy_flex_debug : ilang_lexer.cc
• rtlil_frontend_ilang_yydebug : ilang_parser.tab.cc , ilang_parser.tab.h , ilang_frontend.h
• rtlil_frontend_ilang_yyin : ilang_lexer.cc
• rtlil_frontend_ilang_yyleng : ilang_lexer.cc
• rtlil_frontend_ilang_yylineno : ilang_lexer.cc
• rtlil_frontend_ilang_yylval : ilang_parser.tab.h , ilang_parser.tab.cc
• rtlil_frontend_ilang_yyout : ilang_lexer.cc
• rtlil_frontend_ilang_yytext : ilang_lexer.cc