Go to the source code of this file.
Definition at line 27 of file rename.cc.
   35     for (
auto &it : module->
wires_)
 
   36         if (it.first == from_name) {
 
   38             module->
rename(it.second, to_name);
 
   39             if (it.second->port_id)
 
   44     for (
auto &it : module->
cells_)
 
   45         if (it.first == from_name) {
 
   47             module->
rename(it.second, to_name);
 
const char * c_str() const 
std::map< RTLIL::IdString, RTLIL::Wire * > wires_
static std::string escape_id(std::string str)
void log_cmd_error(const char *format,...)
virtual size_t count_id(RTLIL::IdString id)
std::map< RTLIL::IdString, RTLIL::Cell * > cells_
void log(const char *format,...)
const char * log_id(RTLIL::IdString str)
void rename(RTLIL::Wire *wire, RTLIL::IdString new_name)