#include "kernel/log.h"
#include "kernel/register.h"
#include "kernel/sigtools.h"
#include "kernel/consteval.h"
#include "kernel/celltypes.h"
#include "fsmdata.h"

Include dependency graph for fsm_detect.cc:

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Data Structures
struct	FsmDetectPass

Typedefs
typedef std::pair< RTLIL::Cell *, RTLIL::IdString >	sig2driver_entry_t

Functions
static bool	check_state_mux_tree (RTLIL::SigSpec old_sig, RTLIL::SigSpec sig, SigPool &recursion_monitor)

static bool	check_state_users (RTLIL::SigSpec sig)

static void	detect_fsm (RTLIL::Wire *wire)

Variables
USING_YOSYS_NAMESPACE static PRIVATE_NAMESPACE_BEGIN RTLIL::Module *	module

static SigMap	assign_map

static SigSet< sig2driver_entry_t >	sig2driver

static SigSet< sig2driver_entry_t >	sig2user

static std::set< RTLIL::Cell * >	muxtree_cells

static SigPool	sig_at_port

FsmDetectPass	FsmDetectPass

Typedef Documentation

typedef std::pair<RTLIL::Cell*, RTLIL::IdString> sig2driver_entry_t

Definition at line 32 of file fsm_detect.cc.

Function Documentation

static bool check_state_mux_tree	(	RTLIL::SigSpec	old_sig,
		RTLIL::SigSpec	sig,
		SigPool &	recursion_monitor
	)

static

Definition at line 37 of file fsm_detect.cc.

 {
     if (sig_at_port.check_any(assign_map(sig)))
         return false;
 
     if (sig.is_fully_const() || old_sig == sig)
         return true;
 
     if (recursion_monitor.check_any(sig)) {
         log_warning("logic loop in mux tree at signal %s in module %s.\n",
                 log_signal(sig), RTLIL::id2cstr(module->name));
         return false;
     }
 
     recursion_monitor.add(sig);
 
     std::set<sig2driver_entry_t> cellport_list;
     sig2driver.find(sig, cellport_list);
     for (auto &cellport : cellport_list) {
         if ((cellport.first->type != "$mux" && cellport.first->type != "$pmux") || cellport.second != "\\Y")
             return false;
         RTLIL::SigSpec sig_a = assign_map(cellport.first->getPort("\\A"));
         RTLIL::SigSpec sig_b = assign_map(cellport.first->getPort("\\B"));
         if (!check_state_mux_tree(old_sig, sig_a, recursion_monitor))
             return false;
         for (int i = 0; i < sig_b.size(); i += sig_a.size())
             if (!check_state_mux_tree(old_sig, sig_b.extract(i, sig_a.size()), recursion_monitor))
                 return false;
         muxtree_cells.insert(cellport.first);
     }
 
     recursion_monitor.del(sig);
 
     return true;
 }

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static bool check_state_users ( RTLIL::SigSpec sig )

static

Definition at line 73 of file fsm_detect.cc.

 {
     if (sig_at_port.check_any(assign_map(sig)))
         return false;
 
     std::set<sig2driver_entry_t> cellport_list;
     sig2user.find(sig, cellport_list);
     for (auto &cellport : cellport_list) {
         RTLIL::Cell *cell = cellport.first;
         if (muxtree_cells.count(cell) > 0)
             continue;
         if (cellport.second != "\\A" && cellport.second != "\\B")
             return false;
         if (!cell->hasPort("\\A") || !cell->hasPort("\\B") || !cell->hasPort("\\Y"))
             return false;
         for (auto &port_it : cell->connections())
             if (port_it.first != "\\A" && port_it.first != "\\B" && port_it.first != "\\Y")
                 return false;
         if (assign_map(cell->getPort("\\A")) == sig && cell->getPort("\\B").is_fully_const())
             continue;
         if (assign_map(cell->getPort("\\B")) == sig && cell->getPort("\\A").is_fully_const())
             continue;
         return false;
     }
 
     return true;
 }

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static void detect_fsm ( RTLIL::Wire * wire )

static

Definition at line 101 of file fsm_detect.cc.

 {
     if (wire->attributes.count("\\fsm_encoding") > 0 || wire->width <= 1)
         return;
     if (sig_at_port.check_any(assign_map(RTLIL::SigSpec(wire))))
         return;
 
     std::set<sig2driver_entry_t> cellport_list;
     sig2driver.find(RTLIL::SigSpec(wire), cellport_list);
     for (auto &cellport : cellport_list) {
         if ((cellport.first->type != "$dff" && cellport.first->type != "$adff") || cellport.second != "\\Q")
             continue;
         muxtree_cells.clear();
         SigPool recursion_monitor;
         RTLIL::SigSpec sig_q = assign_map(cellport.first->getPort("\\Q"));
         RTLIL::SigSpec sig_d = assign_map(cellport.first->getPort("\\D"));
         if (sig_q == RTLIL::SigSpec(wire) && check_state_mux_tree(sig_q, sig_d, recursion_monitor) && check_state_users(sig_q)) {
             log("Found FSM state register %s in module %s.\n", wire->name.c_str(), module->name.c_str());
             wire->attributes["\\fsm_encoding"] = RTLIL::Const("auto");
             return;
         }
     }
 }