SplicePass Struct Reference

Inheritance diagram for SplicePass:

Collaboration diagram for SplicePass:

Public Member Functions
	SplicePass ()
virtual void	help ()
virtual void	execute (std::vector< std::string > args, RTLIL::Design *design)
pre_post_exec_state_t	pre_execute ()
void	post_execute (pre_post_exec_state_t state)
void	cmd_log_args (const std::vector< std::string > &args)
void	cmd_error (const std::vector< std::string > &args, size_t argidx, std::string msg)
void	extra_args (std::vector< std::string > args, size_t argidx, RTLIL::Design *design, bool select=true)
virtual void	run_register ()

Static Public Member Functions
static void	call (RTLIL::Design *design, std::string command)
static void	call (RTLIL::Design *design, std::vector< std::string > args)
static void	call_on_selection (RTLIL::Design *design, const RTLIL::Selection &selection, std::string command)
static void	call_on_selection (RTLIL::Design *design, const RTLIL::Selection &selection, std::vector< std::string > args)
static void	call_on_module (RTLIL::Design *design, RTLIL::Module *module, std::string command)
static void	call_on_module (RTLIL::Design *design, RTLIL::Module *module, std::vector< std::string > args)
static void	init_register ()
static void	done_register ()

Data Fields
std::string	pass_name
std::string	short_help
int	call_counter
int64_t	runtime_ns
Pass *	next_queued_pass

Detailed Description

Definition at line 243 of file splice.cc.

Constructor & Destructor Documentation

SplicePass::SplicePass ( )

inline

Definition at line 244 of file splice.cc.

: Pass("splice", "create explicit splicing cells") { }

Member Function Documentation

void Pass::call ( RTLIL::Design *  design, std::string  command  )

staticinherited

Definition at line 146 of file register.cc.

{
    std::vector<std::string> args;

    std::string cmd_buf = command;
    std::string tok = next_token(cmd_buf, " \t\r\n");

    if (tok.empty() || tok[0] == '#')
        return;

    if (tok[0] == '!') {
        cmd_buf = command.substr(command.find('!') + 1);
        while (!cmd_buf.empty() && (cmd_buf.back() == ' ' || cmd_buf.back() == '\t' ||
                cmd_buf.back() == '\r' || cmd_buf.back() == '\n'))
            cmd_buf.resize(cmd_buf.size()-1);
        log_header("Shell command: %s\n", cmd_buf.c_str());
        int retCode = run_command(cmd_buf);
        if (retCode != 0)
            log_cmd_error("Shell command returned error code %d.\n", retCode);
        return;
    }

    while (!tok.empty()) {
        if (tok == "#")
            break;
        if (tok.back() == ';') {
            int num_semikolon = 0;
            while (!tok.empty() && tok.back() == ';')
                tok.resize(tok.size()-1), num_semikolon++;
            if (!tok.empty())
                args.push_back(tok);
            call(design, args);
            args.clear();
            if (num_semikolon == 2)
                call(design, "clean");
            if (num_semikolon == 3)
                call(design, "clean -purge");
        } else
            args.push_back(tok);
        tok = next_token(cmd_buf, " \t\r\n");
    }

    call(design, args);
}

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void Pass::call ( RTLIL::Design *  design, std::vector< std::string >  args  )

staticinherited

Definition at line 191 of file register.cc.

{
    if (args.size() == 0 || args[0][0] == '#')
        return;

    if (echo_mode) {
        log("%s", create_prompt(design, 0));
        for (size_t i = 0; i < args.size(); i++)
            log("%s%s", i ? " " : "", args[i].c_str());
        log("\n");
    }

    if (pass_register.count(args[0]) == 0)
        log_cmd_error("No such command: %s (type 'help' for a command overview)\n", args[0].c_str());

    size_t orig_sel_stack_pos = design->selection_stack.size();
    auto state = pass_register[args[0]]->pre_execute();
    pass_register[args[0]]->execute(args, design);
    pass_register[args[0]]->post_execute(state);
    while (design->selection_stack.size() > orig_sel_stack_pos)
        design->selection_stack.pop_back();

    design->check();
}

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void Pass::call_on_module ( RTLIL::Design *  design, RTLIL::Module *  module, std::string  command  )

staticinherited

Definition at line 240 of file register.cc.

{
    std::string backup_selected_active_module = design->selected_active_module;
    design->selected_active_module = module->name.str();
    design->selection_stack.push_back(RTLIL::Selection(false));
    design->selection_stack.back().select(module);

    Pass::call(design, command);

    design->selection_stack.pop_back();
    design->selected_active_module = backup_selected_active_module;
}

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void Pass::call_on_module ( RTLIL::Design *  design, RTLIL::Module *  module, std::vector< std::string >  args  )

staticinherited

Definition at line 253 of file register.cc.

{
    std::string backup_selected_active_module = design->selected_active_module;
    design->selected_active_module = module->name.str();
    design->selection_stack.push_back(RTLIL::Selection(false));
    design->selection_stack.back().select(module);

    Pass::call(design, args);

    design->selection_stack.pop_back();
    design->selected_active_module = backup_selected_active_module;
}

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void Pass::call_on_selection ( RTLIL::Design *  design, const RTLIL::Selection &  selection, std::string  command  )

staticinherited

Definition at line 216 of file register.cc.

{
    std::string backup_selected_active_module = design->selected_active_module;
    design->selected_active_module.clear();
    design->selection_stack.push_back(selection);

    Pass::call(design, command);

    design->selection_stack.pop_back();
    design->selected_active_module = backup_selected_active_module;
}

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void Pass::call_on_selection ( RTLIL::Design *  design, const RTLIL::Selection &  selection, std::vector< std::string >  args  )

staticinherited

Definition at line 228 of file register.cc.

{
    std::string backup_selected_active_module = design->selected_active_module;
    design->selected_active_module.clear();
    design->selection_stack.push_back(selection);

    Pass::call(design, args);

    design->selection_stack.pop_back();
    design->selected_active_module = backup_selected_active_module;
}

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void Pass::cmd_error ( const std::vector< std::string > &  args, size_t  argidx, std::string  msg  )

inherited

Definition at line 110 of file register.cc.

{
    std::string command_text;
    int error_pos = 0;

    for (size_t i = 0; i < args.size(); i++) {
        if (i < argidx)
            error_pos += args[i].size() + 1;
        command_text = command_text + (command_text.empty() ? "" : " ") + args[i];
    }

    log("\nSyntax error in command `%s':\n", command_text.c_str());
    help();

    log_cmd_error("Command syntax error: %s\n> %s\n> %*s^\n",
            msg.c_str(), command_text.c_str(), error_pos, "");
}

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void Pass::cmd_log_args ( const std::vector< std::string > &  args )

inherited

Definition at line 100 of file register.cc.

{
    if (args.size() <= 1)
        return;
    log("Full command line:");
    for (size_t i = 0; i < args.size(); i++)
        log(" %s", args[i].c_str());
    log("\n");
}

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void Pass::done_register ( )

staticinherited

Definition at line 62 of file register.cc.

{
    frontend_register.clear();
    pass_register.clear();
    backend_register.clear();
    log_assert(first_queued_pass == NULL);
}

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virtual void SplicePass::execute ( std::vector< std::string >  args, RTLIL::Design *  design  )

inlinevirtual

Implements Pass.

Definition at line 283 of file splice.cc.

    {
        bool sel_by_cell = false;
        bool sel_by_wire = false;
        bool sel_any_bit = false;
        bool no_outputs = false;
        std::set<RTLIL::IdString> ports, no_ports;

        size_t argidx;
        for (argidx = 1; argidx < args.size(); argidx++) {
            if (args[argidx] == "-sel_by_cell") {
                sel_by_cell = true;
                continue;
            }
            if (args[argidx] == "-sel_by_wire") {
                sel_by_wire = true;
                continue;
            }
            if (args[argidx] == "-sel_any_bit") {
                sel_any_bit = true;
                continue;
            }
            if (args[argidx] == "-no_outputs") {
                no_outputs = true;
                continue;
            }
            if (args[argidx] == "-port" && argidx+1 < args.size()) {
                ports.insert(RTLIL::escape_id(args[++argidx]));
                no_outputs = true;
                continue;
            }
            if (args[argidx] == "-no_port" && argidx+1 < args.size()) {
                no_ports.insert(RTLIL::escape_id(args[++argidx]));
                continue;
            }
            break;
        }
        extra_args(args, argidx, design);

        if (sel_by_cell && sel_by_wire)
            log_cmd_error("The options -sel_by_cell and -sel_by_wire are exclusive!\n");

        if (sel_by_cell && sel_any_bit)
            log_cmd_error("The options -sel_by_cell and -sel_any_bit are exclusive!\n");

        if (!ports.empty() && !no_ports.empty())
            log_cmd_error("The options -port and -no_port are exclusive!\n");

        log_header("Executing SPLICE pass (creating cells for signal splicing).\n");

        for (auto &mod_it : design->modules_)
        {
            if (!design->selected(mod_it.second))
                continue;

            if (mod_it.second->processes.size()) {
                log("Skipping module %s as it contains processes.\n", mod_it.second->name.c_str());
                continue;
            }

            SpliceWorker worker(design, mod_it.second);
            worker.sel_by_cell = sel_by_cell;
            worker.sel_by_wire = sel_by_wire;
            worker.sel_any_bit = sel_any_bit;
            worker.no_outputs = no_outputs;
            worker.ports = ports;
            worker.no_ports = no_ports;
            worker.run();
        }
    }

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void Pass::extra_args ( std::vector< std::string >  args, size_t  argidx, RTLIL::Design *  design, bool  select = true  )

inherited

Definition at line 128 of file register.cc.

{
    for (; argidx < args.size(); argidx++)
    {
        std::string arg = args[argidx];

        if (arg.substr(0, 1) == "-")
            cmd_error(args, argidx, "Unknown option or option in arguments.");

        if (!select)
            cmd_error(args, argidx, "Extra argument.");

        handle_extra_select_args(this, args, argidx, args.size(), design);
        break;
    }
    // cmd_log_args(args);
}

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virtual void SplicePass::help ( )

inlinevirtual

Reimplemented from Pass.

Definition at line 245 of file splice.cc.

    {
        //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
        log("\n");
        log("    splice [options] [selection]\n");
        log("\n");
        log("This command adds $slice and $concat cells to the design to make the splicing\n");
        log("of multi-bit signals explicit. This for example is useful for coarse grain\n");
        log("synthesis, where dedidacted hardware is needed to splice signals.\n");
        log("\n");
        log("    -sel_by_cell\n");
        log("        only select the cell ports to rewire by the cell. if the selection\n");
        log("        contains a cell, than all cell inputs are rewired, if necessary.\n");
        log("\n");
        log("    -sel_by_wire\n");
        log("        only select the cell ports to rewire by the wire. if the selection\n");
        log("        contains a wire, than all cell ports driven by this wire are wired,\n");
        log("        if necessary.\n");
        log("\n");
        log("    -sel_any_bit\n");
        log("        it is sufficient if the driver of any bit of a cell port is selected.\n");
        log("        by default all bits must be selected.\n");
        log("\n");
        log("    -no_outputs\n");
        log("        do not rewire selected module outputs.\n");
        log("\n");
        log("    -port <name>\n");
        log("        only rewire cell ports with the specified name. can be used multiple\n");
        log("        times. implies -no_output.\n");
        log("\n");
        log("    -no_port <name>\n");
        log("        do not rewire cell ports with the specified name. can be used multiple\n");
        log("        times. can not be combined with -port <name>.\n");
        log("\n");
        log("By default selected output wires and all cell ports of selected cells driven\n");
        log("by selected wires are rewired.\n");
        log("\n");
    }

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void Pass::init_register ( )

staticinherited

Definition at line 54 of file register.cc.

{
    while (first_queued_pass) {
        first_queued_pass->run_register();
        first_queued_pass = first_queued_pass->next_queued_pass;
    }
}

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void Pass::post_execute ( Pass::pre_post_exec_state_t  state )

inherited

Definition at line 84 of file register.cc.

{
    int64_t time_ns = PerformanceTimer::query() - state.begin_ns;
    runtime_ns += time_ns;
    current_pass = state.parent_pass;
    if (current_pass)
        current_pass->runtime_ns -= time_ns;
}

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Pass::pre_post_exec_state_t Pass::pre_execute ( )

inherited

Definition at line 74 of file register.cc.

{
    pre_post_exec_state_t state;
    call_counter++;
    state.begin_ns = PerformanceTimer::query();
    state.parent_pass = current_pass;
    current_pass = this;
    return state;
}

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void Pass::run_register ( )

virtualinherited

Reimplemented in Backend, and Frontend.

Definition at line 48 of file register.cc.

{
    log_assert(pass_register.count(pass_name) == 0);
    pass_register[pass_name] = this;
}

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Field Documentation

int Pass::call_counter

inherited

Definition at line 36 of file register.h.

Pass* Pass::next_queued_pass

inherited

Definition at line 60 of file register.h.

std::string Pass::pass_name

inherited

Definition at line 29 of file register.h.

int64_t Pass::runtime_ns

inherited

Definition at line 37 of file register.h.

std::string Pass::short_help

inherited

Definition at line 29 of file register.h.

---

The documentation for this struct was generated from the following file:

• splice.cc