ast.cc File Reference

#include "kernel/log.h"
#include "libs/sha1/sha1.h"
#include "ast.h"
#include <sstream>
#include <stdarg.h>
#include <math.h>

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Namespaces
	AST
	AST_INTERNAL

Macros
#define	X(_item)   case _item: return #_item;

Functions
static std::string	id2vl (std::string txt)
static AstModule *	process_module (AstNode *ast, bool defer)

Variables
std::string	AST::current_filename
void(*	AST::set_line_num )(int) = NULL
int(*	AST::get_line_num )() = NULL
bool	AST_INTERNAL::flag_dump_ast1
bool	AST_INTERNAL::flag_dump_ast2
bool	AST_INTERNAL::flag_dump_vlog
bool	AST_INTERNAL::flag_nolatches
bool	AST_INTERNAL::flag_nomem2reg
bool	AST_INTERNAL::flag_mem2reg
bool	AST_INTERNAL::flag_lib
bool	AST_INTERNAL::flag_noopt
bool	AST_INTERNAL::flag_icells
bool	AST_INTERNAL::flag_autowire
AstNode *	AST_INTERNAL::current_ast
AstNode *	AST_INTERNAL::current_ast_mod
std::map< std::string, AstNode * >	AST_INTERNAL::current_scope
const std::map< RTLIL::SigBit, RTLIL::SigBit > *	AST_INTERNAL::genRTLIL_subst_ptr = NULL
RTLIL::SigSpec	AST_INTERNAL::ignoreThisSignalsInInitial
AstNode *	AST_INTERNAL::current_top_block
AstNode *	AST_INTERNAL::current_block
AstNode *	AST_INTERNAL::current_block_child
AstModule *	AST_INTERNAL::current_module

Macro Definition Documentation

#define X

(

_item

)

case _item: return #_item;

Function Documentation

static std::string id2vl ( std::string  txt )

static

Definition at line 311 of file ast.cc.

{
    if (txt.size() > 1 && txt[0] == '\\')
        txt = txt.substr(1);
    for (size_t i = 0; i < txt.size(); i++) {
        if ('A' <= txt[i] && txt[i] <= 'Z') continue;
        if ('a' <= txt[i] && txt[i] <= 'z') continue;
        if ('0' <= txt[i] && txt[i] <= '9') continue;
        if (txt[i] == '_') continue;
        txt = "\\" + txt + " ";
        break;
    }
    return txt;
}

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static AstModule* process_module ( AstNode *  ast, bool  defer  )

static

Definition at line 873 of file ast.cc.

{
    log_assert(ast->type == AST_MODULE);

    if (defer)
        log("Storing AST representation for module `%s'.\n", ast->str.c_str());
    else
        log("Generating RTLIL representation for module `%s'.\n", ast->str.c_str());

    current_module = new AstModule;
    current_module->ast = NULL;
    current_module->name = ast->str;
    current_module->attributes["\\src"] = stringf("%s:%d", ast->filename.c_str(), ast->linenum);

    current_ast_mod = ast;
    AstNode *ast_before_simplify = ast->clone();

    if (flag_dump_ast1) {
        log("Dumping verilog AST before simplification:\n");
        ast->dumpAst(NULL, "    ");
        log("--- END OF AST DUMP ---\n");
    }

    if (!defer)
    {
        while (ast->simplify(!flag_noopt, false, false, 0, -1, false, false)) { }

        if (flag_dump_ast2) {
            log("Dumping verilog AST after simplification:\n");
            ast->dumpAst(NULL, "    ");
            log("--- END OF AST DUMP ---\n");
        }

        if (flag_dump_vlog) {
            log("Dumping verilog AST (as requested by dump_vlog option):\n");
            ast->dumpVlog(NULL, "    ");
            log("--- END OF AST DUMP ---\n");
        }

        if (flag_lib) {
            std::vector<AstNode*> new_children;
            for (auto child : ast->children) {
                if (child->type == AST_WIRE && (child->is_input || child->is_output))
                    new_children.push_back(child);
                else
                    delete child;
            }
            ast->children.swap(new_children);
            ast->attributes["\\blackbox"] = AstNode::mkconst_int(1, false);
        }

        ignoreThisSignalsInInitial = RTLIL::SigSpec();

        for (auto &attr : ast->attributes) {
            if (attr.second->type != AST_CONSTANT)
                log_error("Attribute `%s' with non-constant value at %s:%d!\n",
                        attr.first.c_str(), ast->filename.c_str(), ast->linenum);
            current_module->attributes[attr.first] = attr.second->asAttrConst();
        }
        for (size_t i = 0; i < ast->children.size(); i++) {
            AstNode *node = ast->children[i];
            if (node->type == AST_WIRE || node->type == AST_MEMORY)
                node->genRTLIL();
        }
        for (size_t i = 0; i < ast->children.size(); i++) {
            AstNode *node = ast->children[i];
            if (node->type != AST_WIRE && node->type != AST_MEMORY && node->type != AST_INITIAL)
                node->genRTLIL();
        }

        ignoreThisSignalsInInitial.sort_and_unify();

        for (size_t i = 0; i < ast->children.size(); i++) {
            AstNode *node = ast->children[i];
            if (node->type == AST_INITIAL)
                node->genRTLIL();
        }

        ignoreThisSignalsInInitial = RTLIL::SigSpec();
    }

    current_module->ast = ast_before_simplify;
    current_module->nolatches = flag_nolatches;
    current_module->nomem2reg = flag_nomem2reg;
    current_module->mem2reg = flag_mem2reg;
    current_module->lib = flag_lib;
    current_module->noopt = flag_noopt;
    current_module->icells = flag_icells;
    current_module->autowire = flag_autowire;
    current_module->fixup_ports();
    return current_module;
}

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