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memory_unpack.cc File Reference
#include "kernel/register.h"
#include "kernel/log.h"
#include <sstream>
#include <algorithm>
#include <stdlib.h>
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Data Structures

struct  MemoryUnpackPass
 

Functions

USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN void 		handle_memory (RTLIL::Module *module, RTLIL::Cell *memory)
 
void handle_module (RTLIL::Design *design, RTLIL::Module *module)
 

Variables

MemoryUnpackPass MemoryUnpackPass
 

Function Documentation

USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN void handle_memory ( RTLIL::Module *  module,
RTLIL::Cell *  memory 
)

Definition at line 29 of file memory_unpack.cc.

30 {
31  log("Creating $memrd and $memwr for memory `%s' in module `%s':\n",
32  memory->name.c_str(), module->name.c_str());
33 
34  RTLIL::IdString mem_name = RTLIL::escape_id(memory->parameters.at("\\MEMID").decode_string());
35 
36  while (module->memories.count(mem_name) != 0)
37  mem_name = mem_name.str() + stringf("_%d", autoidx++);
38 
39  RTLIL::Memory *mem = new RTLIL::Memory;
40  mem->name = mem_name;
41  mem->width = memory->parameters.at("\\WIDTH").as_int();
42  mem->start_offset = memory->parameters.at("\\OFFSET").as_int();
43  mem->size = memory->parameters.at("\\SIZE").as_int();
44  module->memories[mem_name] = mem;
45 
46  int abits = memory->parameters.at("\\ABITS").as_int();
47  int num_rd_ports = memory->parameters.at("\\RD_PORTS").as_int();
48  int num_wr_ports = memory->parameters.at("\\WR_PORTS").as_int();
49 
50  for (int i = 0; i < num_rd_ports; i++)
51  {
52  RTLIL::Cell *cell = module->addCell(NEW_ID, "$memrd");
53  cell->parameters["\\MEMID"] = mem_name.str();
54  cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS");
55  cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH");
56  cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_ENABLE")).extract(i, 1).as_const();
57  cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_POLARITY")).extract(i, 1).as_const();
58  cell->parameters["\\TRANSPARENT"] = RTLIL::SigSpec(memory->parameters.at("\\RD_TRANSPARENT")).extract(i, 1).as_const();
59  cell->setPort("\\CLK", memory->getPort("\\RD_CLK").extract(i, 1));
60  cell->setPort("\\ADDR", memory->getPort("\\RD_ADDR").extract(i*abits, abits));
61  cell->setPort("\\DATA", memory->getPort("\\RD_DATA").extract(i*mem->width, mem->width));
62  }
63 
64  for (int i = 0; i < num_wr_ports; i++)
65  {
66  RTLIL::Cell *cell = module->addCell(NEW_ID, "$memwr");
67  cell->parameters["\\MEMID"] = mem_name.str();
68  cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS");
69  cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH");
70  cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_ENABLE")).extract(i, 1).as_const();
71  cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_POLARITY")).extract(i, 1).as_const();
72  cell->parameters["\\PRIORITY"] = i;
73  cell->setPort("\\CLK", memory->getPort("\\WR_CLK").extract(i, 1));
74  cell->setPort("\\EN", memory->getPort("\\WR_EN").extract(i*mem->width, mem->width));
75  cell->setPort("\\ADDR", memory->getPort("\\WR_ADDR").extract(i*abits, abits));
76  cell->setPort("\\DATA", memory->getPort("\\WR_DATA").extract(i*mem->width, mem->width));
77  }
78 
79  module->remove(memory);
80 }
RTLIL::IdString::c_str
const char * c_str() const
Definition: rtlil.h:178
stringf
std::string stringf(const char *fmt,...)
Definition: yosys.cc:58
RTLIL::Module::addCell
RTLIL::Cell * addCell(RTLIL::IdString name, RTLIL::IdString type)
Definition: rtlil.cc:1353
RTLIL::SigSpec::as_const
RTLIL::Const as_const() const
Definition: rtlil.cc:2857
RTLIL::Cell::name
RTLIL::IdString name
Definition: rtlil.h:853
RTLIL::Cell::setPort
void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
Definition: rtlil.cc:1789
RTLIL::Module::memories
std::map< RTLIL::IdString, RTLIL::Memory * > memories
Definition: rtlil.h:601
RTLIL::Cell::parameters
std::map< RTLIL::IdString, RTLIL::Const > parameters
Definition: rtlil.h:856
RTLIL::Memory::size
int size
Definition: rtlil.h:836
RTLIL::Memory::start_offset
int start_offset
Definition: rtlil.h:836
RTLIL::escape_id
static std::string escape_id(std::string str)
Definition: rtlil.h:251
RTLIL::Cell::getPort
const RTLIL::SigSpec & getPort(RTLIL::IdString portname) const
Definition: rtlil.cc:1809
RTLIL::Memory::name
RTLIL::IdString name
Definition: rtlil.h:835
RTLIL::Module::name
RTLIL::IdString name
Definition: rtlil.h:599
NEW_ID
#define NEW_ID
Definition: yosys.h:166
RTLIL::Module::remove
void remove(const std::set< RTLIL::Wire * > &wires)
Definition: rtlil.cc:1158
log
void log(const char *format,...)
Definition: log.cc:180
RTLIL::SigSpec::extract
RTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other=NULL) const
Definition: rtlil.cc:2414
RTLIL::Memory::width
int width
Definition: rtlil.h:836
autoidx
YOSYS_NAMESPACE_BEGIN int autoidx
Definition: yosys.cc:51

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void handle_module ( RTLIL::Design *  design,
RTLIL::Module *  module 
)

Definition at line 82 of file memory_unpack.cc.

83 {
84  std::vector<RTLIL::IdString> memcells;
85  for (auto &cell_it : module->cells_)
86  if (cell_it.second->type == "$mem" && design->selected(module, cell_it.second))
87  memcells.push_back(cell_it.first);
88  for (auto &it : memcells)
89  handle_memory(module, module->cells_.at(it));
90 }
RTLIL::Design::selected
bool selected(T1 *module) const
Definition: rtlil.h:551
handle_memory
USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
Definition: memory_unpack.cc:29
RTLIL::Module::cells_
std::map< RTLIL::IdString, RTLIL::Cell * > cells_
Definition: rtlil.h:596

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Variable Documentation

MemoryUnpackPass MemoryUnpackPass